SBAS710A September   2016  – June 2017 ADS9120

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset, NAP, and PD
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Converter Module
        1. 7.3.1.1 Sample-and-Hold Circuit
        2. 7.3.1.2 External Reference Source
        3. 7.3.1.3 Internal Oscillator
        4. 7.3.1.4 ADC Transfer Function
      2. 7.3.2 Interface Module
    4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Interleaving Conversion Cycles and Data Transfer Frames
      3. 7.5.3 Data Transfer Protocols
        1. 7.5.3.1 Protocols for Configuring the Device
        2. 7.5.3.2 Protocols for Reading From the Device
          1. 7.5.3.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 7.5.3.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 7.5.3.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.3.2.3.1 Output Clock Source Options with SRC Protocols
            2. 7.5.3.2.3.2 Bus Width Options with SRC Protocols
            3. 7.5.3.2.3.3 Output Data Rate Options with SRC Protocols
      4. 7.5.4 Device Setup
        1. 7.5.4.1 Single Device: All multiSPI™ Options
        2. 7.5.4.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.5.4.3 Multiple Devices: Daisy-Chain Topology
        4. 7.5.4.4 Multiple Devices: Star Topology
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 PD_CNTL Register (address = 010h)
        2. 7.6.1.2 SDI_CNTL Register (address = 014h)
        3. 7.6.1.3 SDO_CNTL Register (address = 018h)
        4. 7.6.1.4 DATA_CNTL Register (address = 01Ch)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Input Driver
      2. 8.1.2 Input Amplifier Selection
      3. 8.1.3 Charge Kickback Filter
      4. 8.1.4 ADC Reference Driver
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power-Supply Recommendations
    1. 9.1 Power-Supply Decoupling
    2. 9.2 Power Saving
      1. 9.2.1 NAP Mode
      2. 9.2.2 PD Mode
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The two primary circuits required to maximize the performance of a high-precision, successive approximation register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This section details some general principles for designing these circuits, followed by an application circuit designed using the ADS9120.

8.1.1 ADC Input Driver

The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier is used for signal conditioning of the input signal and its low output impedance provides a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC and band-limits the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is critical to meet the linearity and noise performance of the ADS9120.

8.1.2 Input Amplifier Selection

Selection criteria for the input amplifiers is highly dependent on the input signal type as well as the performance goals of the data acquisition system. Some key amplifier specifications to consider when selecting an appropriate amplifier to drive the inputs of the ADC are:

  • Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter (see the Charge Kickback Filter section) at the inputs of the ADC. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In order to maintain the overall stability of the input driver circuit, select the amplifier with Unity Gain Bandwidth (UGB) as described in Equation 14:
    • Equation 14. ADS9120 apps_eqn_ugb_bas629.gif
  • Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in SNR performance of the system. Generally, to ensure that the noise performance of the data acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit must be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band-limited by designing a low cutoff frequency RC filter, as explained in Equation 15.
    • Equation 15. ADS9120 apps_eqn_noise_bas547.gif

    where

    • V1 / f_AMP_PP is the peak-to-peak flicker noise in µV,
    • en_RMS is the amplifier broadband noise density in nV/√Hz,
    • f–3dB is the 3-dB bandwidth of the RC filter, and
    • NG is the noise gain of the front-end circuit that is equal to 1 in a buffer configuration.
  • Distortion. Both the ADC and the input driver introduce distortion in a data acquisition block. To ensure that the distortion performance of the data acquisition system is not limited by the front-end circuit, the distortion of the input driver must be at least 10 dB lower than the distortion of the ADC, as shown in Equation 16.
    • Equation 16. ADS9120 apps_eqn_thd_bas547.gif
  • Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal must settle within an 16-bit accuracy at the device inputs during the acquisition time window. This condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired 16-bit accuracy. Therefore, always verify the settling behavior of the input driver by TINA™-SPICE simulations before selecting the amplifier.

8.1.3 Charge Kickback Filter

A charge kickback filter is designed as a low-pass, RC filter, where the 3-dB bandwidth is optimized based on specific application requirements. For dc signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow accurately settling the signal at the inputs of the ADC during the small acquisition time window. For ac signals, keep the filter bandwidth low to band-limit the noise fed into the input of the ADC, thereby increasing the signal-to-noise ratio (SNR) of the system.

Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected from each input pin of the ADC to the ground (as shown in Figure 92). This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. Generally, the value of this capacitor must be at least 15 times the specified value of the ADC sampling capacitance. For the ADS9120, the input sampling capacitance is equal to 60 pF, thus it is recommended to keep CFLT greater than 900 pF. The capacitor must be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.

ADS9120 apps_aaf_bas629.gif Figure 92. Antialiasing Filter Configuration

Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability and distortion of the design. For the ADS9120, limiting the value of RFLT to a maximum of 10-Ω is recommended in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors must be kept less than 1% to keep the inputs balanced.

The driver amplifier must be selected such that its closed-loop output impedance is at least 5X less than the RFLT.

8.1.4 ADC Reference Driver

The external reference source to the ADS9120 must provide low-drift and very accurate voltage for the ADC reference input and support the dynamic charge requirements without affecting the noise and linearity performance of the device. The output broadband noise of most references can be in the order of a few hundred μVRMS. Therefore, to prevent any degradation in the noise performance of the ADC, the output of the voltage reference must be appropriately filtered by using a low-pass filter with a cutoff frequency of a few hundred hertz.

After band-limiting the noise of the reference circuit, the next important step is to design a reference buffer that can drive the dynamic load posed by the reference input of the ADC. The reference buffer must regulate the voltage at the reference pin such that the value of VREF stays within the 1-LSB error at the start of each conversion. This condition necessitates the use of a large capacitor, CBUF_FLT (see Figure 38), between each pair of REFP and REFM pins for regulating the voltage at the reference input of the ADC. The effective capacitance of any large capacitor reduces with the applied voltage based on the voltage rating and type. Using X7R-type capacitors is strongly recommended.

The amplifier selected as the reference driver must have an extremely low offset and temperature drift with a low output impedance to drive the capacitor at the ADC reference pins without any stability issues.

8.2 Typical Application

8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input

ADS9120 apps_ckt_bas629.gif Figure 93. Differential Input DAQ Circuit for Lowest Distortion and Noise at 2.5 MSPS

8.2.1.1 Design Requirements

Design an application circuit optimized for using the ADS9120 to achieve:

  • > 95-dB SNR, < –118-dB THD
  • ±0.5-LSB linearity and
  • Maximum-specified throughput of 2.5 MSPS

8.2.1.2 Detailed Design Procedure

The application circuits are illustrated in Figure 93. For simplicity, power-supply decoupling capacitors are not shown in these circuit diagrams; see the Power-Supply Recommendations section for suggested guidelines.

The input signal is processed through the OPA625 (a high-bandwidth, low-distortion, high-precision amplifier in an inverting gain configuration) and a low-pass RC filter before being fed into the ADC. Generally, the distortion from the input driver must be at least 10 dB less than the ADC distortion. The distortion resulting from variation in the common-mode signal is eliminated by using the OPA625 in an inverting gain configuration. The low-power OPA625 as an input driver provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications. To exercise the complete dynamic range of the ADS9120, the common-mode voltage at the ADS9120 inputs is established at a value of 2.25 V (4.5 V / 2) by using the noninverting pins of the OPA625 amplifiers.

In addition, the components of the charge kickback filter are such that the noise from the front-end circuit is kept low without adding distortion to the input signal.

The reference driver circuit, illustrated in Figure 93, generates a voltage of 4.5 VDC using a single 5-V supply. This circuit is suitable to drive the reference of the ADS9120 at higher sampling rates up to 2.5 MSPS. The reference voltage of 4.5 V in this design is generated by the high-precision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz.

The reference buffer is designed with the OPA625 and OPA378 in a composite architecture to achieve superior dc and ac performance at a reduced power consumption, compared to using a single high-performance amplifier. The OPA625 is a high-bandwidth amplifier with a very low open-loop output impedance of 1 Ω up to a frequency of 1 MHz. The low open-loop output impedance makes the OPA625 a good choice for driving a high capacitive load to regulate the voltage at the reference input of the ADC. The relatively higher offset and drift specifications of the OPA625 are corrected by using a dc-correcting amplifier (the OPA378) inside the feedback loop. The composite scheme inherits the extremely low offset and temperature drift specifications of the OPA378.

8.2.1.3 Application Curves

ADS9120 D101_SBAS710.gif
fIN = 2 kHz, SNR = 95.5 dB, THD = –118 dB
Figure 94. FFT with a 2-kHz Input Signal
ADS9120 D102_SBAS710.gif
Typical INL of ±0.25 LSB
Figure 95. Typical INL

8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input

ADS9120 apps_ckt_diff_bas710.gif Figure 96. DAQ Circuit With FDA Input Driver and Differential Input
ADS9120 apps_ckt_single_bas710.gif Figure 97. DAQ Circuit With FDA Input Driver and Single-Ended Input

8.2.2.1 Design Requirements

Design an application circuit optimized for using the ADS9120 with a fully differential amplifier (FDA) to achieve:

  • > 94-dB SNR, < –115-dB THD with fully-differential inputs
  • > 94-dB SNR, < –112-dB THD with single-ended inputs
  • ±1-LSB linearity and
  • Maximum-specified throughput

8.2.2.2 Detailed Design Procedure

The application circuits are illustrated in Figure 96 and Figure 97. For simplicity, power-supply decoupling capacitors are not shown in these circuit diagrams; see the Power-Supply Recommendations section for suggested guidelines.

The reference voltage of 4.5 V generated by the REF6045, a high-precision voltage reference with integrated high-bandwidth buffer.

In both applications, the input signal is processed through a high-bandwidth, low-distortion, fully-differential amplifier (FDA) designed in an inverting gain configuration and a low-pass RC filter before going to the ADC. Generally, the distortion from the input driver must be at least 10 dB less than the ADC distortion. The distortion resulting from variation in the common-mode signal is eliminated by using the FDA in an inverting gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates the requirement of a rail-to-rail swing at the amplifier input. Therefore, these circuits use the low-power THS4551 as an input driver that provides exceptional ac performance because of its extremely low-distortion and high bandwidth specifications. In addition, the components of the charge kickback filter keep the noise from the front-end circuit low without adding distortion to the input signal. The 10 Ω in the loop resistor improves the phase margin of the THS4551 when driving capacitive loads.

The circuit in Figure 96 shows a fully-differential data acquisition (DAQ) block optimized for low distortion and noise using the THS4551 and the REF6045 with the ADS9120. This front-end circuit configuration requires a differential signal at the input of the FDA and provides a differential output to drive the ADC inputs. The common-mode voltage of the input signal provided to the ADC is set by the VOCM pin of the THS4551. To use the complete dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider.

The circuit in Figure 97 shows a single-ended to differential DAQ block optimized for low distortion and noise using the THS4551 and the REF6045 with the ADS9120. This front-end circuit configuration requires a single-ended ac signal at the input of the FDA and provides a fully-differential output to drive the ADC inputs. The common-mode voltage of the input signal provided to the ADC is set by the VOCM pin of the THS4551. To use the complete dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider.

In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low without adding distortion to the input signal.

8.2.2.3 Application Curves

ADS9120 D101_SBAS710.gif
fIN = 2 kHz, SNR = 95.4 dB, THD = –119 dB
Figure 98. FFT with a 2-kHz Input Signal, Differential Input
ADS9120 D200_SBAS710.gif
fIN = 2 kHz, SNR = 95.2 dB, THD = –116.3 dB
Figure 100. FFT with a 2-kHz Input Signal, Single-Ended Input
ADS9120 D102_SBAS710.gif
Typical INL of ±0.25 LSB
Figure 99. Typical INL, Differential Input
ADS9120 D102_SBAS710.gif
Typical INL of ±0.25 LSB
Figure 101. Typical INL, Single-Ended Input