SBASA74B January 2023 – May 2024 ADS9218 , ADS9219
PRODMIX
ADD | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0Dh | RESERVED | DATA_FORMAT | RESERVED | GE_CAL_EN1 | OSR_EN | OSR | RESERVED | |||||||||
12h | RESERVED | XOR_EN | DATA_LANES | |||||||||||||
13h | RESERVED | RAMP_INC_A | TP_MODE_CHA | TP_EN_CHA | RESERVED | |||||||||||
14h | TP0_A | |||||||||||||||
15h | TP1_A | TP0_A | ||||||||||||||
16h | TP1_A | |||||||||||||||
18h | RESERVED | RAMP_INC_B | TP_MODE_CHB | TP_EN_CHB | RESERVED | |||||||||||
19h | TP0_B | |||||||||||||||
1Ah | TP1_B | TP0_B | ||||||||||||||
1Bh | TP1_B | |||||||||||||||
1Ch | RESERVED | USER_BITS_ADC_B | RESERVED | USER_BITS_ADC_A | ||||||||||||
33h | RESERVED | GE_CAL_EN3 | RESERVED | GE_CAL_EN2 | INIT_KEY | RESERVED | ||||||||||
90h | RESERVED | TS_LD | RESERVED | |||||||||||||
91h | RESERVED | TEMPERATURE_SENSOR | ||||||||||||||
C0h | RESERVED | CLK1 | OSR_INIT1 | OSR_CLK | RESERVED | PD_CH | ||||||||||
C1h | RESERVED | PD_REF | RESERVED | DATA_RATE | RESERVED | CLK2 | ||||||||||
C4h | RESERVED | OSR_INIT2 | RESERVED | OSR_INIT3 | PD_CHIP | |||||||||||
C5h | RESERVED | CLK3 | RESERVED | CLK4 | RESERVED | |||||||||||
F4h | RESERVED | INIT | RESERVED | |||||||||||||
F6h | RESERVED | INIT_2 | RESERVED | |||||||||||||
FBh | RESERVED | NCO_SYSREF | XOR_MODE | CLK5 | MIXER_EN | |||||||||||
FCh | NCO_PHASE_COUNT[15:0] | |||||||||||||||
FDh | NCO_FREQUENCY[7:0] | NCO_PHASE_COUNT[23:16] | ||||||||||||||
FEh | NCO_FREQUENCY[23:8] |
Access Type | Code | Description |
---|---|---|
R | R | Read |
W | W | Write |
R/W | R/W | Read or write |
Reset or Default Value | ||
-n | Value after reset or the default value |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DATA_FORMAT | RESERVED | |||||
R/W-0h | R/W-1h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GE_CAL_EN1 | OSR_EN | OSR | RESERVED | ||||
R/W-0h | R/W-2h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
13 | DATA_FORMAT | R/W | 1h | Select data format for the
ADC conversion result. 0 : Straight binary format 1 : Two's-complement format |
12-8 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
7 | GE_CAL_EN1 | R/W | 0h | Global control for gain
error calibration. 0 : Gain error calibration disabled for all channels 1 : Gain error calibration enabled for all channels |
6 | OSR_EN | R/W | 0h | Control for data averaging
depth. 0 : Data averaging disabled 1 : Data averaging enabled |
5-2 | OSR | R/W | 0h | Control for enabling data
averaging. 0 : 2 samples averaged 1 : 4 samples averaged 2 : 8 samples averaged 3 : 16 samples averaged |
1-0 | RESERVED | R/W | 2h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XOR_EN | DATA_LANES | |||||
R/W-0h | R/W-0h | R/W-2h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
3 | XOR_EN | R/W | 0h | Enables XOR operation on
ADC conversion result. 0 : XOR operation is disabled 1 : ADC conversion result is bit-wise XOR with the LSB of the ADC conversion result |
2-0 | DATA_LANES | R/W | 2h | Selects the number of
output data lanes and number of data bits per output lane. Enables
XOR operation on ADC conversion result. 0 : ADC A and B data output on DOUTA and DOUTB respectively; 20 bits per ADC. 2 : ADC A and B data output on DOUTA and DOUTB respectively; 24 bits per ADC. 5 : ADC A and B data output on DOUTA; 20 bits per ADC. 7 : ADC A and B data output on DOUTA; 24 bits per ADC. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMP_INC_A | TP_MODE_A | TP_EN_A | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
7-4 | RAMP_INC_A | R/W | 0h | Increment value for the
ramp pattern output. The output ramp increments by N+1, where N is
the value configured in this register. |
3-2 | TP_MODE_A | R/W | 0h | Select digital test
pattern for ADC A. 0 : Fixed pattern from the TP0_A register 1 : Fixed pattern from the TP0_A register 2 : Digital ramp output 3 : Alternate fixed pattern output from the TP0_A and TP1_A registers |
1 | TP_EN_A | R/W | 0h | Enable digital test
pattern for data corresponding to ADC A. 0 : Data output is the ADC conversion result 1 : Data output is the digital test pattern for ACD A |
0 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TP0_A[15:0] | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TP0_A[15:0] | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TP0_A[15:0] | R/W | 0h | Lower 16 bits of test
pattern 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TP1_A[7:0] | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TP0_A[23:16] | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TP1_A[7:0] | R/W | 0h | Lower eight bits of test
pattern 1 |
7-0 | TP0_A[23:16] | R/W | 0h | Upper eight bits of test
pattern 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TP1_A[23:8] | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TP1_A[23:8] | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TP1_A[23:8] | R/W | 0h | Upper 16 bits of test
pattern 1 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMP_INC_B | TP_MODE_B | TP_EN_B | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
7-4 | RAMP_INC_B | R/W | 0h | Increment value for the
ramp pattern output. The output ramp increments by N+1, where N is
the value configured in this register. |
3-2 | TP_MODE_B | R/W | 0h | Select digital test
pattern for ADC B. 0 : Fixed pattern from the TP0_B register 1 : Fixed pattern from the TP0_B register 2 : Digital ramp output 3 : Alternate fixed pattern output from the TP0_B and TP1_B registers |
1 | TP_EN_B | R/W | 0h | Enable digital test
pattern for data corresponding to ADC B. 0 : Data output is the ADC conversion result 1 : Data output is the digital test pattern |
0 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TP0_B[15:0] | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TP0_B[15:0] | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | TP0_B[15:0] | R/W | 0h | Lower 16 bits of test
pattern 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TP1_B[7:0] | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TP0_B[23:16] | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | TP1_B[7:0] | R/W | 0h | Lower eight bits of test
pattern 1 |
7-0 | TP0_B[23:16] | R/W | 0h | Upper eight bits of test
pattern 0 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | USER_BITS_ADC_B | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | USER_BITS_ADC_A | ||||||
R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
13-8 | USER_BITS_ADC_B | R/W | 0h | User-defined bits appended
to the ADC conversion result from ADC B. |
7-6 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
5-0 | USER_BITS_ADC_A | R/W | 0h | User-defined bits appended
to the ADC conversion result from ADC A. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GE_CAL_EN3 | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GE_CAL_EN2 | INIT_KEY | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
13 | GE_CAL_EN3 | R/W | 0h | Global control for gain
error calibration. 0 : Gain error calibration disabled for all channels 1 : Gain error calibration enabled for all channels |
12-7 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
6 | GE_CAL_EN2 | R/W | 0h | Global control for gain
error calibration. 0 : Gain error calibration disabled for all channels 1 : Gain error calibration enabled for all channels |
5-4 | INIT_KEY | R/W | 0h | Device initialization sequence access key. Write 11b to access the device initialization sequence. Write 00b for normal operation. |
3-0 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TS_LD | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
14 | TS_LD | R/W | 0h | Trigger to load temperature sensor output in address 0x91. Transition from 0 to 1 if this bit triggers the data load operation. |
13-0 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TEMPERATURE_SENSOR | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEMPERATURE_SENSOR | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
9-0 | TEMPERATURE_SENSOR | R/W | 0h | 10-bit temperature sensor output. See the Temperature Sensor section. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLK1 | OSR_INIT1 | OSR_CLK | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSR_CLK | RESERVED | PD_CH | |||||
R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
12 | CLK1 | R/W | 0h | Selects the clock
configuration based on output data-lanes. 0 : Configuration for DATA_LANES = 0 or 2 1 : Configuration for DATA_LANES = 5 or 7 |
11-10 | OSR_INIT1 | R/W | 0h | Initialization for data
averaging. 0 : Configuration for disabling data averaging 1 : Configuration for enabling data averaging |
9-7 | OSR_CLK | R/W | 0h | Data output clock configuration for data averaging. See Table 6-3 for more details. |
6-2 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
1-0 | PD_CH | R/W | 0h | Power-down control for the
analog input channels. 0 : Normal operation 1 : ADC A powered down 2 : ADC B powered down 3 : ADC A and B powered down |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PD_REF | RESERVED | DATA_RATE | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLK2 | ||||||
R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
11 | PD_REF | R/W | 0h | ADC reference voltage
source selection. 0 : Internal reference enabled. 1 : Internal reference disabled. Connect the external reference voltage to the REFIO pin. |
10-9 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
8 | DATA_RATE | R/W | 0h | Select data rate for the
data interface. 0 : Double data rate (DDR) 1 : Single data rate (SDR) |
7-1 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
0 | CLK2 | R/W | 0h | Select data rate for the
data interface. 0 : Configuration for DATA_LANES = 2 or 7 1 : Configuration for DATA_LANES = 0 or 5 |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OSR_INIT2 | RESERVED | OSR_INIT3 | PD_CHIP | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-6 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
5-4 | OSR_INIT2 | R/W | 0h | Initialization for data
averaging. 0 : Configuration for disabling data averaging 2 : Configuration for enabling data averaging |
3-2 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
1 | OSR_INIT3 | R/W | 0h | Initialization for data
averaging. 0 : Configuration for disabling data averaging 1 : Configuration for enabling data averaging |
0 | PD_CHIP | R/W | 0h | Full chip power-down
control. 0 : Normal device operation 1 : Full device powered-down |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLK3 | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLK4 | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
9 | CLK3 | R/W | 0h | Select data rate for the
data interface. 0 : Configuration for DATA_LANES = 0 or 2 1 : Configuration for DATA_LANES = 5 or 7 |
8 - 4 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
3 - 2 | CLK4 | R/W | 0h | Clock configuration for
ADS9217. See section on Data Interface for details. Not applicable for ADS9219 and ADS9218. 0 : 24-bit 2-lane mode 3 : all other modes |
1 - 0 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CM_CTRL_EN | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-2 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
1 | INIT | R/W | 0h | INIT field for device initialization. Write 1b during the initialization sequence. Write 0b for normal operation. |
0 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_2 | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-2 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
1 | INIT_2 | R/W | 0h | INIT_2 field for device initialization. Write 1b during the initialization sequence. Write 0b for normal operation. |
0 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NCO_SYSREF | XOR_MODE | CLK5 | MIXER_EN | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R/W | 0h | Reserved. Do not change from the default reset value. |
3 | NCO_SYSREF | R/W | 0h | Set to 1b when applying
periodic pulses on the SMPL_SYNC pin. 0: Synchronize the NCO with one pulse on the SMPL_SYNC pin. 1: Synchronize the NCO with the first pulse on the SMPL_SYNC pin when using periodic pulses. |
2 | XOR_MODE | R/W | 0h | Selects the bit with which
the ADC output data is XOR'ed when XOR output mode is enabled. 0 : PRBS bit is output after the ADC LSB. ADC output data is XOR'ed with the PRBS bit. 1 : ADC output data is XOR'ed with the LSB of the conversion result. |
1 | CLK5 | R/W | 0h | Clock configuration for
the ADS9219 and ADS9218. See the Data Interface section for details. Not applicable for
the ADS9217. 0 : 24-bit 2-lane SDR and DDR modes 1 : 24-bit 1-lane SDR and DDR modes |
0 | MIXER_EN | R/W | 0h | 0: Digital down converter
disabled 1: Digital down converter enabled |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NCO_PHASE_COUNT | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCO_PHASE_COUNT | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | NCO_PHASE_COUNT[15:0] | R/W | 0h | Lower 15 bits of the NCO phase count. See the Digital Down Converter section. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NCO_FREQUENCY | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCO_PHASE_COUNT | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | NCO_FREQUENCY[7:0] | R/W | 0h | Lower eight bits of the NCO phase count. See the Digital Down Converter section. |
7-0 | NCO_PHASE_COUNT[23:16] | R/W | 0h | Higher eight bits of the NCO phase count. See the Digital Down Converter section. |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NCO_FREQUENCY | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCO_FREQUENCY | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | NCO_FREQUENCY | R/W | 0h | Higher 16 bits of the NCO phase count. See the Digital Down Converter section. |