SBASA74B January   2023  – May 2024 ADS9218 , ADS9219

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Diagrams
    9. 5.9  Typical Characteristics: All Devices
    10. 5.10 Typical Characteristics: ADS9219
    11. 5.11 Typical Characteristics: ADS9218
    12. 5.12 Typical Characteristics: ADS9217
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
      2. 6.3.2 Analog Input Bandwidth
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference Voltage
      5. 6.3.5 Temperature Sensor
      6. 6.3.6 Data Averaging
      7. 6.3.7 Digital Down Converter
      8. 6.3.8 Data Interface
        1. 6.3.8.1 Data Frame Width
        2. 6.3.8.2 Synchronizing Multiple ADCs
        3. 6.3.8.3 Test Patterns for Data Interface
          1. 6.3.8.3.1 Fixed Pattern
          2. 6.3.8.3.2 Alternating Test Pattern
          3. 6.3.8.3.3 Digital Ramp
      9. 6.3.9 ADC Sampling Clock Input
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-Down Options
      3. 6.4.3 Normal Operation
      4. 6.4.4 Initialization Sequence
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for ≤20kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for ≤100kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for ≤1MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Register Bank 2

Figure 7-59 Register Bank 2 Map
ADD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
12h RESERVED INIT_3 RESERVED
13h INIT_4 RESERVED
0Ah RESERVED INIT_2 RESERVED
1Ch RESERVED CLK6 RESERVED
Table 7-3 Register Section/Block Access Type Codes
Access Type Code Description
R R Read
W W Write
R/W R/W Read or write
Reset or Default Value
-n Value after reset or the default value

7.3.1 Register 12h (offset = 12h) [reset = 0h]

Figure 7-60 Register 12h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED INIT_3 RESERVED
R/W-0h R/W-0h R/W-0h
Figure 7-61 Register 12h Field Descriptions
Bit Field Type Reset Description
15-7 RESERVED R/W 0h Reserved. Do not change from the default reset value.
6 INIT_3 R/W 0h INIT_3 field for device initialization. Write 1b during the initialization sequence. Write 0b for normal operation.
5-0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.3.2 Register 13h (offset = 13h) [reset = 0h]

Figure 7-62 Register 13h
15 14 13 12 11 10 9 8
INIT_4 RESERVED
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
Figure 7-63 Register 13h Field Descriptions
Bit Field Type Reset Description
15 INIT_4 R/W 0h INIT_4 field for device initialization. Write 1b during initialization sequence. Write 0b for normal operation.
14-0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.3.3 Register 0Ah (offset = 0Ah) [reset = 0h]

Figure 7-64 Register 0Ah
15 14 13 12 11 10 9 8
RESERVED INIT_5 RESERVED
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
Figure 7-65 Register 0Ah Field Descriptions
Bit Field Type Reset Description
15 RESERVED R/W 0h Reserved. Do not change from the default reset value.
14 INIT_5 R/W 0h INIT_5 field for device initialization. Write 1b during initialization sequence. Write 0b for normal operation.
13-0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.3.4 Register 1Ch (offset = 1Ch) [reset = 0h]

Figure 7-66 Register 1Ch
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
CLK6 RESERVED
R/W-0h R/W-0h
Figure 7-67 Register 1Ch Field Descriptions
Bit Field Type Reset Description
15 - 8 RESERVED R/W 0h Reserved. Do not change from the default reset value.
7 - 6 CLK6 R/W 0h Clock configuration for ADS9217. See the Data Interface section for details. Not applicable for ADS9219 and ADS9218.
0 : 24-bit 2-lane mode
3 : all other modes
5 - 0 RESERVED R/W 0h Reserved. Do not change from the default reset value.