SBASAG2B December   2023  – August 2024 ADS9227

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Diagrams
    9. 5.9  Typical Characteristics: All Devices
    10. 5.10 Typical Characteristics: ADS9229
    11. 5.11 Typical Characteristics: ADS9228
    12. 5.12 Typical Characteristics: ADS9227
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
      2. 6.3.2 Analog Input Bandwidth
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference
        1. 6.3.4.1 Internal Reference Voltage
        2. 6.3.4.2 External Reference Voltage
      5. 6.3.5 Temperature Sensor
      6. 6.3.6 Data Averaging
      7. 6.3.7 Digital Down Converter
      8. 6.3.8 Data Interface
        1. 6.3.8.1 Data Frame Width
        2. 6.3.8.2 Synchronizing Multiple ADCs
        3. 6.3.8.3 Test Patterns for Data Interface
          1. 6.3.8.3.1 User-Defined Test Pattern
          2. 6.3.8.3.2 User-Defined Alternating Test Pattern
          3. 6.3.8.3.3 Ramp Test Pattern
      9. 6.3.9 ADC Sampling Clock Input
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-Down Options
      3. 6.4.3 Normal Operation
      4. 6.4.4 Initialization Sequence
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for ≤20kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for ≤100kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for ≤1MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Figure 4-1 RHA Package,6mm × 6mm, 40-Pin VQFN(Top View)
Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AINAM 4 I Negative analog input for ADC A.
AINAP 3 I Positive analog input for ADC A.
AINBM 8 I Negative analog input for ADC B.
AINBP 7 I Positive analog input for ADC B.
AVDD_5V 1, 10 P 5V analog power-supply pin.
CS 17 I Chip-select input pin for the configuration interface; active low.
DCLKM 23 O Negative differential data clock output. Connect a 100Ω resistor between DCLKP and DCLKM close to the receiver.
DCLKP 24 O Positive differential data clock output. Connect a 100Ω resistor between DCLKP and DCLKM close to the receiver.
DOUTAM 27 O Negative differential data output. Connect a 100Ω resistor between DOUTAP and DOUTAM close to the receiver.
Transmits ADC A data in 2-lane mode.
Transmits ADC A and ADC B data in 1-lane mode.
DOUTAP 28 O Positive differential data output corresponding to ADC A. Connect a 100Ω resistor between DOUTAP and DOUTAM close to the receiver.
Transmits ADC A data in 2-lane mode.
Transmits ADC A and ADC B data in 1-lane mode.
DOUTBM 25 O Negative differential data output corresponding to ADC B in 2-lane mode. Connect a 100Ω resistor between DOUTBP and DOUTBM close to the receiver. Unused in 1-lane mode.
DOUTBP 26 O Positive differential data output corresponding to ADC B in 2-lane mode. Connect a 100Ω resistor between DOUTBP and DOUTBM close to the receiver. Unused in 1-lane mode.
FCLKM 29 O Negative differential data frame clock output. Connect a 100Ω resistor between FCLKP and FCLKM close to the receiver.
FCLKP 30 O Positive differential data frame clock output. Connect a 100Ω resistor between FCLKP and FCLKM close to the receiver.
GND 2, 9, 12, 15, 34, 38 P Ground.
PWDN 22 I Power-down control; active low. Connect to VDD_1V8 if unused.
REFIO 39 I/O Internal reference voltage output. External reference voltage input. Connect a 10μF decoupling capacitor to REFM.
REFM 6, 11, 40 P Reference ground. Connect to GND.
RESET 21 I Reset input; active low. Connect to VDD_1V8 if unused.
SCLK 18 I Serial clock input for the configuration interface.
SDI / EXTREF 19 I SDI is a multifunction logic input; pin function is determined by the SPI_EN pin. SDI has an internal 100kΩ pulldown resistor to GND. SPI_EN = 0b: SDI is the logic input to select between the internal or external reference. Connect SDI to GND for the external reference. Connect SDI to VDD_1V8 for the internal reference. SPI_EN = 1b: Serial data input for the configuration interface
SDO 20 O Serial data output for the configuration interface.
SMPL_CLKM 31 I ADC sampling clock input. Negative differential input for the LVDS sampling clock. Connect this pin to GND for the CMOS sampling clock.
SMPL_CLKP 32 I ADC sampling clock input. Positive differential input for the LVDS sampling clock. Clock input for the CMOS sampling clock.
SMPL_SYNC 33 I Synchronization input for internal averaging filter.
Connect to GND if unused. See the Synchronizing Multiple ADCs section on how to use the SMPL_SYNC pin.
SPI_EN 16 I Control to enable configuration of the SPI interface; active high.
Connect a pullup resistor to VDD_1V8 to keep the configuration interface enabled. Connect to GND if SPI configuration is unused. When SPI_EN = 0, select the reference voltage with the SDI/EXTREF pin.
Thermal Pad — P Exposed thermal pad. Connect to GND.
VCMOUT 5 O Common-mode voltage output. Use VCMOUT to set the common-mode voltage at the ADC inputs. Connect a 1μF decoupling capacitor to GND.
VDD_1V8 13, 14, 35, 36, 37 P 1.8V power-supply. Connect 1μF and 0.1μF decoupling capacitors to GND.
(1) I = input, O = output, I/O = input or output, G = ground, P = power.