SBASAQ6A July   2024  – November 2024 ADS9811 , ADS9813

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Clamp Protection Circuit
        2. 6.3.1.2 Programmable Gain Amplifier (PGA)
        3. 6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit
      2. 6.3.2 ADC Transfer Function
      3. 6.3.3 ADC Sampling Clock Input
      4. 6.3.4 Synchronizing Multiple ADCs
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Data Interface
        1. 6.3.6.1 Data Clock Output
        2. 6.3.6.2 ADC Output Data Randomizer
        3. 6.3.6.3 Data Averaging
        4. 6.3.6.4 Test Patterns for Data Interface
          1. 6.3.6.4.1 Fixed Pattern
          2. 6.3.6.4.2 Digital Ramp
          3. 6.3.6.4.3 Alternating Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-Down
      3. 6.4.3 Initialization Sequence
      4. 6.4.4 Normal Operation
      5. 6.4.5 Speed-Boost Mode
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices in a Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Parametric Measurement Unit (PMU)
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

at AVDD_5V = 4.75V to 5.25V, VDD_1V8 = 1.75V to 1.85V, IOVDD = 1.15V to 1.85V, VREF = 4.096V (external), and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
RIN Input impedance All input ranges 0.8 1 1.2 MΩ
Input impedance thermal drift All input ranges 10 30 ppm/°C
Input capacitance 10 pF
ANALOG INPUT FILTER
BW(-3 dB) Analog input LPF bandwidth
–3 dB		 Low-bandwidth filter, all input ranges 22.7 kHz
Wide-bandwidth filter, input range = ±2.5V 221
Wide-bandwidth filter, input range = ±3.5V 325
Wide-bandwidth filter, input range = ±5V 500
Wide-bandwidth filter, input range = ±7V 700
Wide-bandwidth filter, input range = ±10V 691
Wide-bandwidth filter, input range = ±12V 664
DC PERFORMANCE(3)(4)
Resolution No missing codes 18 Bits
DNL Differential nonlinearity Wide CM enabled and disabled, all ranges –0.99 ±0.35 0.99 LSB
INL Integral nonlinearity RANGE = ±5V and ±10V, TA = 20℃ to 60℃,
AVDD_5V = 4.9V to 5.1V
ADS9813 and ADS9811 		 –2 ±0.8 2 LSB
All ranges –4 ±0.8 4
Offset error RANGE = ±5V, ±10V, and ±12V –75 ±15 75 LSB
RANGE = ±3.5V and ±7V –100 ±25 100
RANGE = ±2.5V –175 ±25 175
All other conditions ±50
Offset error thermal drift All ranges, TA = 0°C to 70°C 0.6 2 ppm/°C
All ranges 0.6
Gain error All ranges –0.038 ±0.008 0.038 %FSR
Gain error thermal drift All ranges, TA = 0°C to 70°C 0.6 3 ppm/°C
All ranges 0.6
AC PERFORMANCE(3)(4)
SNR Signal-to-noise ratio Low-noise filter, fIN = 2kHz, range = ±2.5V 85.3 87.4 dBFS
Low-noise filter, fIN = 2kHz, range = ±3.5V 86.3 88.4
Low-noise filter, fIN = 2kHz, range = ±5V 87 89.1
Low-noise filter, fIN = 2kHz, range = ±7V 87.5 89.8
Low-noise filter, fIN = 2kHz, range = ±10V 88 90.2
Low-noise filter, fIN = 2kHz, range = ±12V 88.1 90.3
Wide-bandwidth filter, fIN = 2kHz,
range = ±2.5V		 77.1 79.1
Wide-bandwidth filter, fIN = 2kHz,
range = ±3.5V		 77.4 79.4
Wide-bandwidth filter, fIN = 2kHz,
range = ±5V		 77.5 79.7
Wide-bandwidth filter, fIN = 2kHz,
range = ±7V		 77.7 79.9
Wide-bandwidth filter, fIN = 2kHz,
range = ±10V		 79.5 81.6
Wide-bandwidth filter, fIN = 2 kHz,
range = ±12V		 80.2 82.4
SINAD Signal-to-noise + distortion ratio Low-noise filter, fIN = 2kHz, range = ±2.5V 85.2 87.3 dB
Low-noise filter, fIN = 2kHz, range = ±3.5V 86.2 88.3
Low-noise filter, fIN = 2kHz, range = ±5V 86.9 89
Low-noise filter, fIN = 2kHz, range = ±7V 87.4 89.7
Low-noise filter, fIN = 2kHz, range = ±10V 87.9 90.1
Low-noise filter, fIN = 2kHz, range = ±12V 88 90.2
Wide-bandwidth filter, fIN = 2kHz,
range = ±2.5V		 77 79
Wide-bandwidth filter, fIN = 2kHz,
range = ±3.5V		 77.3 79.3
Wide-bandwidth filter, fIN = 2kHz,
range = ±5V		 77.4 79.6
Wide-bandwidth filter, fIN = 2kHz,
range = ±7V		 77.6 79.8
Wide-bandwidth filter, fIN = 2kHz,
range = ±10V		 79.4 81.5
Wide-bandwidth filter, fIN = 2 kHz,
range = ±12V		 80.1 82.3
THD Total harmonic distortion Low-noise filter, fIN = 2kHz, all ranges –113 dB
Wide-bandwidth filter, fIN = 2kHz, all ranges –113
SFDR Spurious-free dynamic range fIN = 2kHz 102 dB
fIN = 2kHz, data averaging enabled 113
CMRR At dc –70 dB
Isolation crosstalk At dc –100 dB
INTERNAL REFERENCE
VREF(1) Voltage on REFIO pin (configured as output) 1µF capacitor on REFIO pin, TA = 25°C 4.092 4.096 4.1 V
Reference temperature drift 7 20 ppm/°C
DIGITAL INPUTS
VIL Input low logic level –0.3 0.3 IOVDD V
VIH Input high logic level 0.7 IOVDD IOVDD V
Input capacitance 6 pF
LVDS SAMPLING CLOCK INPUT
VTH High-level input voltage (P – M) AC coupled 100 mV
DC coupled 300
VTL Low-level input voltage (P – M) AC coupled –100 mV
DC coupled –300
VICM Input common-mode voltage 0.5 1.2 1.4 V
DIGITAL OUTPUTS
VOL Output low logic level IOL = 200µA sink 0 0.2 IOVDD V
VOH Output high logic level IOH = 200µA source 0.8 IOVDD IOVDD V
POWER SUPPLY - ADS9813
Total power dissipation Maximum throughput 244 304 mW
IAVDD_5V Supply current from AVDD_5V Maximum throughput, internal reference 28.3 32 mA
Power-down 0.2 2
IVDD_1V8 Supply current from VDD_1V8 Maximum throughput, internal reference 52 70 mA
Power-down 0.2 8
IIOVDD Supply current from IOVDD Maximum throughput, CL = 10pF 5 10 mA
Power-down 0.1 2
POWER SUPPLY - ADS9811 and ADS9810
Total power dissipation Maximum throughput 177 215 mW
IAVDD_5V Supply current from AVDD_5V Maximum throughput, internal reference 21.3 25 mA
Supply current from AVDD_5V Power-down 0.2 2
IVDD_1V8 Supply current from VDD_1V8 Maximum throughput, internal reference 35 43 mA
Supply current from VDD_1V8 Power-down 0.2 8
IIOVDD Supply current from IOVDD Maximum throughput, CL = 10pF 4 7 mA
Supply current from IOVDD Power-down 0.1 2
(1) Does not include the variation in voltage resulting from solder shift effects.
(2) Measured with analog input common-mode voltage range ≤ ±RANGE/2 as described in Wide Common-Mode Configuration for Differential Inputs
(3) Minimum and maximum specifications are applicable for low-bandwidth filter setting.