SBASA81B January 2023 – October 2024 ADS9815 , ADS9817
PRODUCTION DATA
As illustrated in Figure 5-2, Figure 5-3, Figure 5-4, and Figure 5-5, the SMPL_SYNC pin synchronizes multiple ADCs using an external SYNC signal. The SMPL_SYNC pin is latched in by the falling edge of the sampling clock.
The synchronization signal is only required one time after power-up with the sampling clock free-running, or after restarting sampling clock, or after a device reset. As illustrated in Figure 5-2, Figure 5-3, Figure 5-4, and Figure 5-5, the SYNC signal resets the internal analog channel selection logic and aligns the FCLKOUT signal to the data frame. If no SYNC signal is given, the internal analog channel selection logic and FCLKOUT are not synchronized, which can lead to a different alignment between the sequence of channel output data and FCLKOUT. When using multiple ADCs with the same sampling clock, the SYNC signal makes sure all ADCs sample the same respective analog input channel at the same time.