SBASA81B January   2023  – October 2024 ADS9815 , ADS9817

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Clamp Protection Circuit
        2. 6.3.1.2 Programmable Gain Amplifier (PGA)
        3. 6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit
        4. 6.3.1.4 Gain Error Calibration
      2. 6.3.2 ADC Transfer Function
      3. 6.3.3 ADC Sampling Clock Input
      4. 6.3.4 Reference
        1. 6.3.4.1 Internal Reference Voltage
        2. 6.3.4.2 External Reference Voltage
      5. 6.3.5 Sample Synchronization
      6. 6.3.6 Data Interface
        1. 6.3.6.1 Data Clock Output
        2. 6.3.6.2 ADC Output Data Randomizer
        3. 6.3.6.3 Test Patterns for Data Interface
          1. 6.3.6.3.1 Fixed Pattern
          2. 6.3.6.3.2 Digital Ramp
          3. 6.3.6.3.3 Alternating Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down
      2. 6.4.2 Reset
      3. 6.4.3 Initialization Sequence
      4. 6.4.4 Normal Operation
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Parametric Measurement Unit (PMU)
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.3 Detailed Design Procedure

The ADS981x is an eight-channel, 18-bit, 2MSPS data acquisition (DAQ) system. The device has a built-in analog front-end that makes the ATE signal chain easier to design and more accurate.

The ADC accuracy is based on the total-unadjusted-error (TUE), which combines INL, offset, and gain errors. Calibrate the external system for offset and gain errors at a specified temperature and supply voltage. When calibrated (as described in Table 8-2), only the INL, thermal offset drift, and thermal gain drift contribute to the TUE. The ADS981x has a TUE of 0.0016% at 25°C ±5°C post-calibration, meeting the design error requirement.
Table 8-2 TUE at TA = 25°C Calculation
CALIBRATION INL (ppm) OFFSET ERROR (ppm) GAIN ERROR (ppm) TUE (ppm) ERROR (%)
No calibration 15.26 495.9 183.1 528.8 0.053
Post-calibration 15.26 0 0 15.3 0.0015
Post-calibration ±5°C 15.26 2.5 3.5 15.9 0.0016

The pin-electronics subsystem manages the PMU outputs. The subsystem connects each PMU output to separate ADC channels (Figure 8-1) or uses a multiplexer to link multiple PMU outputs to one ADC channel (Figure 8-2). This subsystem allows more pin-electronics channels on the card. The ADC requires more bandwidth with multiplexers (Table 8-3) for fast settling when switching PMU channels. The ADS981x has two bandwidth modes: Low-noise (up to 21kHz) and wide-bandwidth (up to 400kHz). As described in Table 8-3 the wide-bandwidth mode samples multiplexed PMU signals and settles to 99.99% FS in 13µs.

Table 8-3 Step-Settling Performance
ANALOG INPUT BANDWIDTH SETTLING TIME
99.90% of FS 99.95% of FS 99.99% of FS
Low BW (21kHz) 56μs 61μs 76μs
Wide BW (400kHz) 7μs 8μs 13μs