SBASA81B January   2023  – October 2024 ADS9815 , ADS9817

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Clamp Protection Circuit
        2. 6.3.1.2 Programmable Gain Amplifier (PGA)
        3. 6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit
        4. 6.3.1.4 Gain Error Calibration
      2. 6.3.2 ADC Transfer Function
      3. 6.3.3 ADC Sampling Clock Input
      4. 6.3.4 Reference
        1. 6.3.4.1 Internal Reference Voltage
        2. 6.3.4.2 External Reference Voltage
      5. 6.3.5 Sample Synchronization
      6. 6.3.6 Data Interface
        1. 6.3.6.1 Data Clock Output
        2. 6.3.6.2 ADC Output Data Randomizer
        3. 6.3.6.3 Test Patterns for Data Interface
          1. 6.3.6.3.1 Fixed Pattern
          2. 6.3.6.3.2 Digital Ramp
          3. 6.3.6.3.3 Alternating Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down
      2. 6.4.2 Reset
      3. 6.4.3 Initialization Sequence
      4. 6.4.4 Normal Operation
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Parametric Measurement Unit (PMU)
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

at AVDD_5V = 4.75 V to 5.25 V, VDD_1V8 = 1.75 V to 1.85 V, IOVDD = 1.15 V to 1.85 V, VREF = 4.096 V (internal or external), wide-common-mode disabled for analog input ranges ±2.5V, ±3.5V, and ±5V, wide-common-mode enabled for analog input ranges ±7V, ±10V, and ±12V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
RIN Input impedance All input ranges 0.85 1 1.15 MΩ
Input impedance thermal drift All input ranges 10 25 ppm/°C
Input capacitance 10 pF
ANALOG INPUT FILTER
BW(-3 dB) Analog input LPF bandwidth
–3 dB		 All input ranges, low-bandwidth filter 21 kHz
RANGE = ±2.5V, wide-bandwidth filter 182
RANGE = ±3.5V, wide-bandwidth filter 240
RANGE = ±5V, wide-bandwidth filter 320
RANGE = ±7V, wide-bandwidth filter 400
RANGE = ±10V, wide-bandwidth filter 385
RANGE = ±12V, wide-bandwidth filter 375
DC PERFORMANCE
Resolution No missing codes 18 Bits
DNL Differential nonlinearity(3) All ranges, wide-CM enabled and disabled –0.99 ±0.5 0.99 LSB
INL Integral nonlinearity All ranges, wide-CM enabled and disabled,
TA = 0℃ to 70℃ 		 –4 ±0.8 4 LSB
All ranges, wide-CM enabled and disabled,
TA = –40℃ to 125℃ 		 –4.5 ±0.8 4.5 LSB
Offset error(2)(5) RANGE = ±2.5V –175 ±90 175 LSB
RANGE = ±2.5V, wide-CM enabled ±120
RANGE = ±3.5V –100 ±60 100
RANGE = ±3.5V, wide-CM enabled ±80
RANGE = ±5V –50 ±10 50
RANGE = ±5V, wide-CM enabled ±60
RANGE = ±7V –100 ±35 100
RANGE = ±10V –50 ±10 50
RANGE = ±12V –75 ±15 75
Offset error thermal drift(2)(4) All ranges, wide-CM enabled and disabled 0.5 1.5 ppm/°C
Gain error(2)(5) RANGE = ±2.5V, ±3.5V, and ±5V –0.05 ±0.02 0.05 %FSR
RANGE = ±2.5V, ±3.5V, and ±5V,
wide-CM enabled		 ±0.04
RANGE = ±7V, ±10V, ±12V –0.05 ±0.02 0.05
Gain error thermal drift(2)(4) Wide-CM enabled and disabled, all ranges 0.7 3 ppm/°C
AC PERFORMANCE
SNR Signal-to-noise ratio, 
low-noise filter		 RANGE = ±2.5V, fIN = 2kHz 86.7 89.5 dBFS
RANGE = ±3.5V, fIN = 2kHz 87.8 90.5
RANGE = ±5V, fIN = 2kHz 88.5 91.4
RANGE = ±7V, fIN = 2kHz 89.3 91.3
RANGE = ±10V, fIN = 2kHz 89.9 91.8
RANGE = ±12V, fIN = 2kHz 90 92
Signal-to-noise ratio, 
wide-bandwidth filter		 RANGE = ±2.5V, fIN = 2kHz 79 82.5
RANGE = ±3.5V, fIN = 2kHz 80 83.5
RANGE = ±5V, fIN = 2kHz 80.5 84.5
RANGE = ±7V, fIN = 2kHz 81.5 83.5
RANGE = ±10V, fIN = 2kHz 83 85
RANGE = ±12V, fIN = 2kHz 83.5 85.5
SINAD Signal-to-noise + distortion ratio, 
low-noise filter		 RANGE = ±2.5V, fIN = 2kHz 85.7 88.9 dB
RANGE = ±3.5V, fIN = 2kHz 86.7 89.9
RANGE = ±5V, fIN = 2kHz 87.3 90.7
RANGE = ±7V, fIN = 2kHz 88.0 90.6
RANGE = ±10V, fIN = 2kHz 88.5 91.1
RANGE = ±12V, fIN = 2kHz 88.6 91.3
Signal-to-noise + distortion ratio, 
wide-bandwidth filter		 RANGE = ±2.5V, fIN = 2kHz 78.6 82.2
RANGE = ±3.5V, fIN = 2kHz 79.5 83.2
RANGE = ±5V, fIN = 2kHz 80.0 84.2
RANGE = ±7V, fIN = 2kHz 80.9 83.2
RANGE = ±10V, fIN = 2kHz 82.3 84.7
RANGE = ±12V, fIN = 2kHz 82.8 85.1
THD Total harmonic distortion All ranges, low-noise filter, fIN = 2kHz –113 dB
All ranges, wide-bandwidth filter, fIN = 2kHz –113
SFDR Spurious-free dynamic range All ranges, fIN = 2kHz 113 dB
CMRR at dc –70 dB
Isolation crosstalk at dc –100 dB
INTERNAL REFERENCE
VREF(1) Voltage on REFIO pin (configured as output) 1µF capacitor on REFIO pin, TA = 25°C 4.092 4.096 4.1 V
Reference temperature drift(4) 10 25 ppm/°C
DIGITAL INPUTS
VIL Input low logic level –0.3 0.3 IOVDD V
VIH Input high logic level 0.7 IOVDD IOVDD V
Input current 0.1 µA
Input capacitance 6 pF
LVDS SAMPLING CLOCK INPUT
VTH High-level input voltage AC coupled 100 mV
DC coupled 300
VTL Low-level input voltage AC coupled –100 mV
DC coupled –300
VICM Input common-mode voltage 0.3 1.2 1.4 V
DIGITAL OUTPUTS
VOL Output low logic level IOL = 500µA sink 0 0.2 IOVDD V
VOH Output high logic level IOH = 500µA source 0.8 IOVDD IOVDD V
POWER SUPPLY - ADS9817
Total power dissipation Maximum throughput 232 304 mW
IAVDD_5V Supply current from AVDD_5V Maximum throughput, internal reference 26 32 mA
Power-down 0.2 2
IVDD_1V8 Supply current from VDD_1V8 Maximum throughput, internal reference 50 70 mA
Power-down 0.2 8
IIOVDD Supply current from IOVDD Maximum throughput 7 10 mA
Power-down 0.1 3
POWER SUPPLY - ADS9815
Total power dissipation Maximum throughput 165 215 mW
IAVDD_5V Supply current from AVDD_5V Maximum throughput, internal reference 19 25 mA
Power-down 0.2 2
IVDD_1V8 Supply current from VDD_1V8 Maximum throughput, internal reference 35 43 mA
Power-down 0.2 8
IIOVDD Supply current from IOVDD Maximum throughput 4 7 mA
Power-down 0.1 3
(1) Does not include the variation in voltage resulting from solder shift effects.
(2) These specifications include full temperature range variation but not the error contribution from internal reference. Measured with single-ended inputs as described in Wide Common-Mode Configuration for Single-Ended Inputs
(3) Wide-CM refers to wide-common-mode voltage at the analog inputs. See section on Section 6.3.1.3 for more details. 
(4) Thermal drift is the difference between maximum and minimum error measured over the temperature range, divided by the temperature range.
(5) Minimum and maximum specifications are applicable for low-bandwidth filter setting.