SBOS588B December   2011  – June 2019 AFE030

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram
  4. 4 Revision History
  5. 5 Description, continued
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics: Transmitter (Tx), Tx_DAC
    5. 7.5  Electrical Characteristics: Transmitter (Tx), Tx_PGA
    6. 7.6  Electrical Characteristics: Transmitter (Tx), Tx_FILTER
    7. 7.7  Electrical Characteristics: Power Amplifier (PA)
    8. 7.8  Electrical Characteristics: Receiver (Rx), Rx PGA1
    9. 7.9  Electrical Characteristics: Receiver (Rx), Rx Filter
    10. 7.10 Electrical Characteristics: Receiver (Rx), Rx PGA2
    11. 7.11 Electrical Characteristics: Digital
    12. 7.12 Electrical Characteristics: Two-Wire Interface
    13. 7.13 Electrical Characteristics: Zero-Crossing Detector
    14. 7.14 Electrical Characteristics: Internal Bias Generator
    15. 7.15 Electrical Characteristics: Power Supply
    16. 7.16 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Requirements
    2. 8.2 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 PA Block
      2. 9.3.2 Tx Block
      3. 9.3.3 Rx Block
      4. 9.3.4 DAC Block
      5. 9.3.5 REF1 and REF2 Blocks
      6. 9.3.6 Zero Crossing Detector Block
      7. 9.3.7 ETx and ERx Blocks
    4. 9.4 Power Supplies
    5. 9.5 Pin Descriptions
      1. 9.5.1 Current Overload
      2. 9.5.2 Thermal Overload
    6. 9.6 Calibration Modes
      1. 9.6.1 Tx Calibration Mode
      2. 9.6.2 Rx Calibration Mode
    7. 9.7 Serial Interface
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
    3. 10.3 Line-Coupling Circuit
    4. 10.4 Circuit Protection
    5. 10.5 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI™ (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH Filter Designer
      2. 11.1.2 Powerline Communications Developer’s Kit
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Timing Requirements

Table 1. SPI Timing Requirements

PARAMETER CONDITION MIN TYP MAX UNIT
Input capacitance 1 pF
Input rise/fall time tRFI CS, DIN, SCLK 2 ns
Output rise/fall time tRFO DOUT 10 ns
CS high time tCSH CS 20 ns
SCLK edge to CS fall setup time tCS0 10 ns
CS fall to first SCLK edge setup time tCSSC 10 ns
SCLK frequency fSCLK 20 MHz
SCLK high time tHI 20 ns
SCLK low time tLO 20 ns
SCLK last edge to CS rise setup time tSCCS 10 ns
CS rise to SCLK edge setup time tCS1 10 ns
DIN setup time tSU 10 ns
DIN hold time tHD 5 ns
SCLK to DOUT valid propagation delay tDO 20 ns
CS rise to DOUT forced to Hi-Z tsoz 20 ns