SBOS531E August   2010  – June 2019 AFE031

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
  4. 4 Revision History
  5. 5 Description, continued
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Thermal Information
    4. 8.4  Electrical Characteristics: Transmitter (Tx)
    5. 8.5  Electrical Characteristics: Power Amplifier (PA)
    6. 8.6  Electrical Characteristics: Receiver (Rx)
    7. 8.7  Electrical Characteristics: Digital
    8. 8.8  Electrical Characteristics: Two-Wire Interface
    9. 8.9  Electrical Characteristics: Internal Bias Generator
    10. 8.10 Electrical Characteristics: Power Supply
    11. 8.11 Timing Requirements
    12. 8.12 Timing Diagrams
    13. 8.13 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 PA Block
      2. 9.2.2 Tx Block
      3. 9.2.3 Rx Block
      4. 9.2.4 DAC Block
      5. 9.2.5 REF1 and REF2 Blocks
      6. 9.2.6 Zero Crossing Detector Block
      7. 9.2.7 ETx and ERx Blocks
    3. 9.3 Power Supplies
    4. 9.4 Pin Descriptions
      1. 9.4.1 Current Overload
      2. 9.4.2 Thermal Overload
    5. 9.5 Calibration Modes
      1. 9.5.1 Tx Calibration Mode
      2. 9.5.2 Rx Calibration Mode
    6. 9.6 Serial Interface
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Detailed Design Procedure
        1. 10.2.1.1 Line-Coupling Circuit
        2. 10.2.1.2 Circuit Protection
        3. 10.2.1.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Powerline Communications Developer’s Kit
        2. 11.1.2.2 TINA-TI™ (Free Software Download)
        3. 11.1.2.3 TI Precision Designs
        4. 11.1.2.4 WEBENCH Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.4 DAC Block

The DAC block consists only of the 10-bit DAC. The use of the DAC is recommended for best performance. The serial interface is used to write directly to the DAC registers when the DAC pin (pin 7) is driven high. Placing the DAC pin into a high state configures the SPI for direct serial interface to the DAC. Use the following sequence to write to the DAC:

  • Set CS low.
  • Set the DAC pin (pin 7) high.
  • Write a 10-bit word to DIN. The DAC register is left-justified and truncates more than 10 bits.
  • CS high updates the DAC.

Refer to Figure 34 for an illustration of this sequence.

AFE031 ai_tim_dac_bos531.gif

NOINDENT:

NOTE: Dashed lines indicate optional additional clocks (data are ignored).
Figure 34. Writing to the DAC Register

Table 6 lists the DAC Register configurations.

Table 6. DAC Registers

DAC PIN HIGH:
DAC REGISTER <15:0>		 LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
BIT NAME
DAC<0> 0 -- W Truncated
DAC<1> 1 -- W Truncated
DAC<2> 2 -- W Truncated
DAC<3> 3 -- W Truncated
DAC<4> 4 -- W Truncated
DAC<5> 5 -- W Truncated
DAC<6> 6 -- W DAC bit 0 = DAC LSB
DAC<7> 7 -- W DAC bit 1
DAC<8> 8 -- W DAC bit 2
DAC<9> 9 -- W DAC bit 3
DAC<10> 10 -- W DAC bit 4
DAC<11> 11 -- W DAC bit 5
DAC<12> 12 -- W DAC bit 6
DAC<13> 13 -- W DAC bit 7
DAC<14> 14 -- W DAC bit 8
DAC<15> 15 -- W DAC bit 9 = DAC MSB