SBOS531E August   2010  – June 2019 AFE031

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
  4. 4 Revision History
  5. 5 Description, continued
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Thermal Information
    4. 8.4  Electrical Characteristics: Transmitter (Tx)
    5. 8.5  Electrical Characteristics: Power Amplifier (PA)
    6. 8.6  Electrical Characteristics: Receiver (Rx)
    7. 8.7  Electrical Characteristics: Digital
    8. 8.8  Electrical Characteristics: Two-Wire Interface
    9. 8.9  Electrical Characteristics: Internal Bias Generator
    10. 8.10 Electrical Characteristics: Power Supply
    11. 8.11 Timing Requirements
    12. 8.12 Timing Diagrams
    13. 8.13 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 PA Block
      2. 9.2.2 Tx Block
      3. 9.2.3 Rx Block
      4. 9.2.4 DAC Block
      5. 9.2.5 REF1 and REF2 Blocks
      6. 9.2.6 Zero Crossing Detector Block
      7. 9.2.7 ETx and ERx Blocks
    3. 9.3 Power Supplies
    4. 9.4 Pin Descriptions
      1. 9.4.1 Current Overload
      2. 9.4.2 Thermal Overload
    5. 9.5 Calibration Modes
      1. 9.5.1 Tx Calibration Mode
      2. 9.5.2 Rx Calibration Mode
    6. 9.6 Serial Interface
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Detailed Design Procedure
        1. 10.2.1.1 Line-Coupling Circuit
        2. 10.2.1.2 Circuit Protection
        3. 10.2.1.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Powerline Communications Developer’s Kit
        2. 11.1.2.2 TINA-TI™ (Free Software Download)
        3. 11.1.2.3 TI Precision Designs
        4. 11.1.2.4 WEBENCH Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

RGZ PACKAGE
QFN-48
(TOP VIEW)
AFE031 po_bos531.gif

NOTE:

Exposed thermal pad is connected to ground.

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND1 12 — Analog ground
AGND2 29 — Analog ground
AVDD1 11 — Analog supply
AVDD2 30 — Analog supply
CS 6 — SPI digital chip select
DAC 7 — DAC mode select
DIN 4 I SPI digital input
DGND 1 — Digital ground
DOUT 5 O SPI digital output
DVDD 2 — Digital supply
E_Rx_IN 32 I Two-wire receiver input
E_Rx_OUT 31 O Two-wire receiver output
E_Tx_CLK 35 I Two-wire transmitter clock input
E_Tx_IN 34 I Two-wire transmitter input
E_Tx_OUT 33 O Two-wire transmitter output
INT 9 — Interrupt on overcurrent or thermal limit
PA_GND1 41 — Power Amplifier ground
PA_GND2 40 — Power Amplifier ground
PA_IN 18 I Power Amplifier input
PA_ISET 46 — Power Amplifier current limit set
PA_OUT1 43 O Power Amplifier output
PA_OUT2 42 O Power Amplifier output
PA_VS1 45 — Power Amplifier supply
PA_VS2 44 — Power Amplifier supply
REF1 19 — Power Amplifier noise reducing capacitor
REF2 28 — Receiver noise reducing capacitor
Rx_C1 24 — Receiver external frequency select
Rx_C2 23 — Receiver external frequency select
Rx_F_IN 25 I Receiver filter input
Rx_F_OUT 22 O Receiver filter output
Rx_FLAG 48 — Receiver ready flag
Rx PGA1_IN 27 I Receiver PGA(1) input
Rx PGA1_OUT 26 O Receiver PGA(1) output
Rx PGA2_IN 21 I Receiver PGA(2) input
Rx PGA2_OUT 20 O Receiver PGA(2) output
SCLK 3 — SPI serial clock
SD 8 — System shutdown
TSENSE 10 — Temp sensing diode (anode)
Tx_F_IN1 15 I Transmit filter input 1
Tx_F_IN2 16 I Transmit filter input 2
Tx_F_OUT 17 O Transmit filter output
Tx_FLAG 47 — Transmitter ready flag
Tx_PGA_IN 13 I Transmit PGA input
Tx_PGA_OUT 14 O Transmit PGA output
ZC_IN1 39 I Zero crossing detector input
ZC_IN2 38 I Zero crossing detector input
ZC_OUT1 37 O Zero crossing detector output
ZC_OUT2 36 O Zero crossing detector output