SBOS531E August   2010  – June 2019 AFE031

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
  4. 4 Revision History
  5. 5 Description, continued
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Thermal Information
    4. 8.4  Electrical Characteristics: Transmitter (Tx)
    5. 8.5  Electrical Characteristics: Power Amplifier (PA)
    6. 8.6  Electrical Characteristics: Receiver (Rx)
    7. 8.7  Electrical Characteristics: Digital
    8. 8.8  Electrical Characteristics: Two-Wire Interface
    9. 8.9  Electrical Characteristics: Internal Bias Generator
    10. 8.10 Electrical Characteristics: Power Supply
    11. 8.11 Timing Requirements
    12. 8.12 Timing Diagrams
    13. 8.13 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 PA Block
      2. 9.2.2 Tx Block
      3. 9.2.3 Rx Block
      4. 9.2.4 DAC Block
      5. 9.2.5 REF1 and REF2 Blocks
      6. 9.2.6 Zero Crossing Detector Block
      7. 9.2.7 ETx and ERx Blocks
    3. 9.3 Power Supplies
    4. 9.4 Pin Descriptions
      1. 9.4.1 Current Overload
      2. 9.4.2 Thermal Overload
    5. 9.5 Calibration Modes
      1. 9.5.1 Tx Calibration Mode
      2. 9.5.2 Rx Calibration Mode
    6. 9.6 Serial Interface
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Detailed Design Procedure
        1. 10.2.1.1 Line-Coupling Circuit
        2. 10.2.1.2 Circuit Protection
        3. 10.2.1.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Powerline Communications Developer’s Kit
        2. 11.1.2.2 TINA-TI™ (Free Software Download)
        3. 11.1.2.3 TI Precision Designs
        4. 11.1.2.4 WEBENCH Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6 Serial Interface

The AFE031 is controlled through a serial interface that allows read/write access to the control and data registers. A host SPI frame consists of a R/W bit, a 6-bit register address, and eight data bits. Data are shifted out on the falling edge of SCLK and latched on the rising edge of SCLK. Refer to the Timing Diagrams for a valid host SPI communications protocol. Table 9 through Table 18 show the complete register information.

Table 9. Data Register

REGISTER ADDRESS DEFAULT FUNCTION
ENABLE1 0x01 0x00 Block enable or disable
GAIN SELECT 0x02 0x32 Rx and Tx gain select
ENABLE2 0x03 0x00 Block enable or disable
CONTROL1 0x04 0x00 Frequency select and calibration, Tx and Rx status
CONTROL2 0x05 0x01 Interrupt enable
RESET 0x09 0x00 Interrupt status and device reset
DIE_ID 0x0A 0x00 Die name
REVISION 0x0B 0x02 Die revision

Table 10. Command Register

BIT NAME LOCATION
(15 = MSB)		 R/W FUNCTION
ADDR8 8 W Register address bit
ADDR9 9 W Register address bit
ADDR10 10 W Register address bit
ADDR11 11 W Register address bit
ADDR12 12 W Register address bit
ADDR13 13 W Register address bit
ADDR14 14 W Register address bit
R/W 15 W Read/write: read = 1, write = 0

Table 11. Enable1 Register: Address 0x01
Default: 0x00

Enable1 Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
PA 0 0 R/W This bit is used to enable/disable the PA Block.
0 = disabled, 1 = enabled.
TX 1 0 R/W This bit is used to enable/disable the Tx Block.
0 = disabled, 1 = enabled.
RX 2 0 R/W This bit is used to enable/disable the Rx Block.
0 = disabled, 1 = enabled.
ERX 3 0 R/W This bit is used to enable/disable the ERx Block.
0 = disabled, 1 = enabled.
ETX 4 0 R/W This bit is used to enable/disable the ETx Block.
0 = disabled, 1 = enabled.
DAC 5 0 R/W This bit is used to enable/disable the DAC Block.
0 = DAC disabled; switch is connected to Tx_PGA_IN pin.
1 = DAC enabled; switch is connected to DAC output.
-- 6 0 -- Reserved
-- 7 0 -- Reserved

Table 12. Gain Select Register: Address 0x02
Default: 0x32

Gain Select Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
RX1G-0,
RX1G-1		 0, 1 0, 1 R/W This bit is used to set the gain of the Rx PGA1.
00 = 0.25 V/V
01 = 0.5 V/V
10 = 1 V/V
11 = 2 V/V
RX2G-0,
RX2G-1		 2, 3 0, 0 R/W This bit is used to set the gain of the Rx PGA2.
00 = 1 V/V
01 = 4 V/V
10 = 16 V/V
11 = 64 V/V
TXG-0,
TXG-1		 4, 5 1, 1 R/W This bit is used to set the gain of the Tx PGA.
00 = 0.25 V/V
01 = 0.5 V/V
10 = 0.707 V/V
11 = 1 V/V
-- 6 0 -- Reserved
-- 7 0 -- Reserved

Table 13. Enable2 Register: Address 0x03
Default: 0x00

Enable2 Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
ZC 0 0 R/W This bit is used to enable/disable the ZC Block.
0 = disabled, 1 = enabled.
REF1 1 0 R/W This bit is used to enable/disable the REF1 Block.
0 = disabled, 1 = enabled.
REF2 2 0 R/W This bit is used to enable/disable the REF2 Block.
0 = disabled, 1 = enabled.
PA_OUT 3 0 R/W This bit is used to enable/disable the PA output stage.
When the PA output stage is enabled it functions normally with a low output impedance, capable of driving heavy loads.
When the PA output stage is disabled it is placed into a high impedance state.
0 = disabled, 1 = enabled.
-- 4 0 -- Reserved
-- 5 0 -- Reserved
-- 6 0 -- Reserved
-- 7 0 -- Reserved

Table 14. Control1 Register: Address 0x04
Default: 0x00

Control1 Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
TX_CAL 0 0 R/W This bit is used to enable/disable the TX calibration mode.
0 = disabled, 1 = enabled.
RX_CAL 1 0 R/W This bit is used to enable/disable the RX calibration mode.
0 = disabled, 1 = enabled.
— 2 0 — Reserved
CA_CBCD 3 0 R/W This bit is used to select the frequency response of the Tx Filter and Rx Filter.
0 = CENELEC A
1 = CENELEC B, C, D
-- 4 0 -- Reserved
-- 5 0 -- Reserved
TX_FLAG 6 0 R This bit is used to indicate the status of the Tx Block.
0 = Tx Block is not ready for transmission.
1 = Tx Block is ready for transmission.
RX_FLAG 7 0 R This bit is used to indicate the status of the Rx Block.
0 = Rx Block is not ready for reception.
1 = Rx Block is ready for reception.

Table 15. Control2 Register: Address 0x05
Default: 0x01

Control2 Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
-- 0 0 -- Reserved
-- 1 0 -- Reserved
-- 2 0 -- Reserved
-- 3 0 -- Reserved
-- 4 0 -- Reserved
T_FLAG_EN 5 0 R/W This bit is used to enable/disable the T_flag bit in the RESET Register.
0 = disabled, 1 = enabled.
I_FLAG_EN 6 0 R/W This bit is used to enable/disable the I_flag bit in the RESET Register.
0 = disabled, 1 = enabled.
-- 7 X -- Reserved

Table 16. RESET Register: Address 0x09
Default: 0x00

Reset Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
-- 0 0 -- Reserved
-- 1 0 -- Reserved
SOFTRST0,
SOFTRST1,
SOFTRST2		 2, 3, 4 0, 0, 0 W These bits are used to perform a software reset of the ENABLE1, ENABLE2, CONTROL2, CONTROL3, and GAIN SELECT registers. Writing '101' to these registers performs a software reset.
T_FLAG 5 0 R/W This bit is used to indicate the status of a PA thermal overload.
0 = On read, indicates that no thermal overload has occurred since the last reset.
0 = On write, resets this bit.
1 = On read, indicates that a thermal overload has occurred since the last reset. Remains latched until reset.
I_FLAG 6 0 R/W This bit is used to indicate the status of a PA output current overload.
0 = On read indicates that no current overload has occurred since the last reset.
0 = On write, resets this bit.
1 = On read indicates that a current overload has occurred since the last reset. Remains latched until reset.
-- 7 0 -- Reserved

Table 17. DieID Register: Address 0x0A
Default: 0x00

DieID Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
DIE ID<0> 0 0 R The Die ID register is hard-wired.
DIE ID<1> 1 0 R The Die ID register is hard-wired.
DIE ID<2> 2 0 R The Die ID register is hard-wired.
DIE ID<3> 3 0 R The Die ID register is hard-wired.
DIE ID<4> 4 0 R The Die ID register is hard-wired.
DIE ID<5> 5 0 R The Die ID register is hard-wired.
DIE ID<6> 6 0 R The Die ID register is hard-wired.
DIE ID<7> 7 0 R The Die ID register is hard-wired.

Table 18. Revision Register: Address 0x0B
Default: 0x02

Revision Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
REVISION ID<0> 0 0 R The revision register is hard-wired.
REVISION ID<1> 1 1 R The revision register is hard-wired.
REVISION ID<2> 2 0 R The revision register is hard-wired.
REVISION ID<3> 3 0 R The revision register is hard-wired.
REVISION ID<4> 4 0 R The revision register is hard-wired.
REVISION ID<5> 5 0 R The revision register is hard-wired.
REVISION ID<6> 6 0 R The revision register is hard-wired.
REVISION ID<7> 7 0 R The revision register is hard-wired.