SBOS531E August   2010  – June 2019 AFE031

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
  4. 4 Revision History
  5. 5 Description, continued
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Thermal Information
    4. 8.4  Electrical Characteristics: Transmitter (Tx)
    5. 8.5  Electrical Characteristics: Power Amplifier (PA)
    6. 8.6  Electrical Characteristics: Receiver (Rx)
    7. 8.7  Electrical Characteristics: Digital
    8. 8.8  Electrical Characteristics: Two-Wire Interface
    9. 8.9  Electrical Characteristics: Internal Bias Generator
    10. 8.10 Electrical Characteristics: Power Supply
    11. 8.11 Timing Requirements
    12. 8.12 Timing Diagrams
    13. 8.13 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 PA Block
      2. 9.2.2 Tx Block
      3. 9.2.3 Rx Block
      4. 9.2.4 DAC Block
      5. 9.2.5 REF1 and REF2 Blocks
      6. 9.2.6 Zero Crossing Detector Block
      7. 9.2.7 ETx and ERx Blocks
    3. 9.3 Power Supplies
    4. 9.4 Pin Descriptions
      1. 9.4.1 Current Overload
      2. 9.4.2 Thermal Overload
    5. 9.5 Calibration Modes
      1. 9.5.1 Tx Calibration Mode
      2. 9.5.2 Rx Calibration Mode
    6. 9.6 Serial Interface
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Detailed Design Procedure
        1. 10.2.1.1 Line-Coupling Circuit
        2. 10.2.1.2 Circuit Protection
        3. 10.2.1.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Powerline Communications Developer’s Kit
        2. 11.1.2.2 TINA-TI™ (Free Software Download)
        3. 11.1.2.3 TI Precision Designs
        4. 11.1.2.4 WEBENCH Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2 Tx Block

The Tx block consists of the Tx PGA and Tx Filter. The Tx PGA is a low-noise, high-performance, programmable gain amplifier. In DAC mode (where pin 7 is a logical '1' and Enable1 Register bit location 5 is a logical '1'), the Tx PGA operates as the internal digital-to-analog converter (DAC) output buffer with programmable gain. In PWM mode (where pin 7 is a logical '0' and Enable1 Register bit location 5 is a logical '0'), the Tx PGA operates as a stand-alone programmable gain amplifier. The Tx PGA gain is programmed through the serial interface. The Tx PGA gain settings are 0.25 V/V, 0.5 V/V, 0.707 V/V, and 1 V/V.

The Tx Filter is a unity-gain, fourth-order low-pass filter. The Tx Filter cutoff frequency is selectable between CENELEC A or CENELEC B, C, and D modes. The Control1 Register bit location 3 setting (CA CBCD) determines the cutoff frequency. Setting Control1 Register bit location 3 to '0' selects the CENELEC A band; setting Control1 Register bit location 3 to '1' selects CENELEC B, C, and D bands.

The AFE031 supports both DAC inputs or PWM inputs for the Tx signal path. DAC mode is recommended for best performance. In DAC mode, no external components in the Tx signal path are required to meet regulatory signal emissions requirements. When in DAC mode, the AFE031 accepts serial data from the microprocessor and writes that data to the internal DAC registers. When in DAC mode (where pin 7 is a logical '1' and Enable1 Register bit location 5 is a logical '1'), the Tx PGA output must be directly coupled to the Tx_FIN1 input and the unused Tx_FIN2 input must be grounded.

The proper connections for the Tx signal path for DAC mode operation are shown in Figure 26. Operating in DAC mode results in the lowest distortion signal injected onto the ac mains. No additional external filtering components are required to meet CENELEC requirements for A, B, C or D bands when operating in DAC mode.

AFE031 ai_tx_signal_path_bos531.gif
1. For capacitor value C, f is the desired lower cutoff frequency and 22 kΩ is the PA input resistance.
Figure 26. Recommended Tx Signal Chain Connections Using DAC Mode

In PWM mode (where pin 7 is a logical '0' and Enable1 Register bit location 5 is a logical '0'), the microprocessor general-purpose input/output (GPIO) can be connected directly to either one of the Tx Filter inputs; the unused input should remain unconnected. A lower distortion PWM signal generated from two PWM signals shifted in phase by 90 degrees can be also be input to the Tx Filter through the use of both inputs. Figure 27 and Figure 28 show the proper connections for single PWM and dual PWM operating modes, respectively.

AFE031 ai_tx_signal_path_single_pwm_bos531.gif
1. Leave unused Tx Filter input unconnected.
2. For capacitor value C, f is the desired lower cutoff frequency and 22 kΩ is the PA input resistance.
Figure 27. Recommended Tx Signal Chain Connections in PWM Mode Using One PWM Signal
AFE031 ai_tx_signal_path_dual_pwm_bos531.gif
1. When using both Tx Filter inputs, use 43-kΩ resistors to match the input resistance for best frequency response.
2. For capacitor value C, f is the desired lower cutoff frequency and 22 kΩ is the PA input resistance.
Figure 28. Recommended Tx Signal Chain Connections in PWM Mode Using Two PWM Signals

In PWM mode, there is inherently more distortion from the PWM signal than from the internal DAC. To achieve the best results in PWM mode, add passive RC filters to increase the low-pass filtering. Figure 29 and Figure 30 illustrate the recommended locations of these RC filters.

AFE031 ai_tx_signal_path_single_pwm_rc_bos531.gif
1. Leave unused Tx Filter input unconnected.
2. Refer to Table 2.
3. For capacitor value C, f is the desired lower cutoff frequency and 22 kΩ is the PA input resistance.
Figure 29. Recommended Tx Signal Chain Connections in PWM Mode
Using One PWM Signal and Additional RC Filters
AFE031 ai_tx_signal_path_dual_pwm_rc_bos531.gif
1. When using both Tx Filter inputs, use 43-kΩ resistors to match the input resistance for best frequency response.
2. Refer to Table 2.
3. For capacitor value C, f is the desired lower cutoff frequency and 22 kΩ is the PA input resistance.
Figure 30. Recommended Tx Signal Chain Connections in PWM Mode
Using Two PWM Signals and Additional RC Filters

For the capacitors listed in Table 2, it is recommended that these components be rated to withstand the full AVDD power-supply voltage.

Table 2. Recommended External R and C Values to Increase Tx Filter Response Order in PWM Applications

FREQUENCY BAND R (Ω) C (nF)
SFSK: 63 kHz, 74 kHz 510 2.7
CENELEC A 510 1.5
CENELEC B, C, D 510 1

The Tx PGA and Tx Filter each have the inputs and outputs externally available in order to provide maximum system design flexibility. Care should be taken when laying out the PCB traces from the inputs or outputs to avoid excessive capacitive loading. Keeping the PCB capacitance from the inputs to ground, or from the outputs to ground, less than 100 pF is recommended.