SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
A2 | 11 | I | Target address selection A2 for I2C when the SPI/I2C pin is low. |
ADC-GND | 32 | I | ADC ground. Must be connected to AGND. |
ADC-REF-IN/CMP | 31 | I/O | External ADC reference input when external VREF is used to drive the ADC. A compensation capacitor connection (connect a 4.7-µF capacitor between this pin and AGND) when internal VREF is used to drive the ADC. |
AGND1 | 54 | I | Analog ground |
AGND2 | 55 | I | Analog ground |
AGND3 | 22 | I | Analog ground |
AGND4 | 21 | I | Analog ground |
ALARM | 62 | O | Global alarm. Open-drain output. An external 10-kΩ pullup resistor is required. This pin goes low (active) when one (or more) analog channels are out of range. |
AVCC1 | 56 | I | Positive analog power for DAC6-OUT, DAC7-OUT, DAC8-OUT, DAC9-OUT, DAC10-OUT, and DAC11-OUT; must be tied to AVCC2 |
AVCC2 | 23 | I | Positive analog power for DAC0-OUT, DAC1-OUT, DAC2-OUT, DAC3-OUT, DAC4-OUT, and DAC5-OUT; must be tied to AVCC1 |
AVDD1 | 49 | I | Positive analog power supply |
AVDD2 | 50 | I | Positive analog power supply |
CH0 | 33 | I | Analog input of channel 0. CH0, CH1, CH2, and CH3 can be programmed as differential or single-ended. |
CH1 | 34 | I | Analog input of channel 1. CH0, CH1, CH2, and CH3 can be programmed as differential or single-ended. |
CH2 | 35 | I | Analog input of channel 2. CH0, CH1, CH2, and CH3 can be programmed as differential or single-ended. |
CH3 | 36 | I | Analog input of channel 3. CH0, CH1, CH2, and CH3 can be programmed as differential or single-ended. |
CH4 | 37 | I | Analog input of channel 4. CH4 to CH15 are single-ended. |
CH5 | 38 | I | Analog input of channel 5. CH4 to CH15 are single-ended. |
CH6 | 39 | I | Analog input of channel 6. CH4 to CH15 are single-ended. |
CH7 | 40 | I | Analog input of channel 7. CH4 to CH15 are single-ended. |
CH8 | 41 | I | Analog input of channel 8. CH4 to CH15 are single-ended. |
CH9 | 42 | I | Analog input of channel 9. CH4 to CH15 are single-ended. |
CH10 | 43 | I | Analog input of channel 10. CH4 to CH15 are single-ended. |
CH11 | 44 | I | Analog input of channel 11. CH4 to CH15 are single-ended. |
CH12 | 45 | I | Analog input of channel 12. CH4 to CH15 are single-ended. |
CH13 | 46 | I | Analog input of channel 13. CH4 to CH15 are single-ended. |
CH14 | 47 | I | Analog input of channel 14. CH4 to CH15 are single-ended. |
CH15 | 48 | I | Analog input of channel 15. CH4 to CH15 are single-ended. |
CNVT | 3 | I | External conversion trigger, active low. The falling edge initiates the sampling and conversion of the ADC. |
CS/A0 | 9 | I | Chip-select signal for SPI when the SPI/I2C pin high. Target address selection A0 for I2C when SPI/I2C low. |
D1–/GPIO4 | 29 | I/O | Remote sensor D1 negative input when D1 enabled; GPIO-6 when D1 disabled. Pullup resistor required for output. |
D1+/GPIO-5 | 30 | I/O | Remote sensor D1 positive input when D1 enabled; GPIO-7 when D1 disabled. Pullup resistor required for output. |
D2–/GPIO-6 | 27 | I/O | Remote sensor D2 negative input when D2 enabled; GPIO-6 when D2 disabled. Pullup resistor required for output. |
D2+/GPIO-7 | 28 | I/O | Remote sensor D2 positive input when D2 enabled; GPIO-7 when D2 disabled. Pullup resistor required for output. |
DAC0-OUT | 26 | O | DAC channel 0 output |
DAC1-OUT | 25 | O | DAC channel 1 output |
DAC2-OUT | 24 | O | DAC channel 2 output |
DAC3-OUT | 20 | O | DAC channel 3 output |
DAC4-OUT | 19 | O | DAC channel 4 output |
DAC5-OUT | 18 | O | DAC channel 5 output |
DAC6-OUT | 51 | O | DAC channel 6 output |
DAC7-OUT | 52 | O | DAC channel 7 output |
DAC8-OUT | 53 | O | DAC channel 8 output |
DAC9-OUT | 59 | O | DAC channel 9 output |
DAC10-OUT | 60 | O | DAC channel 10 output |
DAC11-OUT | 61 | O | DAC channel 11 output |
DAC-CLR-0 | 17 | I | DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-0 pin enter a CLEAR state, the DAC latch is loaded with a predefined code, and the output is set to the corresponding level. However, the DAC-data register does not change. When the DAC goes back to normal operation, the DAC latch is loaded with the previous data from the DAC-data register and the output returns to the previous level, regardless of the status of the SLDAC-n bit. When this pin is high, the DACs are in normal operation. |
DAC-CLR-1 | 63 | I | DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-1 pin enter a CLEAR state, the DAC latch is loaded with a predefined code, and the output is set to the corresponding level. However, the DAC-data register does not change. When the DAC goes back to normal operation, the DAC latch is loaded with the previous data from the DAC-data register and the output returns to the previous level, regardless of the status of the SLDAC-n bit. When this pin is high, the DACs are in normal operation. |
DAV | 2 | O | Data available indicator, active low output. In direct mode, the DAV pin goes low (active) when the conversion ends. In auto mode, a 1-µs pulse (active low) appears on this pin when a conversion cycle completes (for details, see the Primary ADC Operation and Register Maps sections). DAV stays high when deactivated. |
DGND | 6 | I | Digital ground |
DGND2 | 64 | I | Digital ground |
DVDD | 8 | I | Digital power supply (3 V to 5 V). Must be the same value as AVDD. |
GPIO-0 | 13 | I/O | General-purpose digital input and output. This bidirectional, open-drain, digital I/O pin requires an external pullup resistor. For more details, see the General-Purpose Input and Output Pins (GPIO-0 To GPIO-7) section. |
GPIO-1 | 14 | I/O | General-purpose digital input and output. This bidirectional, open-drain, digital I/O pin requires an external pullup resistor. For more details, see the General-Purpose Input and Output Pins (GPIO-0 To GPIO-7) section. |
GPIO-2 | 15 | I/O | General-purpose digital input and output. This bidirectional, open-drain, digital I/O pin requires an external pullup resistor. For more details, see the General-Purpose Input and Output Pins (GPIO-0 To GPIO-7) section. |
GPIO-3 | 16 | I/O | General-purpose digital input and output. This bidirectional, open-drain, digital I/O pin requires an external pullup resistor. For more details, see the General-Purpose Input and Output Pins (GPIO-0 To GPIO-7) section. |
IOVDD | 7 | I | Interface power supply |
REF-DAC | 58 | I | DAC reference input |
REF-OUT | 57 | O | Internal reference output |
RESET | 1 | I | Reset input, active low. A logic low on this pin causes the device to perform a hardware reset. |
SCLK/SCL | 5 | I | Serial clock input of the main serial interface. This pin functions as the SPI clock when the SPI/I2C pin is high. This pin functions as the I2C clock when the SPI/I2C pin is low. |
SDI/SDA | 4 | I/O | Serial interface data. This pin functions as SDI for the serial peripheral interface (SPI) when the SPI/I2C pin (pin 12) is high. This pin functions as SDA for the I2C interface when the SPI/I2C pin is low. |
SDO/A1 | 10 | I/O | SDO for SPI when the SPI/I2C pin is high. Target address selection A1 for I2C when the SPI/I2C pin is low. |
SPI/I2C | 12 | I | Interface selection pin; digital input. When this pin is tied to IOVDD, the SPI is enabled and the I2C interface is disabled. When this pin is tied to ground, the SPI is disabled and the I2C interface is enabled. |