SLASF77A
December 2022 – September 2023
AFE11612-SEP
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Characteristics
6.7
Timing Diagrams
6.8
Typical Characteristics: DAC
6.9
Typical Characteristics: ADC
6.10
Typical Characteristics: Internal Reference
6.11
Typical Characteristics: Temperature Sensor
6.12
Typical Characteristics: Digital Inputs
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Primary ADC Operation
7.3.1.1
Analog Inputs
7.3.1.1.1
Single-Ended Analog Input
7.3.1.1.2
Fully Differential Input
7.3.1.2
ADC Trigger Signals (See AFE configuration register 0 )
7.3.1.3
Double-Buffered ADC Data Registers
7.3.1.3.1
ADC Data Format
7.3.1.4
SCLK Clock Noise Reduction
7.3.1.5
Data Available Pin (DAV)
7.3.1.6
Convert Pin (CNVT)
7.3.1.7
Analog Input Out-of-Range Detection (See The Analog Input Out-of-Range Alarm Section)
7.3.1.8
Full-Scale Range of the Analog Input
7.3.2
Secondary ADC and Temperature Sensor Operation
7.3.2.1
Remote Sensing Diode
7.3.2.2
Ideality Factor
7.3.2.3
Filtering
7.3.2.4
Series Resistance Cancellation
7.3.2.5
Reading Temperature Data
7.3.2.6
Conversion Time
7.3.3
Reference Operation
7.3.3.1
Internal Reference
7.3.3.2
External Reference
7.3.4
DAC Operation
7.3.4.1
Resistor String
7.3.4.2
DAC Output
7.3.4.2.1
Full-Scale Output Range
7.3.4.2.2
DAC Output After Power-On Reset
7.3.4.3
Double-Buffered DAC Data Registers
7.3.4.4
Load DAC Latch
7.3.4.5
Synchronous Output Updating
7.3.4.6
Clear DACs
7.3.4.7
DAC Output Thermal Protection
7.3.5
Alarm Operation
7.3.5.1
Analog Input Out-of-Range Alarm
7.3.5.2
ALARM Pin
7.3.5.3
Hysteresis
7.3.5.4
False-Alarm Protection
7.3.6
General-Purpose Input and Output Pins (GPIO-0 To GPIO-7)
7.3.7
Device Reset Options
7.3.7.1
Hardware Reset
7.3.7.2
Software Reset
7.3.7.3
Power-On Reset (POR)
7.4
Device Functional Modes
7.4.1
DAC Output Mode
7.4.2
ADC Conversion Modes
7.4.2.1
Programmable Conversion Rate
7.4.2.2
Handshaking with the Host (See AFE configuration register 0 )
7.5
Programming
7.5.1
I2C-Compatible Interface
7.5.1.1
F/S-Mode Protocol
7.5.1.2
Hs-Mode Protocol
7.5.1.3
Address Pointer
7.5.1.4
Timeout Function
7.5.1.5
Device Communication Protocol For I2C
7.5.1.5.1
Writing A Single Register ( )
7.5.1.5.2
Writing Multiple Registers ( )
7.5.1.5.3
Reading a Single Register ( )
7.5.1.5.4
Reading Multiple Registers ( and )
7.5.2
Serial Peripheral Interface (SPI)
7.5.2.1
SPI Shift Register
7.5.2.2
SPI Communications Command
7.5.2.3
Standalone Operation
7.5.2.4
Daisy-Chain Operation
7.6
Register Maps
7.6.1
Temperature Data Registers (Read-Only)
7.6.1.1
LT-Temperature-Data (LT_TEMP) Register (address = 00h) [reset = 0000h, 0°C]
7.6.1.2
D1-Temperature-Data (D1_TEMP) Register (address = 01h) [reset = 0000h, 0°C]
7.6.1.3
D2-Temperature-Data (D2_TEMP) Register (address = 02h) [reset = 0000h, 0°C]
7.6.2
Temperature Configuration (TEMP_CONFIG) Register (address = 0Ah) [reset = 003Ch or 3CFFh]
7.6.3
Temperature Conversion Rate (TEMP_CONV_RATE) Register (address = 0Bh) [reset = 0007h or 07FFh]
7.6.4
η-Factor Correction Registers: D1_N_ADJUST and D2_N_ADJUST (address = 21h and 22h) [reset = 0000h or 00FFh]
7.6.5
ADC-n-Data (ADC_n) Registers (addresses = 23h to 32h) [reset = 0000h]
7.6.6
DAC-n-Data (DAC_n) Registers (addresses = 33h to 3Eh) [reset = 0000h)
7.6.7
DAC-n-CLR-Setting (DAC_n_CLR) Registers (addresses = 3Fh to 4Ah) [reset = 0000h]
7.6.8
GPIO Register (address = 4Bh) [reset = 00FFh]
7.6.9
AFE Configuration Register 0 (AFE_CONFIG_0) (address = 4Ch) [reset = 2000h]
7.6.10
AFE Configuration Register 1 (AFE_CONFIG_1) (Address = 4Dh) [reset = 0070h]
7.6.11
Alarm Control Register (ALR_CTRL) (address = 4Eh) [reset = 0000h]
7.6.12
STATUS Register (Address = 4Fh) [reset = 0000h]
7.6.13
ADC Channel Register 0 (ADC_CH0) (address = 50h) [reset = 0000h]
7.6.14
ADC Channel Register 1 (ADC_CH1) (address = 51h) [reset = 0000h]
7.6.15
ADC Gain Register (ADC_GAIN) (address = 52h) [reset = FFFFh]
7.6.16
AUTO_DAC_CLR_SOURCE Register (address = 53h) [reset = 0004h]
7.6.17
AUTO_DAC_CLR_EN Register (address = 54h) [reset = 0000h]
7.6.18
SW_DAC_CLR Register (address = 55h) [reset = 0000h]
7.6.19
HW_DAC_CLR_EN_0 Register (address = 56h) [reset = 0000h]
7.6.20
HW_DAC_CLR_EN_1 Register (address = 57h) [reset = 0000h]
7.6.21
DAC Configuration (DAC_CONFIG) Register (address = 58h) [reset = 0000h]
7.6.22
DAC Gain (DAC_GAIN) Register (address = 59h) [reset = 0000h]
7.6.23
Analog Input Channel Threshold Registers (addresses = 5Ah To 61h)
7.6.23.1
Input-n-High-Threshold Register (where n = 0, 1, 2, 3; addresses: 0 = 5Ah, 1 = 5Ch, 2 = 5Eh, 3 = 60h) [reset = 0FFFh]
7.6.23.2
Input-n-Low-Threshold Register (where n = 0, 1, 2, 3; addresses: 0 = 5Bh, 1 = 5Dh, 2 = 5Fh, 3 = 61h) (reset = 0000h)
7.6.24
Temperature Threshold Registers
7.6.24.1
LT_HIGH_THRESHOLD Register (address = 62h) [reset = 07FFh, +255.875°C]
7.6.24.2
LT_LOW_THRESHOLD Register (address = 63h) [reset = 0800h, –256°C]
7.6.24.3
D1_HIGH_THRESHOLD Register (address = 64h) [reset = 07FFh, +255.875°C]
7.6.24.4
D1_LOW_THRESHOLD Register (address = 65h) [reset = 0800h, –256°C]
7.6.24.5
D2_HIGH_THRESHOLD Register (address = 66h) [reset = 07FFh, +255.875°C]
7.6.24.6
D2_LOW_THRESHOLD Register (address = 67h) [reset = 0800h, –256°C]
7.6.25
Hysteresis Registers
7.6.25.1
Hysteresis Register 0 (HYST_0) (address = 68h) [reset = 0810h, 8 LSB]
7.6.25.2
Hysteresis Register 1 (HYST_1) (address = 69h) [reset = 0810h, 8 LSB]
7.6.25.3
Hysteresis Register 2 (HYST_2) (address = 6Ah) [reset = 2108h, 8°C]
7.6.26
Power-Down Register (PWR_DOWN) (address = 6Bh) [reset = 0000h)
7.6.27
Device ID Register (DEVICE_ID) (read only address = 6Ch) [reset = 1220h]
7.6.28
Software Reset (SW_RST) Register (read or write address = 7Ch) [reset = N/A)
7.6.28.1
SPI Mode
7.6.28.2
I2C Mode
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Sequencing
8.2.2.2
Negative GaN Biasing
8.2.2.3
VDRAIN Monitoring
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.3.1
Power-Supply Sequence
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Diagram
9
Device and Documentation Support
9.1
Documentation Support
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PAP|64
MPQF071C
Thermal pad, mechanical data (Package|Pins)
PAP|64
PPTD050N
Orderable Information
slasf77a_oa
1
Features
Radiation tolerant:
Single-event latch-up (SEL) immune up to
LET = 43 MeV-cm
2
/mg at 125°C
Single-event functional interrupt (SEFI) characterized up to LET = 43 MeV-cm
2
/mg
Total ionizing dose (TID) RLAT/RHA characterized up to 20 krad(Si)
Space-enhanced plastic (space EP):
Meets ASTM E595 outgassing specification
Vendor item drawing (VID) V62/22614
Military temperature range: –55°C to +125°C
One fabrication, assembly, and test site
Gold bond wire, NiPdAu lead finish
Wafer lot traceability
Extended product life cycle
12 monotonic, 12-bit DACs
0 V to 5 V output range
DAC shutdown to user-defined level
16 input, 12-bit SAR ADC
High sample rate: 500 kSPS
16 single-ended inputs or
2 differential and 12 single-ended inputs
Programmable out-of-range alarms
Eight GPIO pins
Internal 2.5-V reference
Two remote temperature sensors
Internal temperature sensor
Configurable SPI and I
2
C interface
2.7-V to 5.5-V operation