SLASF96 April   2024 AFE20408

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Register Structure
          1. 6.3.1.2.1 DAC Synchronous Operation
        3. 6.3.1.3 DAC Buffer Amplifier
          1. 6.3.1.3.1 Autorange Detection
          2. 6.3.1.3.2 Power-Supply Monitoring
      2. 6.3.2 Analog-to-Digital Converter (ADC)
        1. 6.3.2.1 Versatile High-Voltage Measurement Capability
        2. 6.3.2.2 High-Precision Delta-Sigma ADC
          1. 6.3.2.2.1 ADC Custom Channel Sequencer
        3. 6.3.2.3 Low Latency Digital Filter
        4. 6.3.2.4 Flexible Conversion Times and Averaging
        5. 6.3.2.5 Integrated Precision Oscillator
      3. 6.3.3 Output Switch Overview
      4. 6.3.4 Drain Switch Control
      5. 6.3.5 FLEXIO Pin
      6. 6.3.6 Internal Temperature Sensor
      7. 6.3.7 Programmable Out-of-Range Alarms
        1. 6.3.7.1 Temperature Sensor Alarm Function
        2. 6.3.7.2 Supply Out-of-Range Alarm Function
        3. 6.3.7.3 ADC Alarm Function
    4. 6.4 Device Functional Modes
      1. 6.4.1 All-Positive DAC Range Mode
      2. 6.4.2 All-Negative DAC Range Mode
      3. 6.4.3 Mixed DAC Range Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 I2C Bus Overview
        2. 6.5.1.2 I2C Bus Definitions
        3. 6.5.1.3 I2C Target Address Selection
        4. 6.5.1.4 I2C Read and Write Operations
        5. 6.5.1.5 I2C Timeout Function
        6. 6.5.1.6 I2C General-Call Reset
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Bus Overview
  8. 7 Register Maps
    1. 7.1 Global Register Map
      1. 7.1.1 Global Registers: Global Page
        1. 7.1.1.1  NOP_RESET Register (address = 00h) [reset = 0000h]
        2. 7.1.1.2  PAGE Register (address = 01h) [reset = 0000h]
        3. 7.1.1.3  GEN_STATUS Register (address = 03h) [reset = 4000h]
        4. 7.1.1.4  ALARM_STATUS_0 Register (address = 04h) [reset = 0000h]
        5. 7.1.1.5  ALARM_STATUS_1 Register (address = 05h) [reset = 0000h]
        6. 7.1.1.6  PWR_STATUS_0 Register (address = 06h) [reset = 0001h]
        7. 7.1.1.7  PWR_STATUS_1 Register (address = 07h) [reset = 0000h]
        8. 7.1.1.8  PWR_EN Register (address = 08h) [reset = 0200h]
        9. 7.1.1.9  TRIGGER Register (address = 10h) [reset = 0000h]
        10. 7.1.1.10 GPIO_DATA Register (address = 11h) [reset = 0001h]
        11. 7.1.1.11 DRVEN_SW_EN Register (address = 12h) [reset = 00FFh]
        12. 7.1.1.12 DRVEN Register (address = 13h) [reset = 0000h]
        13. 7.1.1.13 DAC_BCAST Register (address = 14h) [reset = 0000h]
        14. 7.1.1.14 GLOBAL_CFG Register (address = 17h) [reset = 0000h]
        15. 7.1.1.15 ADC_SENSE0 Register (address = 18h) [reset = 0000h]
        16. 7.1.1.16 ADC_SENSE1 Register (address = 19h) [reset = 0000h]
        17. 7.1.1.17 ADC_ADC0 Register (address = 1Ah) [reset = 0000h]
        18. 7.1.1.18 ADC_ADC1 Register (address = 1Bh) [reset = 0000h]
        19. 7.1.1.19 ADC_TMP Register (address = 1Ch) [reset = 0000h]
    2. 7.2 General Configuration Register Map
      1. 7.2.1 General Configuration Registers: Page 0
        1. 7.2.1.1  CHIP_ID Register (address = 40h) [reset = 2480h]
        2. 7.2.1.2  CHIP_VER Register (address = 41h) [reset = 0000h]
        3. 7.2.1.3  SDO_EN Register (address = 42h) [reset = 0000h]
        4. 7.2.1.4  GEN_CFG_0 Register (address = 44h) [reset = 0010h]
        5. 7.2.1.5  GEN_CFG_1 Register (address = 45h) [reset = 1101h]
        6. 7.2.1.6  ALARMOUT_SRC_0 Register (address = 48h) [reset = 0000h]
        7. 7.2.1.7  ALARMOUT_SRC_1 Register (address = 49h) [reset = 1833h]
        8. 7.2.1.8  ALARM_STATUS_0_BYP Register (address = 4Ch) [reset = 0000h]
        9. 7.2.1.9  ALARM_STATUS_1_BYP Register (address = 4Dh) [reset = 0000h]
        10. 7.2.1.10 PAON_SRC_0 Register (address = 50h) [reset = 0000h]
        11. 7.2.1.11 PAON_SRC_1 Register (address = 51h) [reset = 1833h]
        12. 7.2.1.12 RESET_FLAGS Register (Offset = 70h) [Reset = 000Fh]
    3. 7.3 ADC Configuration Register Map
      1. 7.3.1 ADC Configuration Registers: Page 1
        1. 7.3.1.1  ADC_GEN_CFG Register (address = 40h) [reset = 3334h]
        2. 7.3.1.2  ADC_CONV_CFG_0 Register (address = 41h) [reset = 0555h]
        3. 7.3.1.3  ADC_CONV_CFG_1 Register (address = 42h) [reset = 0000h]
        4. 7.3.1.4  ADC_BYP Register (address = 44h) [reset = 0000h]
        5. 7.3.1.5  ADC_HYST_0 Register (address = 46h) [reset = 0808h]
        6. 7.3.1.6  ADC_HYST_1 Register (address = 47h) [reset = 0008h]
        7. 7.3.1.7  SENSE0_UP_THRESH Register (address = 50h) [reset = 7FFFh]
        8. 7.3.1.8  SENSE0_LO_THRESH Register (address = 51h) [reset = 8000h]
        9. 7.3.1.9  SENSE1_UP_THRESH Register (address = 52h) [reset = 7FFFh]
        10. 7.3.1.10 SENSE1_LO_THRESH Register (address = 53h) [reset = 8000h]
        11. 7.3.1.11 ADC0_UP_THRESH Register (address = 54h) [reset = 7FFFh]
        12. 7.3.1.12 ADC0_LO_THRESH Register (address = 55h) [reset = 0000h]
        13. 7.3.1.13 ADC1_UP_THRESH Register (address = 56h) [reset = 7FFFh]
        14. 7.3.1.14 ADC1_LO_THRESH Register (address = 57h) [reset = 0000h]
        15. 7.3.1.15 TMP_UP_THRESH Register (address = 58h) [reset = 7FFFh]
    4. 7.4 ADC Custom Channel Sequencer Configuration Register Map
      1. 7.4.1 ADC CCS Registers: Page 3
        1. 7.4.1.1 ADC_CCS_IDS_n Registers (address = 40h to 7Eh) [reset = see ]
        2. 7.4.1.2 ADC_CCS_CFG_0 Register (address = 7Fh) [reset = 0004h]
    5. 7.5 DAC Configuration Register Map
      1. 7.5.1 DAC Configuration Registers: Page 3
        1. 7.5.1.1  DAC_CURRENT Register (address = 40h) [reset = 0000h]
        2. 7.5.1.2  DAC_SYNC_CFG Register (address = 41h) [reset = 0000h]
        3. 7.5.1.3  DAC_CFG Register (address = 42h) [reset = 0000h]
        4. 7.5.1.4  DAC_APD_EN Register (address = 43h) [reset = AAFFh]
        5. 7.5.1.5  DACA_APD_SRC_0 Register (address = 44h) [reset = 0000h]
        6. 7.5.1.6  DACA_APD_SRC_1 Register (address = 45h) [reset = 1833h]
        7. 7.5.1.7  OUTA_APD_SRC_0 Register (address = 46h) [reset = 0000h]
        8. 7.5.1.8  OUTA_APD_SRC_1 Register (address = 47h) [reset = 1833h]
        9. 7.5.1.9  DACB_APD_SRC_0 Register (address = 48h) [reset = 0000h]
        10. 7.5.1.10 DACB_APD_SRC_1 Register (address = 49h) [reset = 1833h]
        11. 7.5.1.11 OUTB_APD_SRC_0 Register (address = 4Ah) [reset = 0000h]
        12. 7.5.1.12 OUTB_APD_SRC_1 Register (address = 4Bh) [reset = 1833h]
        13. 7.5.1.13 DAC_CODE_LIMIT_0 Register (address = 4Ch) [reset = 3F3Fh]
        14. 7.5.1.14 DAC_CODE_LIMIT_1 Register (address = 4Dh) [reset = 3F3Fh]
        15. 7.5.1.15 DAC_CODE_LIMIT_2 Register (address = 4Eh) [reset = 3F3Fh]
        16. 7.5.1.16 DAC_CODE_LIMIT_3 Register (address = 4Fh) [reset = 3F3Fh]
        17. 7.5.1.17 DRVEN0_EN Register (address = 50h) [reset = 0000h]
        18. 7.5.1.18 DRVEN1_EN Register (address = 51h) [reset = 0000h]
        19. 7.5.1.19 FLEXIO_EN Register (address = 52h) [reset = 0000h]
    6. 7.6 DAC Buffer Register Map
      1. 7.6.1 DAC Buffer Data Registers: Page 4
        1. 7.6.1.1 DACA/Bn Buffer Registers (address = 40h to 47h) [reset = 0000h]
    7. 7.7 DAC Active Register Map
      1. 7.7.1 DAC Active Data Registers: Page 4
        1. 7.7.1.1 DACA/Bn Active Register (address = 40h to 47h) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Switching Timing
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ADC Input Conditioning
        2. 8.2.2.2 Quiescent Current and Total Power Consumption
          1. 8.2.2.2.1 Maximum VCC/VSS Supply Current Transients
          2. 8.2.2.2.2 DAC Load Stability
        3. 8.2.2.3 Disabling PA Drain Voltage
        4. 8.2.2.4 PAON External Circuit
      3. 8.2.3 Application Curves
        1. 8.2.3.1 DAC Load Stability
        2. 8.2.3.2 Start-Up Behavior
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Diagram
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 ADC Custom Channel Sequencer Configuration Register Map

Table 7-52 Page 2: ADC Custom Channel Sequencer Configuration Register Map
ADDR (HEX)REGISTER TYPERESET (HEX)BIT DESCRIPTION
1514131211109876543210
40ADC_CCS_IDS_0R/W0201RESERVEDCCS_ID_1[2:0]RESERVEDCCS_ID_0[2:0]
41ADC_CCS_IDS_1R/W0403RESERVEDCCS_ID_3[2:0]RESERVEDCCS_ID_2[2:0]
42ADC_CCS_IDS_2R/W0005RESERVEDCCS_ID_5[2:0]RESERVEDCCS_ID_4[2:0]
43ADC_CCS_IDS_3R/W0000RESERVEDCCS_ID_7[2:0]RESERVEDCCS_ID_6[2:0]
44ADC_CCS_IDS_4R/W0000RESERVEDCCS_ID_9[2:0]RESERVEDCCS_ID_8[2:0]
45ADC_CCS_IDS_5R/W0000RESERVEDCCS_ID_11[2:0]RESERVEDCCS_ID_10[2:0]
46ADC_CCS_IDS_6R/W0000RESERVEDCCS_ID_13[2:0]RESERVEDCCS_ID_12[2:0]
47ADC_CCS_IDS_7R/W0000RESERVEDCCS_ID_15[2:0]RESERVEDCCS_ID_14[2:0]
48ADC_CCS_IDS_8R/W0000RESERVEDCCS_ID_17[2:0]RESERVEDCCS_ID_16[2:0]
49ADC_CCS_IDS_9R/W0000RESERVEDCCS_ID_19[2:0]RESERVEDCCS_ID_18[2:0]
4AADC_CCS_IDS_
10		R/W0000RESERVEDCCS_ID_21[2:0]RESERVEDCCS_ID_20[2:0]
4BADC_CCS_IDS_
11		R/W0000RESERVEDCCS_ID_23[2:0]RESERVEDCCS_ID_22[2:0]
4CADC_CCS_IDS_
12		R/W0000RESERVEDCCS_ID_25[2:0]RESERVEDCCS_ID_24[2:0]
4DADC_CCS_IDS_
13		R/W0000RESERVEDCCS_ID_27[2:0]RESERVEDCCS_ID_26[2:0]
4EADC_CCS_IDS_
14		R/W0000RESERVEDCCS_ID_29[2:0]RESERVEDCCS_ID_28[2:0]
4FADC_CCS_IDS_
15		R/W0000RESERVEDCCS_ID_31[2:0]RESERVEDCCS_ID_30[2:0]
50ADC_CCS_IDS_
16		R/W0000RESERVEDCCS_ID_33[2:0]RESERVEDCCS_ID_32[2:0]
51ADC_CCS_IDS_
17		R/W0000RESERVEDCCS_ID_35[2:0]RESERVEDCCS_ID_34[2:0]
52ADC_CCS_IDS_
18		R/W0000RESERVEDCCS_ID_37[2:0]RESERVEDCCS_ID_36[2:0]
53ADC_CCS_IDS_
19		R/W0000RESERVEDCCS_ID_39[2:0]RESERVEDCCS_ID_38[2:0]
54ADC_CCS_IDS_
20		R/W0000RESERVEDCCS_ID_41[2:0]RESERVEDCCS_ID_40[2:0]
55ADC_CCS_IDS_
21		R/W0000RESERVEDCCS_ID_43[2:0]RESERVEDCCS_ID_42[2:0]
56ADC_CCS_IDS_
22		R/W0000RESERVEDCCS_ID_45[2:0]RESERVEDCCS_ID_44[2:0]
57ADC_CCS_IDS_
23		R/W0000RESERVEDCCS_ID_47[2:0]RESERVEDCCS_ID_46[2:0]
58ADC_CCS_IDS_
24		R/W0000RESERVEDCCS_ID_49[2:0]RESERVEDCCS_ID_48[2:0]
59ADC_CCS_IDS_
25		R/W0000RESERVEDCCS_ID_51[2:0]RESERVEDCCS_ID_50[2:0]
5AADC_CCS_IDS_
26		R/W0000RESERVEDCCS_ID_53[2:0]RESERVEDCCS_ID_52[2:0]
5BADC_CCS_IDS_
27		R/W0000RESERVEDCCS_ID_55[2:0]RESERVEDCCS_ID_54[2:0]
5CADC_CCS_IDS_
28		R/W0000RESERVEDCCS_ID_57[2:0]RESERVEDCCS_ID_56[2:0]
5DADC_CCS_IDS_
29		R/W0000RESERVEDCCS_ID_59[2:0]RESERVEDCCS_ID_58[2:0]
5EADC_CCS_IDS_
30		R/W0000RESERVEDCCS_ID_61[2:0]RESERVEDCCS_ID_60[2:0]
5FADC_CCS_IDS_
31		R/W0000RESERVEDCCS_ID_63[2:0]RESERVEDCCS_ID_62[2:0]
60ADC_CCS_IDS_
32		R/W0000RESERVEDCCS_ID_65[2:0]RESERVEDCCS_ID_64[2:0]
61ADC_CCS_IDS_
33		R/W0000RESERVEDCCS_ID_67[2:0]RESERVEDCCS_ID_66[2:0]
62ADC_CCS_IDS_
34		R/W0000RESERVEDCCS_ID_69[2:0]RESERVEDCCS_ID_68[2:0]
63ADC_CCS_IDS_
35		R/W0000RESERVEDCCS_ID_71[2:0]RESERVEDCCS_ID_70[2:0]
64ADC_CCS_IDS_
36		R/W0000RESERVEDCCS_ID_73[2:0]RESERVEDCCS_ID_72[2:0]
65ADC_CCS_IDS_
37		R/W0000RESERVEDCCS_ID_75[2:0]RESERVEDCCS_ID_74[2:0]
66ADC_CCS_IDS_
38		R/W0000RESERVEDCCS_ID_77[2:0]RESERVEDCCS_ID_76[2:0]
67ADC_CCS_IDS_
39		R/W0000RESERVEDCCS_ID_79[2:0]RESERVEDCCS_ID_78[2:0]
68ADC_CCS_IDS_
40		R/W0000RESERVEDCCS_ID_81[2:0]RESERVEDCCS_ID_80[2:0]
69ADC_CCS_IDS_
41		R/W0000RESERVEDCCS_ID_83[2:0]RESERVEDCCS_ID_82[2:0]
6AADC_CCS_IDS_
42		R/W0000RESERVEDCCS_ID_85[2:0]RESERVEDCCS_ID_84[2:0]
6BADC_CCS_IDS_
43		R/W0000RESERVEDCCS_ID_87[2:0]RESERVEDCCS_ID_86[2:0]
6CADC_CCS_IDS_
44		R/W0000RESERVEDCCS_ID_89[2:0]RESERVEDCCS_ID_88[2:0]
6DADC_CCS_IDS_
45		R/W0000RESERVEDCCS_ID_91[2:0]RESERVEDCCS_ID_90[2:0]
6EADC_CCS_IDS_
46		R/W0000RESERVEDCCS_ID_93[2:0]RESERVEDCCS_ID_92[2:0]
6FADC_CCS_IDS_
47		R/W0000RESERVEDCCS_ID_95[2:0]RESERVEDCCS_ID_94[2:0]
70ADC_CCS_IDS_
48		R/W0000RESERVEDCCS_ID_97[2:0]RESERVEDCCS_ID_96[2:0]
71ADC_CCS_IDS_
49		R/W0000RESERVEDCCS_ID_99[2:0]RESERVEDCCS_ID_98[2:0]
72ADC_CCS_IDS_
50		R/W0000RESERVEDCCS_ID_101[2:0]RESERVEDCCS_ID_100[2:0]
73ADC_CCS_IDS_
51		R/W0000RESERVEDCCS_ID_103[2:0]RESERVEDCCS_ID_102[2:0]
74ADC_CCS_IDS_
52		R/W0000RESERVEDCCS_ID_105[2:0]RESERVEDCCS_ID_104[2:0]
75ADC_CCS_IDS_
53		R/W0000RESERVEDCCS_ID_107[2:0]RESERVEDCCS_ID_106[2:0]
76ADC_CCS_IDS_
54		R/W0000RESERVEDCCS_ID_109[2:0]RESERVEDCCS_ID_108[2:0]
77ADC_CCS_IDS_
55		R/W0000RESERVEDCCS_ID_111[2:0]RESERVEDCCS_ID_110[2:0]
78ADC_CCS_IDS_
56		R/W0000RESERVEDCCS_ID_113[2:0]RESERVEDCCS_ID_112[2:0]
79ADC_CCS_IDS_
57		R/W0000RESERVEDCCS_ID_115[2:0]RESERVEDCCS_ID_114[2:0]
7AADC_CCS_IDS_
58		R/W0000RESERVEDCCS_ID_117[2:0]RESERVEDCCS_ID_116[2:0]
7BADC_CCS_IDS_
59		R/W0000RESERVEDCCS_ID_119[2:0]RESERVEDCCS_ID_118[2:0]
7CADC_CCS_IDS_
60		R/W0000RESERVEDCCS_ID_121[2:0]RESERVEDCCS_ID_120[2:0]
7DADC_CCS_IDS_
61		R/W0000RESERVEDCCS_ID_123[2:0]RESERVEDCCS_ID_122[2:0]
7EADC_CCS_IDS_
62		R/W0000RESERVEDCCS_ID_125[2:0]RESERVEDCCS_ID_124[2:0]
7FADC_CCS_CFG_0R/W0004RESERVEDCCS_START_INDEX[6:0]RESERVEDCCS_STOP_INDEX[6:0]