SLASF96 April   2024 AFE20408

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Register Structure
          1. 6.3.1.2.1 DAC Synchronous Operation
        3. 6.3.1.3 DAC Buffer Amplifier
          1. 6.3.1.3.1 Autorange Detection
          2. 6.3.1.3.2 Power-Supply Monitoring
      2. 6.3.2 Analog-to-Digital Converter (ADC)
        1. 6.3.2.1 Versatile High-Voltage Measurement Capability
        2. 6.3.2.2 High-Precision Delta-Sigma ADC
          1. 6.3.2.2.1 ADC Custom Channel Sequencer
        3. 6.3.2.3 Low Latency Digital Filter
        4. 6.3.2.4 Flexible Conversion Times and Averaging
        5. 6.3.2.5 Integrated Precision Oscillator
      3. 6.3.3 Output Switch Overview
      4. 6.3.4 Drain Switch Control
      5. 6.3.5 FLEXIO Pin
      6. 6.3.6 Internal Temperature Sensor
      7. 6.3.7 Programmable Out-of-Range Alarms
        1. 6.3.7.1 Temperature Sensor Alarm Function
        2. 6.3.7.2 Supply Out-of-Range Alarm Function
        3. 6.3.7.3 ADC Alarm Function
    4. 6.4 Device Functional Modes
      1. 6.4.1 All-Positive DAC Range Mode
      2. 6.4.2 All-Negative DAC Range Mode
      3. 6.4.3 Mixed DAC Range Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 I2C Bus Overview
        2. 6.5.1.2 I2C Bus Definitions
        3. 6.5.1.3 I2C Target Address Selection
        4. 6.5.1.4 I2C Read and Write Operations
        5. 6.5.1.5 I2C Timeout Function
        6. 6.5.1.6 I2C General-Call Reset
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Bus Overview
  8. 7 Register Maps
    1. 7.1 Global Register Map
      1. 7.1.1 Global Registers: Global Page
        1. 7.1.1.1  NOP_RESET Register (address = 00h) [reset = 0000h]
        2. 7.1.1.2  PAGE Register (address = 01h) [reset = 0000h]
        3. 7.1.1.3  GEN_STATUS Register (address = 03h) [reset = 4000h]
        4. 7.1.1.4  ALARM_STATUS_0 Register (address = 04h) [reset = 0000h]
        5. 7.1.1.5  ALARM_STATUS_1 Register (address = 05h) [reset = 0000h]
        6. 7.1.1.6  PWR_STATUS_0 Register (address = 06h) [reset = 0001h]
        7. 7.1.1.7  PWR_STATUS_1 Register (address = 07h) [reset = 0000h]
        8. 7.1.1.8  PWR_EN Register (address = 08h) [reset = 0200h]
        9. 7.1.1.9  TRIGGER Register (address = 10h) [reset = 0000h]
        10. 7.1.1.10 GPIO_DATA Register (address = 11h) [reset = 0001h]
        11. 7.1.1.11 DRVEN_SW_EN Register (address = 12h) [reset = 00FFh]
        12. 7.1.1.12 DRVEN Register (address = 13h) [reset = 0000h]
        13. 7.1.1.13 DAC_BCAST Register (address = 14h) [reset = 0000h]
        14. 7.1.1.14 GLOBAL_CFG Register (address = 17h) [reset = 0000h]
        15. 7.1.1.15 ADC_SENSE0 Register (address = 18h) [reset = 0000h]
        16. 7.1.1.16 ADC_SENSE1 Register (address = 19h) [reset = 0000h]
        17. 7.1.1.17 ADC_ADC0 Register (address = 1Ah) [reset = 0000h]
        18. 7.1.1.18 ADC_ADC1 Register (address = 1Bh) [reset = 0000h]
        19. 7.1.1.19 ADC_TMP Register (address = 1Ch) [reset = 0000h]
    2. 7.2 General Configuration Register Map
      1. 7.2.1 General Configuration Registers: Page 0
        1. 7.2.1.1  CHIP_ID Register (address = 40h) [reset = 2480h]
        2. 7.2.1.2  CHIP_VER Register (address = 41h) [reset = 0000h]
        3. 7.2.1.3  SDO_EN Register (address = 42h) [reset = 0000h]
        4. 7.2.1.4  GEN_CFG_0 Register (address = 44h) [reset = 0010h]
        5. 7.2.1.5  GEN_CFG_1 Register (address = 45h) [reset = 1101h]
        6. 7.2.1.6  ALARMOUT_SRC_0 Register (address = 48h) [reset = 0000h]
        7. 7.2.1.7  ALARMOUT_SRC_1 Register (address = 49h) [reset = 1833h]
        8. 7.2.1.8  ALARM_STATUS_0_BYP Register (address = 4Ch) [reset = 0000h]
        9. 7.2.1.9  ALARM_STATUS_1_BYP Register (address = 4Dh) [reset = 0000h]
        10. 7.2.1.10 PAON_SRC_0 Register (address = 50h) [reset = 0000h]
        11. 7.2.1.11 PAON_SRC_1 Register (address = 51h) [reset = 1833h]
        12. 7.2.1.12 RESET_FLAGS Register (Offset = 70h) [Reset = 000Fh]
    3. 7.3 ADC Configuration Register Map
      1. 7.3.1 ADC Configuration Registers: Page 1
        1. 7.3.1.1  ADC_GEN_CFG Register (address = 40h) [reset = 3334h]
        2. 7.3.1.2  ADC_CONV_CFG_0 Register (address = 41h) [reset = 0555h]
        3. 7.3.1.3  ADC_CONV_CFG_1 Register (address = 42h) [reset = 0000h]
        4. 7.3.1.4  ADC_BYP Register (address = 44h) [reset = 0000h]
        5. 7.3.1.5  ADC_HYST_0 Register (address = 46h) [reset = 0808h]
        6. 7.3.1.6  ADC_HYST_1 Register (address = 47h) [reset = 0008h]
        7. 7.3.1.7  SENSE0_UP_THRESH Register (address = 50h) [reset = 7FFFh]
        8. 7.3.1.8  SENSE0_LO_THRESH Register (address = 51h) [reset = 8000h]
        9. 7.3.1.9  SENSE1_UP_THRESH Register (address = 52h) [reset = 7FFFh]
        10. 7.3.1.10 SENSE1_LO_THRESH Register (address = 53h) [reset = 8000h]
        11. 7.3.1.11 ADC0_UP_THRESH Register (address = 54h) [reset = 7FFFh]
        12. 7.3.1.12 ADC0_LO_THRESH Register (address = 55h) [reset = 0000h]
        13. 7.3.1.13 ADC1_UP_THRESH Register (address = 56h) [reset = 7FFFh]
        14. 7.3.1.14 ADC1_LO_THRESH Register (address = 57h) [reset = 0000h]
        15. 7.3.1.15 TMP_UP_THRESH Register (address = 58h) [reset = 7FFFh]
    4. 7.4 ADC Custom Channel Sequencer Configuration Register Map
      1. 7.4.1 ADC CCS Registers: Page 3
        1. 7.4.1.1 ADC_CCS_IDS_n Registers (address = 40h to 7Eh) [reset = see ]
        2. 7.4.1.2 ADC_CCS_CFG_0 Register (address = 7Fh) [reset = 0004h]
    5. 7.5 DAC Configuration Register Map
      1. 7.5.1 DAC Configuration Registers: Page 3
        1. 7.5.1.1  DAC_CURRENT Register (address = 40h) [reset = 0000h]
        2. 7.5.1.2  DAC_SYNC_CFG Register (address = 41h) [reset = 0000h]
        3. 7.5.1.3  DAC_CFG Register (address = 42h) [reset = 0000h]
        4. 7.5.1.4  DAC_APD_EN Register (address = 43h) [reset = AAFFh]
        5. 7.5.1.5  DACA_APD_SRC_0 Register (address = 44h) [reset = 0000h]
        6. 7.5.1.6  DACA_APD_SRC_1 Register (address = 45h) [reset = 1833h]
        7. 7.5.1.7  OUTA_APD_SRC_0 Register (address = 46h) [reset = 0000h]
        8. 7.5.1.8  OUTA_APD_SRC_1 Register (address = 47h) [reset = 1833h]
        9. 7.5.1.9  DACB_APD_SRC_0 Register (address = 48h) [reset = 0000h]
        10. 7.5.1.10 DACB_APD_SRC_1 Register (address = 49h) [reset = 1833h]
        11. 7.5.1.11 OUTB_APD_SRC_0 Register (address = 4Ah) [reset = 0000h]
        12. 7.5.1.12 OUTB_APD_SRC_1 Register (address = 4Bh) [reset = 1833h]
        13. 7.5.1.13 DAC_CODE_LIMIT_0 Register (address = 4Ch) [reset = 3F3Fh]
        14. 7.5.1.14 DAC_CODE_LIMIT_1 Register (address = 4Dh) [reset = 3F3Fh]
        15. 7.5.1.15 DAC_CODE_LIMIT_2 Register (address = 4Eh) [reset = 3F3Fh]
        16. 7.5.1.16 DAC_CODE_LIMIT_3 Register (address = 4Fh) [reset = 3F3Fh]
        17. 7.5.1.17 DRVEN0_EN Register (address = 50h) [reset = 0000h]
        18. 7.5.1.18 DRVEN1_EN Register (address = 51h) [reset = 0000h]
        19. 7.5.1.19 FLEXIO_EN Register (address = 52h) [reset = 0000h]
    6. 7.6 DAC Buffer Register Map
      1. 7.6.1 DAC Buffer Data Registers: Page 4
        1. 7.6.1.1 DACA/Bn Buffer Registers (address = 40h to 47h) [reset = 0000h]
    7. 7.7 DAC Active Register Map
      1. 7.7.1 DAC Active Data Registers: Page 4
        1. 7.7.1.1 DACA/Bn Active Register (address = 40h to 47h) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Switching Timing
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ADC Input Conditioning
        2. 8.2.2.2 Quiescent Current and Total Power Consumption
          1. 8.2.2.2.1 Maximum VCC/VSS Supply Current Transients
          2. 8.2.2.2.2 DAC Load Stability
        3. 8.2.2.3 Disabling PA Drain Voltage
        4. 8.2.2.4 PAON External Circuit
      3. 8.2.3 Application Curves
        1. 8.2.3.1 DAC Load Stability
        2. 8.2.3.2 Start-Up Behavior
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Diagram
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

all minimum and maximum values at TJ = –40℃ to +125℃; all typical values at TJ = 25℃, VDD = 3.0V to 5.5V, VIO = 1.65V to 3.6V, positive output range: VCC[A,B] = 3.0V to 11.0V, VSS[A,B] = GND, negative output range: VSS[A,B] = –11.0V to –3.0V, VCC[A,B] = GND, and DAC outputs unloaded (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC CHARACTERISTICS(1)
Resolution 13 Bits
Full scale output voltage range Set at start-up through autorange detection –10 0 V
Set at start-up through autorange detection 0 10
DNL Differential nonlinearity Specified 13-bit monotonic –1 1 LSB
INL Integral nonlinearity –4 4 LSB
TUE Total unadjusted error –0.6 ±0.1 0.6 %FSR
TUE Total unadjusted error (4) Operating in extended temperature range (TJ = –55℃ to +150℃) –2 ±0.1 2 %FSR
Total adjusted error After one point calibration at 25℃,
DAC output at 1/4 of full-scale range		 –0.1 ±0.01 0.1 %FSR
Offset error Positive output range –40 ±5 40 mV
Negative output range –40 ±5 40
Offset error temperature drift ±5 ppm/°C
Gain error –0.5 ±0.01 0.5 %FSR
Gain error temperature drift ±20 ppm/°C
Zero-scale error Positive output range: all zeros code 0 5 35 mV
Negative output range: all ones code –35 –5 0
Zero-scale error temperature drift ±5 ppm/°C
Full-scale error Positive output range: all ones code –0.7 ±0.05 0.7 %FSR
Negative output range: all zeros code –0.7 ±0.05 0.7
Full-scale error temperature drift ±20 ppm/°C
Short circuit current(2) Start-up current mode 15 mA
Low-current mode 30
Normal-current mode 90
High-current mode 120
Capacitive load stability(3) 0 15 µF
DC output impedance Midscale code 3 Ω
Output voltage settling time CL = 15µF, 2.5V step to within 2.5mV 400 µs
Output noise 0.1Hz to 10Hz, midscale code 70 µVpp
Output noise density 1kHz, midscale code 700 nV/√Hz
PSRRAC Power supply ac rejection ratio Midscale code, frequency = 60Hz,
amplitude = 200mVpp superimposed on VCC[A,B] or VSS[A,B]		   66   dB
Midscale code, frequency = 60Hz,
amplitude = 200mVpp superimposed on VDD		 70
PSRRDC Power supply dc rejection ratio Midscale code, VDD = 5V ±10%,
VCC[A,B] = 10V ±10%, VSS = –10V ±10%		 500 µV/V
Channel-to-channel dc crosstalk Measured DAC output at midscale, all other DAC outputs at full-scale 150 µV
OUTPUT SWITCH DC CHARACTERISTICS
RDAC Resistance between DAC buffers and output pins 1.5V headroom from supply 3 5 Ω
RVSS Resistance between VSS[A,B] and output pins 4 7 Ω
SUPPLY MONITOR CHARACTERISTICS
VSSTH VSS threshold detector Low VSS supply failure detect –2.2 –1.7 V
Mid VSS supply failure detect –3.7 –3.2
High VSS supply failure detect –6.7 –6.2
VCCTH VCC threshold detector VCC supply failure detect 1.7 2.2 V
HIGH-VOLTAGE SENSE CHARACTERISTICS
VIN Analog input range VSS[A,B] = 0V 0 85 V
Offset voltage VIN = 20mV ±1.5 ±13 mV
Offset voltage(4) VIN = 20mV, operation in extended temperature range (TJ = –55°C to +150°C) ±5 ±40 mV
Offset voltage drift ±20 µV/°C
Gain error ±0.1 ±1.0 %
Gain error(4) Operation in extended temperature range (TJ = –55°C to +150°C) ±0.3 ±3.0 %
Gain error drift ±20 ppm/°C
Input impedance Active mode 1 MΩ
Pin leakage current Shutdown mode, VIN = 85V 1 μA
Resolution 3.125 mV
CURRENT SENSE CHARACTERISTICS
VCM Common-mode input range VSS[A,B] = 0V –0.3 85 V
VDIFF Shunt voltage input range SHUNT_RANGE = 0 –163.84 163.84 mV
SHUNT_RANGE = 1 –40.96 40.96
Shunt offset voltage VCM = 48V, TCT > 280μs ±10 ±100 μV
VCM = 0V, TCT > 280μs ±10 ±100
Shunt offset voltage drift ±100 nV/°C
Shunt voltage gain error VCM = 24V ±0.1 ±1.0 %
Shunt voltage gain error VCM = 24V, operation in extended temperature range (TJ = –55°C to 150°C) ±0.3 ±3.0 %
Shunt voltage gain error drift ±50 ppm/°C
Common-mode rejection ratio 120 dB
Input bias current SENSE+ and SENSE– inputs, VCM = 85V 1 µA
Input differential impedance Active mode, VDIFF < 164mV 92 kΩ
Resolution Shunt voltage, SHUNT_RANGE = 0 5 µV
Shunt voltage, SHUNT_RANGE = 1 1.25
TEMPERATURE SENSE CHARACTERISTICS
Accuracy TJ = –40°C to +125°C –2.5 ±0.25 2.5 °C
Resolution LSB size 7.8125 m°C
DIGITAL INPUT CHARACTERISTICS
VIH High-level input voltage 0.7 × VIO V
VIL Low-level input voltage 0.3 × VIO V
Input current 2 µA
Input pin capacitance 8 pF
DIGITAL OUTPUT CHARACTERISTICS
VOH High-level output voltage ISOURCE = 0.2mA VIO – 0.4 V
VOL Low-level output voltage ISINK = –0.2mA 0.4 V
Output pin capacitance 8 pF
VOL Open-drain low-level output voltage ISINK = 2mA 0.4 V
POWER CONSUMPTION CHARACTERISTICS
IVDD VDD supply current(4) Positive output range 5 mA
Negative output range 6
Positive output range, operating in extended temperature range (TJ = –55°C to +150°C) 10
Negative output range, operating in extended temperature range (TJ = –55°C to +150°C) 12
IVCC VCC supply current(4) Positive output range, midscale output 6 mA
Positive output range, midscale output, operating in extended temperature range (TJ = –55°C to +150°C) 12
IVSS VSS supply current(4) Negative output range, 1/4 of full-scale output 7 mA
Negative output range, 1/4 of full-scale output, operating in extended temperature range (TJ = –55°C to +150°C) 15
IVIO VIO supply current(4) 5 µA
Operating in extended temperature range (TJ = –55°C to +150°C) 10
(1) End point fit between codes 64 to 8128 for negative output range and 64 to 8128 for positive output range.
(2) Overload condition protection. Junction temperature can be exceeded during current limit. Operation greater than the specified maximum junction temperature can impair device reliability.
(3) No continuous oscillations when DAC transitions between codes.
(4) All values provided for extended temperature range (–55°C to +150°C) are specified by characterization