SLASFB2 November 2023 AFE432A3W , AFE532A3W
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADC-EN | ADC-AVG | RESERVED | TRIG-ADC | |||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-000h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R/W | 0h | Always write 0h. |
13 | ADC-EN | R/W | 0h | 0: ADC is disabled. 1: ADC is enabled on channel 1. Comparator mode must be enabled on channel 1 before setting this bit. Connect FB1 to VDD using a pullup resistor. |
12-11 | ADC-AVG | R/W | 0h | 00: 4
samples are averaged. 01: 8 samples are averaged. 10: 16 samples are averaged. 11: 32 samples are averaged. |
10-1 | RESERVED | R/W | 000h | Always write 0b01 1110 0000 (1E0h). |
0 | TRIG-ADC | W | 0h | Write 1 to start ADC conversion. This bit is auto-resetting. Check the ADC-DRDY bit in the GENERAL-STATUS or the ADC-DATA register for ADC data validity. |