SLASFB2 November   2023 AFE432A3W , AFE532A3W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Voltage Output
    6. 5.6  Electrical Characteristics: Current Output
    7. 5.7  Electrical Characteristics: Comparator Mode
    8. 5.8  Electrical Characteristics: ADC Input
    9. 5.9  Electrical Characteristics: General
    10. 5.10 Timing Requirements: I2C Standard Mode
    11. 5.11 Timing Requirements: I2C Fast Mode
    12. 5.12 Timing Requirements: I2C Fast-Mode Plus
    13. 5.13 Timing Requirements: SPI Write Operation
    14. 5.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    15. 5.15 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    16. 5.16 Timing Requirements: GPIO
    17. 5.17 Timing Diagrams
    18. 5.18 Typical Characteristics: Voltage Output
    19. 5.19 Typical Characteristics: Current Output
    20. 5.20 Typical Characteristics: Comparator
    21. 5.21 Typical Characteristics: ADC
    22. 5.22 Typical Characteristics: General
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Smart Analog Front End (AFE) Architecture
      2. 6.3.2 Digital Input/Output
      3. 6.3.3 Nonvolatile Memory (NVM)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Voltage-Output Mode
        1. 6.4.1.1 Voltage Reference and DAC Transfer Function
          1. 6.4.1.1.1 Internal Reference
          2. 6.4.1.1.2 Power-Supply as Reference
      2. 6.4.2 Current-Output Mode
      3. 6.4.3 Comparator Mode
        1. 6.4.3.1 Programmable Hysteresis Comparator
        2. 6.4.3.2 Programmable Window Comparator
      4. 6.4.4 Analog-to-Digital Converter (ADC) Mode
      5. 6.4.5 Fault-Dump Mode
      6. 6.4.6 Application-Specific Modes
        1. 6.4.6.1 Voltage Margining and Scaling
          1. 6.4.6.1.1 High-Impedance Output and PROTECT Input
          2. 6.4.6.1.2 Programmable Slew-Rate Control
        2. 6.4.6.2 Function Generation
          1. 6.4.6.2.1 Triangular Waveform Generation
          2. 6.4.6.2.2 Sawtooth Waveform Generation
          3. 6.4.6.2.3 Sine Waveform Generation
      7. 6.4.7 Device Reset and Fault Management
        1. 6.4.7.1 Power-On Reset (POR)
        2. 6.4.7.2 External Reset
        3. 6.4.7.3 Register-Map Lock
        4. 6.4.7.4 NVM Cyclic Redundancy Check (CRC)
          1. 6.4.7.4.1 NVM-CRC-FAIL-USER Bit
          2. 6.4.7.4.2 NVM-CRC-FAIL-INT Bit
      8. 6.4.8 General-Purpose Input/Output (GPIO) Modes
    5. 6.5 Programming
      1. 6.5.1 SPI Programming Mode
      2. 6.5.2 I2C Programming Mode
        1. 6.5.2.1 F/S Mode Protocol
        2. 6.5.2.2 I2C Update Sequence
          1. 6.5.2.2.1 Address Byte
          2. 6.5.2.2.2 Command Byte
        3. 6.5.2.3 I2C Read Sequence
  8. 7 Register Map
    1. 7.1  NOP Register (address = 00h) [reset = 0000h]
    2. 7.2  DAC-0-MARGIN-HIGH Register (address = 0Dh) [reset = 0000h]
    3. 7.3  DAC-1-MARGIN-HIGH Register (address = 13h) [reset = 0000h]
    4. 7.4  DAC-2-MARGIN-HIGH Register (address = 01h) [reset = 0000h]
    5. 7.5  DAC-0-MARGIN-LOW Register (address = 0Eh) [reset = 0000h]
    6. 7.6  DAC-1-MARGIN-LOW Register (address = 14h) [reset = 0000h]
    7. 7.7  DAC-2-MARGIN-LOW Register (address = 02h) [reset = 0000h]
    8. 7.8  DAC-0-GAIN-CONFIG Register (address = 0Fh) [reset = 0000h]
    9. 7.9  DAC-1-GAIN-CMP-CONFIG Register (address = 15h) [reset = 0000h]
    10. 7.10 DAC-2-GAIN-CONFIG Register (address = 03h) [reset = 0000h]
    11. 7.11 DAC-1-CMP-MODE-CONFIG Register (address = 17h) [reset = 0000h]
    12. 7.12 DAC-0-FUNC-CONFIG Register (address = 12h) [reset = 0000h]
    13. 7.13 DAC-1-FUNC-CONFIG Register (address = 18h) [reset = 0000h]
    14. 7.14 DAC-2-FUNC-CONFIG Register (address = 06h) [reset = 0000h]
    15. 7.15 DAC-0-DATA Register (address = 1Bh) [reset = 0000h]
    16. 7.16 DAC-1-DATA Register (address = 1Ch) [reset = 0000h]
    17. 7.17 DAC-2-DATA Register (address = 19h) [reset = 0000h]
    18. 7.18 ADC-CONFIG-TRIG Register (address = 1Dh) [reset = 0000h]
    19. 7.19 ADC-DATA Register (address = 1Eh) [reset = 0001h]
    20. 7.20 COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
    21. 7.21 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
    22. 7.22 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
    23. 7.23 GENERAL-STATUS Register (address = 22h) [reset = 20h, DEVICE-ID, VERSION-ID]
    24. 7.24 CMP-STATUS Register (address = 23h) [reset = 000Ch]
    25. 7.25 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
    26. 7.26 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
    27. 7.27 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
    28. 7.28 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
    29. 7.29 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
    30. 7.30 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBH|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Overview

The 10-bit AFE532A3W and the 8-bit AFE432A3W (AFEx32A3W) are a three-channel buffered voltage-output, current-output, and ADC-input smart AFEs. The DAC channel 2 acts as a current source. The DAC channel 1 is configurable as voltage output, comparator input, or ADC input. The DAC outputs are changed to Hi-Z when VDD is off; a feature useful in voltage-margining applications. This smart AFE contains NVM, an internal reference, automatically detectable I2C or SPI, force-sense output, and a general-purpose input. This device supports Hi-Z power-down modes by default, which can be configured to 10 kΩ-GND or 100 kΩ-GND for voltage-output channels using the NVM. The AFEx32A3W has a power-on-reset (POR) circuit that makes sure all the registers start with default or user-programmed settings using NVM. The AFEx32A3W operates with either an internal reference or with a power supply as the reference.

The AFEx32A3W supports I2C standard mode (100kbps), fast mode (400kbps), and fast-mode plus (1Mbps). The I2C interface can be configured with four target addresses using the A0 pin. SPI mode supports a 3-wire interface by default with up to 50-MHz SCLK input. The GPIO/SDO input can be configured as SDO in the NVM for SPI read capability. The GPIO/SDO input can alternatively be configurable as LDAC, PD, STATUS, FAULT-DUMP, RESET, and PROTECT functions.

The AFEx32A3W also includes digital slew rate control, and supports standard waveform generation such as sine, cosine, triangular, and sawtooth waveforms. This device can generate pulse-width modulation (PWM) output with the combination of the triangular or sawtooth waveform and the FB1 pin. The force-sense outputs of channel 1 can be used as a programmable comparator. The comparator mode allows programmable hysteresis, latching comparator, window comparator, and fault-dump to the NVM. These features enable the AFEx32A3W to go beyond the limitations of a conventional DAC that depends on a processor to function. As a result of processor-less operation and the smart feature set, the AFEx32A3W is called a smart AFE.