SBAS650C May   2014  – April 2021 AFE4403

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Family Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Requirements: Supply Ramp and Power-Down
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Channel
        1. 8.3.1.1 Receiver Front-End
        2. 8.3.1.2 Ambient Cancellation Scheme and Second Stage Gain Block
        3. 8.3.1.3 Receiver Control Signals
        4. 8.3.1.4 Receiver Timing
      2. 8.3.2 Clocking and Timing Signal Generation
      3. 8.3.3 Timer Module
        1. 8.3.3.1 Using the Timer Module
      4. 8.3.4 Receiver Subsystem Power Path
      5. 8.3.5 Transmit Section
        1. 8.3.5.1 Third LED Support
        2. 8.3.5.2 Transmitter Power Path
        3. 8.3.5.3 LED Power Reduction During Periods of Inactivity
        4. 8.3.5.4 LED Configurations
    4. 8.4 Device Functional Modes
      1. 8.4.1 ADC Operation and Averaging Module
        1. 8.4.1.1 Operation Without Averaging
        2. 8.4.1.2 Operation With Averaging
        3. 8.4.1.3 Dynamic Power-Down Mode
      2. 8.4.2 Diagnostics
        1. 8.4.2.1 Photodiode-Side Fault Detection
        2. 8.4.2.2 Transmitter-Side Fault Detection
        3. 8.4.2.3 Diagnostics Module
    5. 8.5 Programming
      1. 8.5.1 Serial Programming Interface
      2. 8.5.2 Reading and Writing Data
        1. 8.5.2.1 Writing Data
        2. 8.5.2.2 Reading Data
        3. 8.5.2.3 Multiple Data Reads and Writes
        4. 8.5.2.4 Register Initialization
        5. 8.5.2.5 AFE SPI Interface Design Considerations
    6. 8.6 Register Maps
      1. 8.6.1 AFE Register Map
      2. 8.6.2 AFE Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Consumption Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1.3 Dynamic Power-Down Mode

When operated at low PRF, a dynamic power-down mode can be optionally enabled to shut off blocks during a portion of each period. This operation is illustrated in Figure 8-30. The dynamic power-down signal (called PDN_CYCLE) can be internally generated using the timing controller. PDN_CYCLE can be used to shut off power to internal blocks during the unused section within each pulse repetition period.

GUID-541E63C3-CBEF-466C-B4E4-E0B7D2499EA3-low.gif Figure 8-30 Dynamic Power-Down Mode Timing

t1 and t2 denote the timing margin between the active portion of the period and the dynamic power-down signal. TI recommends setting t1 > 50 µs and t2 > 200 µs in order to ensure sufficient time for the shutdown blocks to recover from power-down. By choosing the blocks that are shut down during dynamic power-down, a power savings of anywhere between 35% to 70% power can be achieved when the PDN_CYCLE phase is active.

The sequence of the convert phases within a pulse repetition period should be as follows: LED2 (Red) → Ambient 2 → LED1 (IR) → Ambient 1. The sample phases must precede the corresponding convert phase. Also note that the ADC_RDY signal coincides with the first ADC Reset signal. The time window between the ADC_RDY (first ADC Reset) and the second ADC Reset represents the window where the contents of all the 6 registers correspond to the samples of the four conversion phases from the previous pulse repetition period.

The MCU could either read all of these registers during this time window, or could read each register separately in the time window where its contents are stable.

The DYNAMIC1, DYNAMIC2, DYNAMIC3, and DYNAMIC4 bits determine which blocks are powered down during the dynamic power-down state (when PDN_CYCLE is high). For maximum power saving, all four bits can be set to 1. TI recommends setting t1 to greater than 100 µs and t2 to greater than 200 µs to ensure that the blocks recover from power-down in time for the next cycle.

The bit corresponding to the TIA power-down (DYNAMIC3) needs a bit more consideration. When the TIA is powered down, the TIA no longer maintains the bias across the photodiode output. This loss of bias can cause the photodiode output voltage to drift from the normal value. The recovery time constant associated with the photodiode returning to a proper bias condition (when the TIA is powered back on) is approximately equal to 2 × CPD × RF, where CPD is the effective differential capacitance of the photodiode and RF is the TIA gain setting. This consideration might result in a different choice for the value of t2.