SBAS650C May   2014  – April 2021 AFE4403

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Family Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Requirements: Supply Ramp and Power-Down
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Channel
        1. 8.3.1.1 Receiver Front-End
        2. 8.3.1.2 Ambient Cancellation Scheme and Second Stage Gain Block
        3. 8.3.1.3 Receiver Control Signals
        4. 8.3.1.4 Receiver Timing
      2. 8.3.2 Clocking and Timing Signal Generation
      3. 8.3.3 Timer Module
        1. 8.3.3.1 Using the Timer Module
      4. 8.3.4 Receiver Subsystem Power Path
      5. 8.3.5 Transmit Section
        1. 8.3.5.1 Third LED Support
        2. 8.3.5.2 Transmitter Power Path
        3. 8.3.5.3 LED Power Reduction During Periods of Inactivity
        4. 8.3.5.4 LED Configurations
    4. 8.4 Device Functional Modes
      1. 8.4.1 ADC Operation and Averaging Module
        1. 8.4.1.1 Operation Without Averaging
        2. 8.4.1.2 Operation With Averaging
        3. 8.4.1.3 Dynamic Power-Down Mode
      2. 8.4.2 Diagnostics
        1. 8.4.2.1 Photodiode-Side Fault Detection
        2. 8.4.2.2 Transmitter-Side Fault Detection
        3. 8.4.2.3 Diagnostics Module
    5. 8.5 Programming
      1. 8.5.1 Serial Programming Interface
      2. 8.5.2 Reading and Writing Data
        1. 8.5.2.1 Writing Data
        2. 8.5.2.2 Reading Data
        3. 8.5.2.3 Multiple Data Reads and Writes
        4. 8.5.2.4 Register Initialization
        5. 8.5.2.5 AFE SPI Interface Design Considerations
    6. 8.6 Register Maps
      1. 8.6.1 AFE Register Map
      2. 8.6.2 AFE Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Consumption Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1.1 Receiver Front-End

The receiver consists of a differential current-to-voltage (I-V) transimpedance amplifier (TIA) that converts the input photodiode current into an appropriate voltage, as shown in Figure 8-1. The feedback resistor of the amplifier (RF) is programmable to support a wide range of photodiode currents. Available RF values include:
1 MΩ, 500 kΩ, 250 kΩ, 100 kΩ, 50 kΩ, 25 kΩ, and 10 kΩ.

The device is ideally suited as a front-end for a PPG (photoplethysmography) application. In such an application, the light from the LED is reflected (or transmitted) from (or through) the various components inside the body (such as blood, tissue, and so forth) and are received by the photodiode. The signal received by the photodiode has three distinct components:

  1. A pulsatile or ac component that arises as a result of the changes in blood volume through the arteries.
  2. A constant dc signal that is reflected or transmitted from the time invariant components in the path of light. This constant dc component is referred to as the pleth signal.
  3. Ambient light entering the photodiode.
The ac component is usually a small fraction of the pleth component, with the ratio referred to as the perfusion index (PI). Thus, the allowed signal chain gain is usually determined by the amplitude of the dc component.

GUID-47A8902C-8E73-4770-858E-686839A5FF92-low.gifFigure 8-1 Receiver Front-End

The RF amplifier and the feedback capacitor (CF) form a low-pass filter for the input signal current. Always ensure that the low-pass filter RC time constant has sufficiently high bandwidth (as shown by Equation 1) because the input current consists of pulses. For this reason, the feedback capacitor is also programmable. Available CF values include: 5 pF, 10 pF, 25 pF, 50 pF, 100 pF, and 250 pF. Any combination of these capacitors can also be used.

Equation 1. GUID-1505E3E5-5BBD-4574-8157-B14C1EC3AC03-low.gif

The output voltage of the I-V amplifier includes the pleth component (the desired signal) and a component resulting from the ambient light leakage. The I-V amplifier is followed by the second stage, which consists of a current digital-to-analog converter (DAC) that sources the cancellation current and an amplifier that gains up the pleth component alone. The amplifier has five programmable gain settings: 0 dB, 3.5 dB, 6 dB, 9.5 dB, and 12 dB. The gained-up pleth signal is then low-pass filtered (500-Hz bandwidth) and buffered before driving a 22-bit ADC. The current DAC has a cancellation current range of 10 µA with 10 steps (1 µA each). The DAC value can be digitally specified with the SPI interface. Using ambient compensation with the ambient DAC allows the dc-biased signal to be centered to near mid-point of the amplifier (±0.9 V). Using the gain of the second stage allows for more of the available ADC dynamic range to be used.

The output of the ambient cancellation amplifier is separated into LED2 and LED1 channels. When LED2 is on, the amplifier output is filtered and sampled on capacitor CLED2. Similarly, the LED1 signal is sampled on the CLED1 capacitor when LED1 is on. In between the LED2 and LED1 pulses, the idle amplifier output is sampled to estimate the ambient signal on capacitors CLED2_amb and CLED1_amb.

The sampling duration is termed the Rx sample time and is programmable for each signal, independently. The sampling can start after the I-V amplifier output is stable (to account for LED and cable settling times). The Rx sample time is used for all dynamic range calculations; the minimum time recommended is 50 µs. While the AFE4403 can support pulse widths lower than 50 us, having too low a pulse width could result in a degraded signal and noise from the photodiode.

A single, 22-bit ADC converts the sampled LED2, LED1, and ambient signals sequentially. Each conversion provides a single digital code at the ADC output. As discussed in the Receiver Timing section, the conversions are meant to be staggered so that the LED2 conversion starts after the end of the LED2 sample phase, and so on.

Note that four data streams are available at the ADC output (LED2, LED1, ambient LED2, and ambient LED1) at the same rate as the pulse repetition frequency. The ADC is followed by a digital ambient subtraction block that additionally outputs the (LED2 – ambient LED2) and (LED1 – ambient LED1) data values.

The model of the photodiode and the connection to the TIA is shown in Figure 8-2.

GUID-226A1470-7453-4CB3-98BB-4A9FB0409D0D-low.gifFigure 8-2 TIA Block Diagram

Iin is the signal current generated by the photodiode in response to the incident light. Cin is the zero-bias capacitance of the photodiode. The current-to-voltage gain in the TIA is given by Equation 2:

Equation 2. VTIA (diff) = VTIA+ – VTIA– = 2 × Iin × RF

For example, for a photodiode current of Iin = 1 µA and a TIA gain setting of RF = 100 kΩ, the differential output of the TIA is equal to 200 mV. The TIA has an operating range of ±1 V, and the ADC has an input full-scale range of ±1.2 V (the extra margin is to prevent the ADC from saturating while operating the TIA at the fullest output range). Furthermore, because the PPG signal is one-sided, only one half of the full-scale is used. TI recommends operating the device at a dc level that is not more than 50% to 60% of the ADC full-scale. The margin allows for sudden changes in the signal level that might saturate the signal chain if operating too close to full-scale. Signal levels are shown in Figure 8-3:

GUID-1BC28021-B97F-42AE-9831-938F8EC52361-low.gifFigure 8-3 Signal Levels in TIA and ADC

On startup, a gain calibration algorithm running on the microcontroller unit (MCU) can be used to monitor the dc level and adjusts the LED current and TIA gain to get close to the target dc level. In addition to a target dc level, a high and low threshold (for example 80% and 20% of full-scale) can be determined that can cause the algorithm to switch to a different TIA gain or LED current setting when the signal amplitude changes beyond these thresholds.

In heart rate monitoring (HRM) applications demanding small-form factors, the sensor size can be so small (and the signal currents so low) that they do not occupy even 50% of full-scale even with the highest TIA gain setting of 1 MΩ, which is the case for signal currents that are less than 300 nA. As such, experimentation with various use cases is essential in order to determine the optimal target value, as well as high and low thresholds. Also, by enabling the stage 2 and introducing additional gain (up to 12 dB), a few extra decibels of SNR can be achieved.