SLASFB2 November 2023 AFE432A3W , AFE532A3W
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
DAC channel 1 can be configured as programmable comparator in the voltage-output mode. To enter the comparator mode for channel 1, write 1 to the CMP-1-EN bit in DAC-1-GAIN-CMP-CONFIG register. The comparator output can be configured as push-pull or open-drain using the CMP-1-OD-EN bit. To enable the comparator output on the output pin, write 1 to the CMP-1-OUT-EN bit. To invert the comparator output, write 1 to the CMP-1-INV-EN bit. The FB1 pin has a finite impedance. By default, the FB1 pin is in the high-impedance mode. To disable high-impedance on the FB1 pin, write 1 to the CMP-1-HIZ-IN-DIS bit. Table 6-1 shows the comparator output at the pin for different bit settings. The output of the comparator is indicated by the CMP-FLAG-1 bit in the CMP-STATUS register.
CMP-1-EN | CMP-1-OUT-EN | CMP-1-OD-EN | CMP-1-INV-EN | CMPX-OUT PIN |
---|---|---|---|---|
0 | X | X | X | Comparator not enabled |
1 | 0 | X | X | No output |
1 | 1 | 0 | 0 | Push-pull output |
1 | 1 | 0 | 1 | Push-pull and inverted output |
1 | 1 | 1 | 0 | Open-drain output |
1 | 1 | 1 | 1 | Open-drain and inverted output |
Figure 6-2 shows the interface circuit when DAC channel 1 is configured as a comparator. The programmable comparator operation is as shown in Figure 6-3. The comparator can be configured in no-hysteresis, with-hysteresis, and window-comparator modes using the CMP-1-MODE bit in the respective DAC-1-CMP-MODE-CONFIG register, as shown in Table 6-2.
CMP-1-MODE BIT FIELD | COMPARATOR CONFIGURATION |
---|---|
00 | Normal comparator mode. No hysteresis or window operation. |
01 | Hysteresis comparator mode. DAC-1-MARGIN-HIGH and DAC-1-MARGIN-LOW registers set the hysteresis. |
10 | Window comparator mode. DAC-1-MARGIN-HIGH and DAC-1-MARGIN-LOW registers set the window bounds. |
11 | Invalid setting |