SLASFB2 November 2023 AFE432A3W , AFE532A3W
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Table 6-2 shows that comparator mode provides hysteresis when the CMP-1-MODE bit is set to 01b. Figure 6-4 shows that the hysteresis is provided by the DAC-1-MARGIN-HIGH and DAC-1-MARGIN-LOW registers.
When the DAC-1-MARGIN-HIGH is set to full-code or the DAC-1-MARGIN-LOW is set to zero-code, the comparator works as a latching comparator that is, the output is latched after the threshold is crossed. The latched output can be reset by writing to the corresponding RESET-CMP-FLAG-1 bit in the COMMON-DAC-TRIG register. Figure 6-5 shows the behavior of a latching comparator with active low output, and Figure 6-6 shows the behavior of a latching comparator with active high output.