SLASFB2 November   2023 AFE432A3W , AFE532A3W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Voltage Output
    6. 5.6  Electrical Characteristics: Current Output
    7. 5.7  Electrical Characteristics: Comparator Mode
    8. 5.8  Electrical Characteristics: ADC Input
    9. 5.9  Electrical Characteristics: General
    10. 5.10 Timing Requirements: I2C Standard Mode
    11. 5.11 Timing Requirements: I2C Fast Mode
    12. 5.12 Timing Requirements: I2C Fast-Mode Plus
    13. 5.13 Timing Requirements: SPI Write Operation
    14. 5.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    15. 5.15 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    16. 5.16 Timing Requirements: GPIO
    17. 5.17 Timing Diagrams
    18. 5.18 Typical Characteristics: Voltage Output
    19. 5.19 Typical Characteristics: Current Output
    20. 5.20 Typical Characteristics: Comparator
    21. 5.21 Typical Characteristics: ADC
    22. 5.22 Typical Characteristics: General
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Smart Analog Front End (AFE) Architecture
      2. 6.3.2 Digital Input/Output
      3. 6.3.3 Nonvolatile Memory (NVM)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Voltage-Output Mode
        1. 6.4.1.1 Voltage Reference and DAC Transfer Function
          1. 6.4.1.1.1 Internal Reference
          2. 6.4.1.1.2 Power-Supply as Reference
      2. 6.4.2 Current-Output Mode
      3. 6.4.3 Comparator Mode
        1. 6.4.3.1 Programmable Hysteresis Comparator
        2. 6.4.3.2 Programmable Window Comparator
      4. 6.4.4 Analog-to-Digital Converter (ADC) Mode
      5. 6.4.5 Fault-Dump Mode
      6. 6.4.6 Application-Specific Modes
        1. 6.4.6.1 Voltage Margining and Scaling
          1. 6.4.6.1.1 High-Impedance Output and PROTECT Input
          2. 6.4.6.1.2 Programmable Slew-Rate Control
        2. 6.4.6.2 Function Generation
          1. 6.4.6.2.1 Triangular Waveform Generation
          2. 6.4.6.2.2 Sawtooth Waveform Generation
          3. 6.4.6.2.3 Sine Waveform Generation
      7. 6.4.7 Device Reset and Fault Management
        1. 6.4.7.1 Power-On Reset (POR)
        2. 6.4.7.2 External Reset
        3. 6.4.7.3 Register-Map Lock
        4. 6.4.7.4 NVM Cyclic Redundancy Check (CRC)
          1. 6.4.7.4.1 NVM-CRC-FAIL-USER Bit
          2. 6.4.7.4.2 NVM-CRC-FAIL-INT Bit
      8. 6.4.8 General-Purpose Input/Output (GPIO) Modes
    5. 6.5 Programming
      1. 6.5.1 SPI Programming Mode
      2. 6.5.2 I2C Programming Mode
        1. 6.5.2.1 F/S Mode Protocol
        2. 6.5.2.2 I2C Update Sequence
          1. 6.5.2.2.1 Address Byte
          2. 6.5.2.2.2 Command Byte
        3. 6.5.2.3 I2C Read Sequence
  8. 7 Register Map
    1. 7.1  NOP Register (address = 00h) [reset = 0000h]
    2. 7.2  DAC-0-MARGIN-HIGH Register (address = 0Dh) [reset = 0000h]
    3. 7.3  DAC-1-MARGIN-HIGH Register (address = 13h) [reset = 0000h]
    4. 7.4  DAC-2-MARGIN-HIGH Register (address = 01h) [reset = 0000h]
    5. 7.5  DAC-0-MARGIN-LOW Register (address = 0Eh) [reset = 0000h]
    6. 7.6  DAC-1-MARGIN-LOW Register (address = 14h) [reset = 0000h]
    7. 7.7  DAC-2-MARGIN-LOW Register (address = 02h) [reset = 0000h]
    8. 7.8  DAC-0-GAIN-CONFIG Register (address = 0Fh) [reset = 0000h]
    9. 7.9  DAC-1-GAIN-CMP-CONFIG Register (address = 15h) [reset = 0000h]
    10. 7.10 DAC-2-GAIN-CONFIG Register (address = 03h) [reset = 0000h]
    11. 7.11 DAC-1-CMP-MODE-CONFIG Register (address = 17h) [reset = 0000h]
    12. 7.12 DAC-0-FUNC-CONFIG Register (address = 12h) [reset = 0000h]
    13. 7.13 DAC-1-FUNC-CONFIG Register (address = 18h) [reset = 0000h]
    14. 7.14 DAC-2-FUNC-CONFIG Register (address = 06h) [reset = 0000h]
    15. 7.15 DAC-0-DATA Register (address = 1Bh) [reset = 0000h]
    16. 7.16 DAC-1-DATA Register (address = 1Ch) [reset = 0000h]
    17. 7.17 DAC-2-DATA Register (address = 19h) [reset = 0000h]
    18. 7.18 ADC-CONFIG-TRIG Register (address = 1Dh) [reset = 0000h]
    19. 7.19 ADC-DATA Register (address = 1Eh) [reset = 0001h]
    20. 7.20 COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
    21. 7.21 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
    22. 7.22 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
    23. 7.23 GENERAL-STATUS Register (address = 22h) [reset = 20h, DEVICE-ID, VERSION-ID]
    24. 7.24 CMP-STATUS Register (address = 23h) [reset = 000Ch]
    25. 7.25 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
    26. 7.26 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
    27. 7.27 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
    28. 7.28 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
    29. 7.29 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
    30. 7.30 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBH|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Register Map

Table 7-1 Register Map: Channel-Specific Registers
REGISTER(1)(2) MOST SIGNIFICANT DATA BYTE (MSDB) LEAST SIGNIFICANT DATA BYTE (LSDB)
BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
NOP NOP
DAC-0-MARGIN-HIGH DAC-0-MARGIN-HIGH X
DAC-1-MARGIN-HIGH DAC-1-MARGIN-HIGH X
DAC-2-MARGIN-HIGH DAC-2-MARGIN-HIGH X
DAC-0-MARGIN-LOW DAC-0-MARGIN-LOW X
DAC-1-MARGIN-LOW DAC-1-MARGIN-LOW X
DAC-2-MARGIN-LOW DAC-2-MARGIN-LOW X
DAC-0-GAIN-CONFIG X REF-GAIN X
DAC-1-GAIN-CMP-CONFIG X REF-GAIN X CMP-1-OD-EN CMP-1-OUT-EN CMP-1-HIZ-IN-DIS CMP-1-INV-EN CMP-1-EN
DAC-2-GAIN-CONFIG X IOUT-GAIN X
DAC-1-CMP-MODE-CONFIG X CMP-1-MODE X
DAC-0-FUNC-CONFIG CLR-SEL-0 SYNC-CONFIG-0 BRD-CONFIG-0 FUNC-GEN-CONFIG-BLOCK-0
DAC-1-FUNC-CONFIG CLR-SEL-1 SYNC-CONFIG-1 BRD-CONFIG-1 FUNC-GEN-CONFIG-BLOCK-1
DAC-2-FUNC-CONFIG CLR-SEL-2 SYNC-CONFIG-2 BRD-CONFIG-2 FUNC-GEN-CONFIG-BLOCK-1
DAC-0-DATA DAC-0-DATA X
DAC-1-DATA DAC-1-DATA X
DAC-2-DATA DAC-2-DATA X
ADC-CONFIG-TRIG RESERVED ADC-EN ADC-AVG RESERVED TRIG-ADC
ADC-DATA ADC-DATA X ADC-DRDY
Table 7-2 Register Map: Common Registers
REGISTER(1)(2) MOST SIGNIFICANT DATA BYTE (MSDB) LEAST SIGNIFICANT DATA BYTE (LSDB)
BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
COMMON-CONFIG WIN-LATCH-EN DEV-LOCK EE-READ-ADDR EN-INT-REF DAC-PDN-1 RESERVED DAC-PDN-0 RESERVED DAC-PDN-2 RESERVED
COMMON-TRIGGER DEV-UNLOCK RESET LDAC CLR X FAULT-DUMP PROTECT READ-ONE-TRIG NVM-PROG NVM-RELOAD
COMMON-DAC-TRIG X TRIG-MAR-LO-2 TRIG-MAR-HI-2 START-FUNC-2 X TRIG-MAR-LO-0 TRIG-MAR-HI-0 START-FUNC-0 RESET-CMP-FLAG-1 TRIG-MAR-LO-1 TRIG-MAR-HI-1 START-FUNC-1
GENERAL-STATUS NVM-CRC-FAIL-INT NVM-CRC-FAIL-USER ADC-DRDY DAC-BUSY-1 DAC-BUSY-0 X DAC-BUSY-2 NVM-BUSY DEVICE-ID VERSION-ID
CMP-STATUS X PROTECT-FLAG WIN-CMP-1 X CMP-FLAG-1 X
GPIO-CONFIG GF-EN X GPO-EN GPO-CONFIG GPI-CH-SEL GPI-CONFIG GPI-EN
DEVICE-MODE-CONFIG RESERVED PROTECT-CONFIG RESERVED X
INTERFACE-CONFIG X TIMEOUT-EN X RESERVED X FSDO-EN X SDO-EN
SRAM-CONFIG X SRAM-ADDR
SRAM-DATA SRAM-DATA
BRDCAST-DATA BRDCAST-DATA X
(1) The highlighted gray cells indicate the register bits or fields that are stored in the NVM.
(2) X = Don't care.
Table 7-3 Register Names
I2C/SPI ADDRESS REGISTER NAME SECTION
00h NOP Section 7.1
01h DAC-2-MARGIN-HIGH Section 7.4
02h DAC-2-MARGIN-LOW Section 7.7
03h DAC-2-GAIN-CONFIG Section 7.10
06h DAC-2-FUNC-CONFIG Section 7.14
0Dh DAC-0-MARGIN-HIGH Section 7.2
0Eh DAC-0-MARGIN-LOW Section 7.6
0Fh DAC-0-GAIN-CONFIG Section 7.8
12h DAC-0-FUNC-CONFIG Section 7.12
13h DAC-1-MARGIN-HIGH Section 7.3
14h DAC-1-MARGIN-LOW Section 7.6
15h DAC-1-GAIN-CMP-CONFIG Section 7.9
17h DAC-1-CMP-MODE-CONFIG Section 7.11
18h DAC-1-FUNC-CONFIG Section 7.13
19h DAC-2-DATA Section 7.17
1Bh DAC-0-DATA Section 7.15
1Ch DAC-1-DATA Section 7.16
1Dh ADC-CONFIG-TRIG Section 7.18
1Eh ADC-DATA Section 7.19
1Fh COMMON-CONFIG Section 7.20
20h COMMON-TRIGGER Section 7.21
21h COMMON-DAC-TRIG Section 7.22
22h GENERAL-STATUS Section 7.23
23h CMP-STATUS Section 7.24
24h GPIO-CONFIG Section 7.25
25h DEVICE-MODE-CONFIG Section 7.26
26h INTERFACE-CONFIG Section 7.27
2Bh SRAM-CONFIG Section 7.28
2Ch SRAM-DATA Section 7.29
50h BRDCAST-DATA Section 7.30
Table 7-4 Access Type Codes
Access Type Code Description
X X Don't care
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value