SBASAC1A august   2021  – july 2023 AFE439A2 , AFE539A4 , AFE639D2

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Comparator Mode
    7. 6.7  Electrical Characteristics: ADC Input
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: PWM Output
    16. 6.16 Timing Requirements: I2C Controller
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics: Voltage Output
    19. 6.19 Typical Characteristics: ADC
    20. 6.20 Typical Characteristics: Comparator
    21. 6.21 Typical Characteristics: General
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
      2. 7.4.2 Voltage Reference and DAC Transfer Function
        1. 7.4.2.1 Power-Supply as Reference
        2. 7.4.2.2 Internal Reference
        3. 7.4.2.3 External Reference
      3. 7.4.3 Comparator Mode
      4. 7.4.4 Analog-to-Digital Converter (ADC) Mode
      5. 7.4.5 Pulse-Width Modulation (PWM)
      6. 7.4.6 Proportional-Integral (PI) Control
        1. 7.4.6.1 AFE439A2 PI Control
        2. 7.4.6.2 AFE539A4 PI Control
        3. 7.4.6.3 AFE639D2 PI Control
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h)
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh)
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  STATE-MACHINE-CONFIG1 Register (address = 29h) [reset = C800h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics: Voltage Output

at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1 ×, 12-bit resolution, and DAC outputs unloaded (unless otherwise noted)

GUID-20230701-SS0I-PJCV-NGHF-KWXTLGKDTHZX-low.svg
Internal reference, gain = 4 ×
Figure 6-4 Voltage Output INL vs Digital Input Code
GUID-20230701-SS0I-SCFG-XBJM-BZC1D0JRC3S1-low.svg
 
Figure 6-6 Voltage Output INL vs Temperature
GUID-20230701-SS0I-LDQV-WNQ0-X5MH81GQJFXX-low.svg
Internal reference, gain = 4x
Figure 6-8 Voltage Output DNL vs Digital Input Code
GUID-20230701-SS0I-NFDP-07CW-GHFH9QHDNHPX-low.svg
 
Figure 6-10 Voltage Output DNL vs Temperature
GUID-20230701-SS0I-ZMXP-CKXH-CVK5J4WHKXSF-low.svg
Internal reference, gain = 4 ×
Figure 6-12 Voltage Output TUE vs Digital Input Code
GUID-20230701-SS0I-LTH3-LJDV-PKPLHMMJCVH2-low.svg
DAC channels at midscale
Figure 6-14 Voltage Output TUE vs Temperature
GUID-20230701-SS0I-LN5T-LL2Z-GXVJ8SLZNFP7-low.svg
 
Figure 6-16 Voltage Output Offset Error vs Temperature
GUID-20230701-SS0I-WRPN-SGGW-CP0S6PPV7SZ3-low.svg
DAC channels at midscale 
Figure 6-18 Voltage Output vs Load Current
GUID-20230701-SS0I-BSCT-4K2W-KTCCCGWVT2DK-low.svg
 
Figure 6-20 Voltage Output Code-to-Code Glitch - Falling Edge
GUID-20211028-SS0I-ZWSW-N4VP-B2JWTJSZ2KG4-low.svg
Full scale to zero scale swing
Figure 6-22 Voltage Output Setting Time - Falling Edge
GUID-20211028-SS0I-QXZP-ZVBL-VMKDDTBXDQF1-low.svg
DAC at zero scale 
Figure 6-24 Voltage Output Power-Off Glitch
GUID-20211028-SS0I-DX2L-CT3V-RNN8RCCBPKX9-low.svg
 
Figure 6-26 Voltage Output Noise Density
GUID-20211028-SS0I-FHNC-K2X0-MD2PPQK5TNRD-low.svg
f = 0.1 Hz to 10 Hz 
Figure 6-28 Voltage Output Flicker Noise
GUID-20230701-SS0I-F8DV-5CZQ-RHKP5TWDBWRS-low.svg
 
Figure 6-5 Voltage Output INL vs Digital Input Code
GUID-20230701-SS0I-XB7C-XSPB-3WVNR17VHJJW-low.svg
 
Figure 6-7 Voltage Output INL vs Supply Voltage
GUID-20230701-SS0I-LK22-3J68-7Q1RXVT1MDSL-low.svg
 
Figure 6-9 Voltage Output DNL vs Digital Input Code
GUID-20230701-SS0I-72GD-9MMG-J2DFNJVVGP9V-low.svg
 
Figure 6-11 Voltage Output DNL vs Supply Voltage
GUID-20230701-SS0I-RR7T-C2R3-40J5JZGXQXMP-low.svg
 
Figure 6-13 Voltage Output TUE vs Digital Input Code
GUID-20230701-SS0I-CKBD-HQ9C-PL6PVGQ9ZZC1-low.svg
DAC channels at midscale
Figure 6-15 Voltage Output TUE vs Supply Voltage
GUID-20230701-SS0I-ZZ6H-GRPS-28TLTZW5MJ8C-low.svg
 
Figure 6-17 Voltage Output Gain Error vs Temperature
GUID-20230701-SS0I-2XNB-4BV5-Q9MW8F1RLVCJ-low.svg
 
Figure 6-19 Voltage Output Code-to-Code Glitch - Rising Edge
GUID-20211028-SS0I-2GJL-SHNH-K1SFJJHZCH4W-low.svg
Zero scale to full scale swing 
Figure 6-21 Voltage Output Setting Time - Rising Edge
GUID-20211028-SS0I-VGC7-JRDN-KM2NWKHZ61RB-low.svg
DAC in Hi-Z power-down mode
Figure 6-23 Voltage Output Power-On Glitch
GUID-20211028-SS0I-QZLC-9XXN-6RBHPLWPZWNR-low.svg
Internal reference, gain = 4 ×
Figure 6-25 Voltage Output Noise Density
GUID-20211028-SS0I-GRVW-XMWF-KTWJZQTNFLTL-low.svg
Internal reference, gain = 4 ×, f = 0.1 Hz to 10 Hz
Figure 6-27 Voltage Output Flicker Noise
GUID-20211028-SS0I-8QBN-36CV-V34TQMMXJ82D-low.svg
 
Figure 6-29 Voltage Output AC PSRR vs Frequency