SBASB81 December 2024 AFE5401-EP
PRODUCTION DATA
To enhance system-level debug capabilities, the device offers a mode where the output of each block in the signal chain can be connected to the ADC input. With this mode, internal signals can be easily monitored to ensure that each block output is not saturated. Figure 7-17 shows the device signal chain block diagram. Figure 7-18 and Figure 7-19 show typical frequency response plots at the output of each stage.