SBASB81 December   2024 AFE5401-EP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Digital Characteristics
    7. 5.7  Timing Requirements: Output Interface
    8. 5.8  Timing Requirements: RESET
    9. 5.9  Timing Requirements: Serial Interface Operation
    10. 5.10 Typical Characteristics
  7. Parameter Measurement Information
    1. 6.1 Timing Requirements: Across Output Serialization Modes
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Noise Amplifier (LNA)
      2. 7.3.2 Programmable Gain Amplifier (PGA)
      3. 7.3.3 Antialiasing Filter
      4. 7.3.4 Analog-to-Digital Converter (ADC)
      5. 7.3.5 Digital Gain
      6. 7.3.6 Input Clock Divider
      7. 7.3.7 Data Output Serialization
      8. 7.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 7.3.8.1 Main Channels
        2. 7.3.8.2 Auxiliary Channel
    4. 7.4 Device Functional Modes
      1. 7.4.1 Equalizer Mode
      2. 7.4.2 Data Output Mode
        1. 7.4.2.1 Header
        2. 7.4.2.2 Test Pattern Mode
      3. 7.4.3 Parity
      4. 7.4.4 Standby, Power-Down Mode
      5. 7.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 7.4.5.1 Decimate-by-2 Mode
        2. 7.4.5.2 Decimate-by-4 Mode
      6. 7.4.6 Diagnostic Mode
      7. 7.4.7 Signal Chain Probe
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
        1. 7.5.2.1 Register Write Mode
        2. 7.5.2.2 Register Read Mode
      3. 7.5.3 CMOS Output Interface
        1. 7.5.3.1 Synchronization and Triggering
    6. 7.6 Register Maps
      1. 7.6.1 Functional Register Map
      2. 7.6.2 Register Descriptions
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
      2. 8.3.2 Power Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

Typical values are at TA = +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.

AFE5401-EP FFT for 3-MHz, –1-dBFS Input Signal, 0-dB PGA Gain (Sample Rate = 25 MSPS)
SNR = 67.7 dBFSSFDR = 65.7 dBcTHD = 65.2 dBc
Figure 5-5 FFT for 3-MHz, –1-dBFS Input Signal, 0-dB PGA Gain (Sample Rate = 25 MSPS)
AFE5401-EP FFT with Two-Tone Signal
fIN1 = 1.5 MHzEach Tone at –7-dBFS Amplitude
fIN2 = 2 MHzTwo-Tone IMD = –83 dBFS
Figure 5-7 FFT with Two-Tone Signal
AFE5401-EP Signal-to-Noise Ratio vs Input Signal Frequency (PGA Gain = 0 dB)
Figure 5-9 Signal-to-Noise Ratio vs Input Signal Frequency (PGA Gain = 0 dB)
AFE5401-EP Signal-to-Noise Ratio vs PGA Gain
Figure 5-11 Signal-to-Noise Ratio vs PGA Gain
AFE5401-EP Signal-to-Noise Ratio, Spurious-Free Dynamic Range vs Input Signal Amplitude (PGA Gain = 0 dB)
Figure 5-13 Signal-to-Noise Ratio, Spurious-Free Dynamic Range vs Input Signal Amplitude (PGA Gain = 0 dB)
AFE5401-EP Signal-to-Noise Ratio vs Input Clock Amplitude (PGA Gain = 0 dB)
Figure 5-15 Signal-to-Noise Ratio vs Input Clock Amplitude (PGA Gain = 0 dB)
AFE5401-EP Signal-to-Noise Ratio vs Input Clock Duty Cycle (PGA Gain = 0 dB)
Figure 5-17 Signal-to-Noise Ratio vs Input Clock Duty Cycle (PGA Gain = 0 dB)
AFE5401-EP Signal-to-Noise Ratio vs Sampling Frequency (PGA Gain = 0 dB)
Figure 5-19 Signal-to-Noise Ratio vs Sampling Frequency (PGA Gain = 0 dB)
AFE5401-EP Spurious-Free Dynamic Range vs Sampling Frequency (PGA Gain = 0 dB)
Figure 5-21 Spurious-Free Dynamic Range vs Sampling Frequency (PGA Gain = 0 dB)
AFE5401-EP Signal-to-Noise Ratio vs LNA Gain (PGA Gain = 30 dB)
Figure 5-23 Signal-to-Noise Ratio vs LNA Gain (PGA Gain = 30 dB)
AFE5401-EP Input-Referred Noise vs LNA Gain (PGA Gain = 30 dB)
Figure 5-25 Input-Referred Noise vs LNA Gain (PGA Gain = 30 dB)
AFE5401-EP Output-Referred Noise vs PGA Gain
Figure 5-27 Output-Referred Noise vs PGA Gain
AFE5401-EP Gain Matching Histogram (Maximum Gain Difference Among the Four Channels within a Device)
Figure 5-29 Gain Matching Histogram (Maximum Gain Difference Among the Four Channels within a Device)
AFE5401-EP Offset Error Histogram at PGA Gain = 30 dB
Figure 5-31 Offset Error Histogram at PGA Gain = 30 dB
AFE5401-EP Antialias Filter Response vs FILTER_BW Settings (PGA Gain = 30 dB)
Figure 5-33 Antialias Filter Response vs FILTER_BW Settings (PGA Gain = 30 dB)
AFE5401-EP Antialias Filter Response for Equalizer Modes (PGA Gain = 0 dB)
Figure 5-35 Antialias Filter Response for Equalizer Modes (PGA Gain = 0 dB)
AFE5401-EP FFT for AUX Channel (3-MHz, –1-dBFS Input Signal, Sample Rate = 25 MSPS)
SNR = 69.2 dBFSSFDR = 69.8 dBcTHD = 69.7 dBc
Figure 5-37 FFT for AUX Channel (3-MHz, –1-dBFS Input Signal, Sample Rate = 25 MSPS)
AFE5401-EP Decimate-by-4 Filter Response (Sampling Frequency = 12.5 MHz)
Figure 5-39 Decimate-by-4 Filter Response (Sampling Frequency = 12.5 MHz)
AFE5401-EP DVDD18 Supply Current vs Sampling Frequency
Figure 5-41 DVDD18 Supply Current vs Sampling Frequency
AFE5401-EP DRVDD Supply Current vs Sampling Frequency (15-pF Load with Toggle Test Mode)
Figure 5-43 DRVDD Supply Current vs Sampling Frequency (15-pF Load with Toggle Test Mode)
AFE5401-EP FFT for 3-MHz, –1-dBFS Input Signal, 30-dB PGA Gain (Sample Rate = 25 MSPS)
SNR = 53.3 dBFSSFDR = 63.7 dBcTHD = 63.6 dBc
Figure 5-6 FFT for 3-MHz, –1-dBFS Input Signal, 30-dB PGA Gain (Sample Rate = 25 MSPS)
AFE5401-EP Spurious-Free Dynamic Range vs Input Signal Frequency
Figure 5-8 Spurious-Free Dynamic Range vs Input Signal Frequency
AFE5401-EP Signal-To-Noise Ratio vs Input Signal Frequency (PGA Gain = 30 dB)
Figure 5-10 Signal-To-Noise Ratio vs Input Signal Frequency (PGA Gain = 30 dB)
AFE5401-EP Spurious-Free Dynamic Range vs PGA Gain
Figure 5-12 Spurious-Free Dynamic Range vs PGA Gain
AFE5401-EP Signal-to-Noise Ratio, Spurious-Free Dynamic Range vs Input Signal Amplitude (PGA Gain = 30 dB)
Figure 5-14 Signal-to-Noise Ratio, Spurious-Free Dynamic Range vs Input Signal Amplitude (PGA Gain = 30 dB)
AFE5401-EP Spurious-Free Dynamic Range vs Input Clock Amplitude (PGA Gain = 0 dB)
Figure 5-16 Spurious-Free Dynamic Range vs Input Clock Amplitude (PGA Gain = 0 dB)
AFE5401-EP Spurious-Free Dynamic Range vs Input Clock Amplitude (PGA Gain = 0 dB)
Figure 5-18 Spurious-Free Dynamic Range vs Input Clock Amplitude (PGA Gain = 0 dB)
AFE5401-EP Signal-to-Noise Ratio vs Sampling Frequency (PGA Gain = 30 dB)
Figure 5-20 Signal-to-Noise Ratio vs Sampling Frequency (PGA Gain = 30 dB)
AFE5401-EP Spurious-Free Dynamic Range vs Sampling Frequency (PGA Gain = 30 dB)
Figure 5-22 Spurious-Free Dynamic Range vs Sampling Frequency (PGA Gain = 30 dB)
AFE5401-EP Spurious-Free Dynamic Range vs LNA Gain (PGA Gain = 30 dB)
Figure 5-24 Spurious-Free Dynamic Range vs LNA Gain (PGA Gain = 30 dB)
AFE5401-EP Input-Referred Noise vs PGA Gain
Figure 5-26 Input-Referred Noise vs PGA Gain
AFE5401-EP Gain Error Histogram for PGA Gain = 30 dB
Figure 5-28 Gain Error Histogram for PGA Gain = 30 dB
AFE5401-EP Channel Offset vs PGA Gain for Two Typical Devices
Figure 5-30 Channel Offset vs PGA Gain for Two Typical Devices
AFE5401-EP Antialias Filter Response vs FILTER_BW Settings (PGA Gain = 0 dB)
Figure 5-32 Antialias Filter Response vs FILTER_BW Settings (PGA Gain = 0 dB)
AFE5401-EP Antialias Filter Response vs AVDD18 (PGA Gain = 0 dB, FILTER_BW = 8 MHz)
Figure 5-34 Antialias Filter Response vs AVDD18 (PGA Gain = 0 dB, FILTER_BW = 8 MHz)
AFE5401-EP Antialias Filter Response for Equalizer Modes (PGA Gain = 30 dB)
Figure 5-36 Antialias Filter Response for Equalizer Modes (PGA Gain = 30 dB)
AFE5401-EP Decimate-by-2 Filter Response (Sampling Frequency = 50 MHz)
Figure 5-38 Decimate-by-2 Filter Response (Sampling Frequency = 50 MHz)
AFE5401-EP AVDD18 Supply Current vs Sampling Frequency
Figure 5-40 AVDD18 Supply Current vs Sampling Frequency
AFE5401-EP AVDD3 Supply Current vs Sampling Frequency
Figure 5-42 AVDD3 Supply Current vs Sampling Frequency
AFE5401-EP AFE Core Power, Channel Excluding DRVDD
Figure 5-44 AFE Core Power, Channel Excluding DRVDD