SBASB81 December   2024 AFE5401-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Digital Characteristics
    7. 5.7  Timing Requirements: Output Interface
    8. 5.8  Timing Requirements: RESET
    9. 5.9  Timing Requirements: Serial Interface Operation
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Timing Requirements: Across Output Serialization Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Noise Amplifier (LNA)
      2. 7.3.2 Programmable Gain Amplifier (PGA)
      3. 7.3.3 Antialiasing Filter
      4. 7.3.4 Analog-to-Digital Converter (ADC)
      5. 7.3.5 Digital Gain
      6. 7.3.6 Input Clock Divider
      7. 7.3.7 Data Output Serialization
      8. 7.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 7.3.8.1 Main Channels
        2. 7.3.8.2 Auxiliary Channel
    4. 7.4 Device Functional Modes
      1. 7.4.1 Equalizer Mode
      2. 7.4.2 Data Output Mode
        1. 7.4.2.1 Header
        2. 7.4.2.2 Test Pattern Mode
      3. 7.4.3 Parity
      4. 7.4.4 Standby, Power-Down Mode
      5. 7.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 7.4.5.1 Decimate-by-2 Mode
        2. 7.4.5.2 Decimate-by-4 Mode
      6. 7.4.6 Diagnostic Mode
      7. 7.4.7 Signal Chain Probe
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
        1. 7.5.2.1 Register Write Mode
        2. 7.5.2.2 Register Read Mode
      3. 7.5.3 CMOS Output Interface
        1. 7.5.3.1 Synchronization and Triggering
    6. 7.6 Register Maps
      1. 7.6.1 Functional Register Map
      2. 7.6.2 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
      2. 8.3.2 Power Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8.2 Auxiliary Channel

The auxiliary analog inputs (INIP_AUX, INIM _AUX) can be enabled instead of the INIP, INIM inputs using the AUX_CHI_EN bits (Table 7-9). The auxiliary analog input signal path consists of an input unity-gain buffer followed by an ADC. The LNA, PGA, equalizer, and antialiasing filter are bypassed and powered down in this mode. Figure 7-8 shows the internal block diagram for auxiliary channel mode. When this mode is enabled, the maximum input swing is limited to 2 VPP before the input becomes saturated or distorted.

Table 7-9 AUX_CHI_EN Register
AUX_CHI_ENDESCRIPTION
0INIP, INIM active, analog
1INIP _AUX, INIM_AUX
AFE5401-EP Common-Mode Biasing of Auxiliary Channel Input Pins
Dashed area denotes one of four channels.
Figure 7-8 Common-Mode Biasing of Auxiliary Channel Input Pins

The dc common-mode on the INIP_AUX, INIM _AUX pins are internally biased to the optimum voltage (referred to as VCM).

The dc common-mode biasing is set with two internal, programmable, single-ended resistors (RINTTERM_AUX). These resistors can be programmed to a higher value using the TERM_INT_20K_AUX register setting as described in Table 7-10.

Table 7-10 Internal Termination Register Setting (AUX)
TERM_INT_20K_AUXDESCRIPTION
0RINTTERM_AUX = 1 kΩ
1RINTTERM_AUX = 10 kΩ

The auxiliary inputs can also be ac-coupled as a result of the internal common-mode setting. The external input ac-coupling capacitors form a high-pass filter with RINTTERM_AUX. Therefore, the capacitor values should allow the lowest frequency of interest to pass with minimum attenuation.

For typical frequencies greater than 1 MHz, a value of 50 nF or greater is recommended. For instances where the input signal cannot be ac-coupled because of system requirements, it is recommended to use the VCM output to set the dc common-mode of the input signal. The driving capability of VCM is limited. A 100-nF capacitor should be connected on each VCM input to AVSS.