SBASB81 December   2024 AFE5401-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Digital Characteristics
    7. 5.7  Timing Requirements: Output Interface
    8. 5.8  Timing Requirements: RESET
    9. 5.9  Timing Requirements: Serial Interface Operation
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Timing Requirements: Across Output Serialization Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Noise Amplifier (LNA)
      2. 7.3.2 Programmable Gain Amplifier (PGA)
      3. 7.3.3 Antialiasing Filter
      4. 7.3.4 Analog-to-Digital Converter (ADC)
      5. 7.3.5 Digital Gain
      6. 7.3.6 Input Clock Divider
      7. 7.3.7 Data Output Serialization
      8. 7.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 7.3.8.1 Main Channels
        2. 7.3.8.2 Auxiliary Channel
    4. 7.4 Device Functional Modes
      1. 7.4.1 Equalizer Mode
      2. 7.4.2 Data Output Mode
        1. 7.4.2.1 Header
        2. 7.4.2.2 Test Pattern Mode
      3. 7.4.3 Parity
      4. 7.4.4 Standby, Power-Down Mode
      5. 7.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 7.4.5.1 Decimate-by-2 Mode
        2. 7.4.5.2 Decimate-by-4 Mode
      6. 7.4.6 Diagnostic Mode
      7. 7.4.7 Signal Chain Probe
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
        1. 7.5.2.1 Register Write Mode
        2. 7.5.2.2 Register Read Mode
      3. 7.5.3 CMOS Output Interface
        1. 7.5.3.1 Synchronization and Triggering
    6. 7.6 Register Maps
      1. 7.6.1 Functional Register Map
      2. 7.6.2 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
      2. 8.3.2 Power Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2 Data Output Mode

The functionality of DSYNC1, DSYNC2, DCLK, and D[11:0] are controlled by selecting the data output mode. The functionality of the DSYNC1, DSYNC2, DCLK, and D[11:0] output pins for 4x serialization modes are shown in Figure 7-11 and Figure 7-12. Any event on the TRIG pin triggers the DSYNC1 and DSYNC2 signals. The DSYNC1 period is determined by the COMP_DSYNC1 register value and the DSYNC2 period is determined by the SAMPLE_COUNT register value. When OUT_MODE_EN = 0, data output is continuous. When OUT_MODE_EN = 1, data is active only during the sample phase. Output pins are configured using the registers described in Table 7-12 through Table 7-16.

AFE5401-EP Data Output Timing Diagram (4x Serialization)Figure 7-11 Data Output Timing Diagram (4x Serialization)
AFE5401-EP Data Output Timing Diagram (4x Serialization, Input Divider Enabled)Figure 7-12 Data Output Timing Diagram (4x Serialization, Input Divider Enabled)
Table 7-12 Register Functions
REGISTERFUNCTION
DELAY_COUNT[23:0]From a TRIG event, the sample phase is delayed for a DELAY_COUNT number of tAFE_CLK cycles
SAMPLE_COUNT[23:0]From the end of DELAY_PHASE, the sample phase duration is the SAMPLE_COUNT number of tAFE_CLK cycles
COMP_DSYNC1[15:0]DSYNC1 period in number of tAFE_CLKcycles
Table 7-13 DSYNC1_START_LOW Register
DSYNC1_START_LOWDESCRIPTION
0DSYNC1 is high at the sample phase start
1DSYNC1 is low at the sample phase start
Table 7-14 OUT_MODE_EN Register
OUT_MODE_ENDESCRIPTION
0Data always active
1Data active in sample phase
Table 7-15 DSYNC_EN Register
DSYNC_ENDESCRIPTION
0Disable DSYNC generation
1Enable DSYNC generation
Table 7-16 OUT_BLANK_HIZ Register
OUT_BLANK_HIZDESCRIPTION
0D[11:0] is low during inactive phase
1D[11:0] is high impedance during inactive phase


Note:

The signal processing blocks in the device are always active and are not controlled by output mode configuration settings.

The functionality of the DSYNC1, DSYNC2, DCLK, and D[11:0] output pins with the input divider enabled for 3x serializations is shown in Figure 7-13.

AFE5401-EP Data Output Timing (3x Serialization, Input Divider Enabled)Figure 7-13 Data Output Timing (3x Serialization, Input Divider Enabled)

The TRIG to DSYNC2 latency is given by Table 7-17.

Table 7-17 TRIG to DSYNC2 Latency across Serialization Modes for AFE_CLK = 25 MHz
Serialization ModesTTRIG_DSYNC2_LAT(1)Units
4x230ns
3x230ns
2x240ns
1x250ns
(1) The TRIG_DSYNC2_LAT delay can vary by ± 8 ns.