SBASB81 December   2024 AFE5401-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Digital Characteristics
    7. 5.7  Timing Requirements: Output Interface
    8. 5.8  Timing Requirements: RESET
    9. 5.9  Timing Requirements: Serial Interface Operation
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Timing Requirements: Across Output Serialization Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Noise Amplifier (LNA)
      2. 7.3.2 Programmable Gain Amplifier (PGA)
      3. 7.3.3 Antialiasing Filter
      4. 7.3.4 Analog-to-Digital Converter (ADC)
      5. 7.3.5 Digital Gain
      6. 7.3.6 Input Clock Divider
      7. 7.3.7 Data Output Serialization
      8. 7.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 7.3.8.1 Main Channels
        2. 7.3.8.2 Auxiliary Channel
    4. 7.4 Device Functional Modes
      1. 7.4.1 Equalizer Mode
      2. 7.4.2 Data Output Mode
        1. 7.4.2.1 Header
        2. 7.4.2.2 Test Pattern Mode
      3. 7.4.3 Parity
      4. 7.4.4 Standby, Power-Down Mode
      5. 7.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 7.4.5.1 Decimate-by-2 Mode
        2. 7.4.5.2 Decimate-by-4 Mode
      6. 7.4.6 Diagnostic Mode
      7. 7.4.7 Signal Chain Probe
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
        1. 7.5.2.1 Register Write Mode
        2. 7.5.2.2 Register Read Mode
      3. 7.5.3 CMOS Output Interface
        1. 7.5.3.1 Synchronization and Triggering
    6. 7.6 Register Maps
      1. 7.6.1 Functional Register Map
      2. 7.6.2 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
      2. 8.3.2 Power Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Functions

PINDESCRIPTION
NAMENO
D[11:0]35-46CMOS outputs for channels 1 to 4
D_GPO[1:0]47, 48General-purpose CMOS output
AVDD3183.3-V analog supply voltage
AVDD1819, 24, 621.8-V analog supply voltage
AVSS20, 23, 61, 63Analog ground
CLKINM22Negative differential clock input pin. A single-ended clock is also supported.
CLKINP21Positive differential clock input pin. A single-ended clock is also supported.
DCLK34CMOS output clock
DRVDD32, 33, 50CMOS output driver supply
DRVSS31, 49CMOS output driver ground
DSYNC126Data synchronization clock 1
DSYNC227Data synchronization clock 2
DVDD1828, 30, 511.8-V digital supply voltage
DVSS29, 52Digital ground
IN1M4Negative differential analog input pin for channel 1
IN1P3Positive differential analog input pin for channel 1
IN1M_AUX2Negative differential auxiliary analog input pin for channel 1
IN1P_AUX1Positive differential auxiliary analog input pin for channel 1
IN2M8Negative differential analog input pin for channel 2
IN2P7Positive differential analog input pin for channel 2
IN2M_AUX6Negative differential auxiliary analog input pin for channel 2
IN2P_AUX5Positive differential auxiliary analog input pin for channel 2
IN3M12Negative differential analog input pin for channel 3
IN3P11Positive differential analog input pin for channel 3
IN3M_AUX10Negative differential auxiliary analog input pin for channel 3
IN3P_AUX9Positive differential auxiliary analog input pin for channel 3
IN4M16Negative differential analog input pin for channel 4
IN4P15Positive differential analog input pin for channel 4
IN4P_AUX13Positive differential auxiliary analog input pin for channel 4
IN4M_AUX14Negative differential auxiliary analog input pin for channel 4
NC58, 60Do not connect
RESET57Hardware reset pin (active high). This pin has an internal 150-kΩ pull-down resistor.
SCLK56Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.
SDATA55Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.
SDOUT53Serial interface data readout
SEN54Serial interface enable. This pin has an internal 150-kΩ pull-up resistor.
STBY59Standby control input. This pin has an internal 150-kΩ pull-down resistor.
TRIG25Trigger for DSYNC1 and DSYNC2. This pin has an internal 150-kΩ pull-down resistor.
VCM17, 64Output pins for common-mode bias voltage of the auxiliary input signals
Thermal padPadLocated on bottom of package, internally connected to AVSS. Connect to ground plane on the board.