SBASB81 December   2024 AFE5401-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Digital Characteristics
    7. 5.7  Timing Requirements: Output Interface
    8. 5.8  Timing Requirements: RESET
    9. 5.9  Timing Requirements: Serial Interface Operation
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Timing Requirements: Across Output Serialization Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Noise Amplifier (LNA)
      2. 7.3.2 Programmable Gain Amplifier (PGA)
      3. 7.3.3 Antialiasing Filter
      4. 7.3.4 Analog-to-Digital Converter (ADC)
      5. 7.3.5 Digital Gain
      6. 7.3.6 Input Clock Divider
      7. 7.3.7 Data Output Serialization
      8. 7.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 7.3.8.1 Main Channels
        2. 7.3.8.2 Auxiliary Channel
    4. 7.4 Device Functional Modes
      1. 7.4.1 Equalizer Mode
      2. 7.4.2 Data Output Mode
        1. 7.4.2.1 Header
        2. 7.4.2.2 Test Pattern Mode
      3. 7.4.3 Parity
      4. 7.4.4 Standby, Power-Down Mode
      5. 7.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 7.4.5.1 Decimate-by-2 Mode
        2. 7.4.5.2 Decimate-by-4 Mode
      6. 7.4.6 Diagnostic Mode
      7. 7.4.7 Signal Chain Probe
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
        1. 7.5.2.1 Register Write Mode
        2. 7.5.2.2 Register Read Mode
      3. 7.5.3 CMOS Output Interface
        1. 7.5.3.1 Synchronization and Triggering
    6. 7.6 Register Maps
      1. 7.6.1 Functional Register Map
      2. 7.6.2 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
      2. 8.3.2 Power Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Timing Requirements: Across Output Serialization Modes

Table 6-1 and Table 6-2 provide details for the 4x serialization timing requirements for DRVDD = 3.3 V and DRVDD = 1.8 V, respectively. Table 6-3 and Table 6-4 provide details for the 3x serialization timing requirements for DRVDD = 3.3 V and DRVDD = 1.8 V, respectively. Table 6-5 provides the details for the 2x and 1x serialization timing requirements for DRVDD = 1.8 V to 3.3 V.

Table 6-1 Timing Requirements: 4x Serialization (DRVDD = 3.3 V)
INPUT CLOCK FREQUENCY (MHz)OUTPUT CLOCK (DCLK) FREQUENCY (MHz)TEST CONDITIONSSETUP TIME (ns)
tSU		HOLD TIME (ns)
tHO		tOUT (ns)
MINTYPMAXMINTYPMAXMINTYPMAX
12.550CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		9.17.96.79.5
1560CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		7.16.16.79.5
2080CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		5.34.16.79.5
25100CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		4.12.86.79.5
25100CLOAD = 15 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 6		3.52.66.49.0
Table 6-2 Timing Requirements: 4x Serialization (DRVDD = 1.8 V)
INPUT CLOCK FREQUENCY (MHz)OUTPUT CLOCK (DCLK) FREQUENCY (MHz)TEST CONDITIONSSETUP TIME (ns)
tSU		HOLD TIME (ns)
tHO		tOUT (ns)
MINTYPMAXMINTYPMAXMINTYPMAX
12.550CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		9.27.95.610.6
1560CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		7.26.15.610.6
2080CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		5.33.95.610.6
25100CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		3.72.75.610.6
25100CLOAD = 15 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 14		2.62.75.310.0
Table 6-3 Timing Requirements: 3x Serialization (DRVDD = 3.3 V)
INPUT CLOCK FREQUENCY (MHz)OUTPUT CLOCK (DCLK) FREQUENCY (MHz)TEST CONDITIONSSETUP TIME (ns)
tSU		HOLD TIME (ns)
tHO		tOUT (ns)
MINTYPMAXMINTYPMAXMINTYPMAX
12.537.5CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		12.411.820.123.2
1545CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		9.99.117.420.4
2060CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		7.26.315.118.0
2575CLOAD = 5 pF,
STR_CTRL_CLK, STR_CTRL_DATA = 0		5.74.113.416.0
2575CLOAD = 15 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 6		5.13.812.815.3
Table 6-4 Timing Requirements: 3x Serialization (DRVDD = 1.8 V)
INPUT CLOCK FREQUENCY (MHz)OUTPUT CLOCK (DCLK) FREQUENCY (MHz)TEST CONDITIONSSETUP TIME (ns)
tSU		HOLD TIME (ns)
tHO		tOUT (ns)
MINTYPMAXMINTYPMAXMINTYPMAX
12.537.5CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		12.511.919.223.6
1545CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		10.09.316.620.1
2060CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		7.36.414.018.4
2575CLOAD = 5 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 5		5.74.712.416.7
2575CLOAD = 15 pF,
STR_CTRL_CLK and STR_CTRL_DATA = 14		4.7412.116.4
Table 6-5 Timing Requirements: 2x and 1x Serialization (DRVDD = 1.8 V to 3.3 V)
INPUT CLOCK FREQUENCY (MHz)OUTPUT CLOCK (DCLK) FREQUENCY (MHz)TEST CONDITIONSSETUP TIME (ns)
tSU		HOLD TIME (ns)
tHO		tOUT (ns)
MINTYPMAXMINTYPMAXMINTYPMAX
25502x Serialization mode: CLOAD = 5 pF.
For DRVDD = 1.8 V, STR_CTRL_CLK and STR_CTRL_DATA = 5.
For DRVDD = 3.3 V, STR_CTRL_CLK and STR_CTRL_DATA = 0.		7.38.05.510.5
25251x Serialization mode: CLOAD = 5 pF.
For DRVDD = 1.8 V, STR_CTRL_CLK and STR_CTRL_DATA = 5.
For DRVDD = 3.3 V, STR_CTRL_CLK and STR_CTRL_DATA = 0.		18.517.525.230.1