SBASB81 December   2024 AFE5401-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Digital Characteristics
    7. 5.7  Timing Requirements: Output Interface
    8. 5.8  Timing Requirements: RESET
    9. 5.9  Timing Requirements: Serial Interface Operation
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Timing Requirements: Across Output Serialization Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Noise Amplifier (LNA)
      2. 7.3.2 Programmable Gain Amplifier (PGA)
      3. 7.3.3 Antialiasing Filter
      4. 7.3.4 Analog-to-Digital Converter (ADC)
      5. 7.3.5 Digital Gain
      6. 7.3.6 Input Clock Divider
      7. 7.3.7 Data Output Serialization
      8. 7.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 7.3.8.1 Main Channels
        2. 7.3.8.2 Auxiliary Channel
    4. 7.4 Device Functional Modes
      1. 7.4.1 Equalizer Mode
      2. 7.4.2 Data Output Mode
        1. 7.4.2.1 Header
        2. 7.4.2.2 Test Pattern Mode
      3. 7.4.3 Parity
      4. 7.4.4 Standby, Power-Down Mode
      5. 7.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 7.4.5.1 Decimate-by-2 Mode
        2. 7.4.5.2 Decimate-by-4 Mode
      6. 7.4.6 Diagnostic Mode
      7. 7.4.7 Signal Chain Probe
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
        1. 7.5.2.1 Register Write Mode
        2. 7.5.2.2 Register Read Mode
      3. 7.5.3 CMOS Output Interface
        1. 7.5.3.1 Synchronization and Triggering
    6. 7.6 Register Maps
      1. 7.6.1 Functional Register Map
      2. 7.6.2 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
      2. 8.3.2 Power Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6 Input Clock Divider

The device clock input is passed through a clock divider block that can divide the input clock by a factor of 1, 2, 3, or 4. This divided clock (AFE_CLK) is used for simultaneously sampling the four ADC inputs. In default mode, a division factor of 1 is used where the AFE_CLK frequency is the same as the input clock frequency. The clock divider block can be enabled using the DIV_EN register bit and, when enabling this bit, the AFE_CLK frequency is automatically determined by the serialization factor set by the CH_OUT_DIS register bits (Table 7-7). The division factor can also be manually specified by enabling the DIV_FRC and DIV_REG register bits. Care must be taken to ensure that the input clock frequency is within the recommended operating range specified in the Section 5.3.

After device reset, the divider is reset at the first pulse applied on the TRIG pin. This configuration is especially useful when using multiple devices in the system, where the sampling instants of all ADCs in the system must be synchronized. Figure 7-5 illustrates the TRIG timing diagram and the various divided-down AFE_CLK signals. Figure 7-6 provides the TRIG input setup and hold time with respect to the device clock input. Bit settings for the DIV_EN register, DIV_FRD register, and DIV_REG register are provided in Table 7-4, Table 7-5, and Table 7-6, respectively.

AFE5401-EP Input Clock DividerFigure 7-5 Input Clock Divider
AFE5401-EP TRIG CLKIN Setup and HoldFigure 7-6 TRIG CLKIN Setup and Hold
Table 7-4 DIV_EN Register
DIV_ENDESCRIPTION
0Divider disabled and bypassed
1Divider enabled
Table 7-5 DIV_FRC Register
DIV_FRCDESCRIPTION
0Input divider ratio = serialization factor(1) (automatically set)
1Input divider ratio = DIV_REG (manually set)
(1) The divider ratio is automatically calculated to the serialization factor value based on the CH_OUT_DIS[1:4] register bits; see Table 7-7.
Table 7-6 DIV_REG Register
DIV_REGDESCRIPTION
0Divider disabled and bypassed
1Divide-by-2
2Divide-by-3
3Divide-by-4