Table 1. Voltage-Controlled-Attenuator Noise vs Attenuation

8.3.5.1 16 × ƒ_cw Mode

The 16 × ƒ_cw mode achieves the best phase accuracy compared to other modes. The 16 × ƒ_cw mode is the default mode for CW operation. In this mode, 16 × ƒ_cw and 1 × ƒ_cw clocks are required. 16׃_cw generates LO signals with 16 accurate phases. Multiple AFE5808A devices can be synchronized by the 1 × ƒ_cw; that is, LO signals in multiple AFEs can have the same starting phase. The phase noise specification is critical only for the 16X clock. The 1X clock is for synchronization only, and it doesn’t require low phase noise. See the CW Clock Selection.

The top level clock distribution diagram is shown in Figure 66. Each mixer's clock is distributed through a 16 × 8 cross-point switch. The inputs of the cross-point switch are 16 different phases of the 1x clock. TI recommends aligning the rising edges of the 1 × ƒ_cw and 16 × ƒ_cw clocks.

The cross-point switch distributes the clocks with appropriate phase delay to each mixer. For example, Vi(t) is a received signal with a delay of , a delayed LO(t) should be applied to the mixer to compensate for the delay. Thus a 22.5⁰ delayed clock, that is , is selected for this channel. The mathematic calculation is expressed in Equation 2.

Equation 2.

Vo(t) represents the demodulated Doppler signal of each channel. When the doppler signals from N channels are summed, the signal-to-noise ratio improves.

Figure 66. CW Mixer Clock Generation

Figure 67. 1x and 16x CW Clock Timing

8.3.5.2 8 × ƒ_cw and 4 × ƒ_cw Modes

8 × ƒ_cw and 4 × ƒ_cw modes are alternative modes when higher frequency clock solution (that is 16 × ƒ_cw clock) is not available in system. Figure 68 shows the block diagram of these two modes.

Good phase accuracy and matching are also maintained. Quadature clock generator is used to create in-phase and quadrature clocks with exactly 90° phase difference. The only difference between 8 × ƒ_cw and 4 × ƒ_cw modes is the accessibility of the 3rd and 5th harmonic suppression filter. In the 8 × ƒ_cw mode, the suppression filter can be supported. In both modes, phase delay resolution is achieved by weighting the in-phase and quadrature paths correspondingly. For example, if a delay of or 22.5° is targeted, the weighting coefficients should follow Equation 3, assuming I_in and Q_in are sin(ω₀t) and cos(ω₀t) respectively:

Equation 3.

Therefore, after I/Q mixers, phase delay in the received signals is compensated. The mixers’ outputs from all channels are aligned and added linearly to improve the signal-to-noise ratio. TI recommends having the 4 × ƒ_cw or 8 × ƒ_cw and 1 × ƒ_cw clocks aligned both at the rising edge.

Figure 68. 8 X ƒ_cw and 4 X ƒ_cw Block Diagram

Figure 69. 8 x ƒ_cw and 4 x ƒ_cw Timing Diagram

8.3.5.3 1 × ƒ_cw Mode

The 1x ƒ_cw mode requires in-phase and quadrature clocks with low phase noise specifications. The phase delay resolution is also achieved by weighting the in-phase and quadrature signals as described in the 8 × ƒ_cw and 4 × ƒ_cw modes.

Figure 70. Block Diagram of 1 x ƒ_cw mode

8.4.4.1 ADC Test Modes

The AFE5808A device can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal ADC data output. The device may also be made to output 6 preset patterns:

1. Ramp: Setting Register 2[15:13] = 111 causes all the channels to output a repeating full-scale ramp pattern. The ramp increments from zero code to full-scale code in steps of 1 LSB every clock cycle. After hitting the full-scale code, the ADC output returns back to zero code and ramps again.
2. Zeros: The device can be programmed to output all 0s by setting Register 2[15:13] = 110.
3. Ones: The device can be programmed to output all 1s by setting Register 2[15:13] = 100.
4. Deskew Pattern: When 2[15:13] = 010; this mode replaces the 14-bit ADC output with the 01010101010101 word.
5. Sync Pattern: When 2[15:13] = 001, the normal ADC output is replaced by a fixed 11111110000000 word.
6. Toggle: When 2[15:13] = 101, the normal ADC output is alternating between 1s and 0s. The start state of ADC word can be either 1s or 0s.
7. Custom Pattern: This mode can be enabled when 2[15:13] = 011. Users can write the required VALUE into register bits <CUSTOM PATTERN>, which is Register 5[13:0]. Then, the device will output VALUE at its outputs, about 3 to 4 ADC clock cycles after the 24th rising edge of SCLK. So, the time taken to write one value is 24 SCLK clock cycles + 4 ADC clock cycles. To change the customer pattern value, users can repeat writing Register 5[13:0] with a new value. Due to the speed limit of SPI, the refresh rate of the custom pattern may not be high. For example, 128 points custom pattern takes approximately 128 × (24 SCLK clock cycles + 4 ADC clock cycles).

NOTE

Only one of the above ADC patterns can be active at any given instant.

8.4.4.2 VCA Test Mode

The VCA has a test mode in which the CH7 and CH8 PGA outputs can be brought to the CW pins. By monitoring these PGA outputs, the functionality of VCA operation can be verified. The PGA outputs are connected to the virtual ground pins of the summing amplifier (CW_IP_AMPINM/P, CW_QP_AMPINM/P) through 5-kΩ resistors. The PGA outputs can be monitored at the summing amplifier outputs when the LPF capacitors C_EXT are removed. The signals at the summing amplifier outputs are attenuated due to the 5-kΩ resistors. The attenuation coefficient is R_INT/EXT / 5 kΩ.

If users would like to check the PGA outputs without removing C_EXT, an alternative way is to measure the PGA outputs directly at the CW_IP_AMPINM/P and CW_QP_AMPINM/P when the CW summing amplifier is powered down.

Some registers are related to this test mode, PGA Test Mode Enable: Reg59[9]; Buffer Amplifier Power Down Reg59[8]; and Buffer Amplifier Gain Control Reg54[4:0]. Based on the buffer amplifier configuration, the registers can be set in different ways:

• Configuration 1
  • In this configuration, the test outputs can be monitored at CW_AMPINP/M.
  • Reg59[9] = 1; test mode enabled
  • Reg59[8] = 0; buffer amplifier powered-down
• Configuration 2
  • In this configuration, the test outputs can be monitored at CW_OUTP/M.
  • Reg59[9] = 1; test mode enabled
  • Reg59[8] = 1; buffer amplifier powered on
  • Reg54[4:0] = 10H; internal feedback 2-kΩ resistor enabled. Different values can be used as well.

Figure 76. AFE5808A PGA Test Mode

8.4.5.1 Power and Performance Optimization

The AFE5808A device has options to adjust power consumption and meet different noise performances. This feature would be useful for portable systems operated by batteries when low power is more desired. See Electrical Characteristics as well as the Typical Characteristics for more information.

8.4.5.2 Power Management Priority

Power management plays a critical role to extend battery life and ensure long operation time. The AFE5808A device has fast and flexible power-down and power-up control, which can maximize battery life. The AFE5808A device can be powered down and powered up through external pins or internal registers. The following table indicates the affected circuit blocks and priorities when the power management is invoked. The higher priority controls can overwrite the lower priority ones. In the device, all the power down controls are logically ORed to generate final power down for different blocks. Thus, the higher priority controls can cover the lower priority ones. The AFE5808A register settings are maintained when the AFE5808A is in either partial power down mode or complete power down mode.

8.4.5.3 Partial Power Up and Power Down Mode

The partial power-up and power-down mode is also called as fast power-up and power-down mode. In this mode, most amplifiers in the signal path are powered down, while the internal reference circuits remain active as well as the LVDS clock circuit (that is the LVDS circuit still generates its frame and bit clocks).

The partial power down function allows the AFE5808A device to wake up from a low-power state quickly. This configuration ensures that the external capacitors are discharged slowly; thus, a minimum wake-up time is needed as long as the charges on those capacitors are restored. The VCA wake-up response is typically about 2 μs or 1% of the power down duration whichever is larger. The longest wake-up time depends on the capacitors connected at INP and INM, as the wake-up time is the time required to recharge the caps to the desired operating voltages. For 0.1 μF at INP and 15 nF at INM can give a wake-up time of 2.5 ms. For larger capacitors this time will be longer. The ADC wake-up time is about 1 μs. Thus the AFE5808A wake-up time is more dependent on the VCA wake-up time. This also assumes that the ADC clock has been running for at least 50 µs before normal operating mode resumes. The power-down time is instantaneous, less than 1 µs.

This fast wake-up response is desired for portable ultrasound applications in which the power saving is critical. The pulse repetition frequency of a ultrasound system could vary from 50 KHz to 500 Hz, while the imaging depth (that is, the active period for a receive path) varies from 10 μs to hundreds of µs. The power saving can be pretty significant when a system’s PRF is low. In some cases, only the VCA would be powered down while the ADC keeps running normally to ensure minimal impact to FPGAs.

In the partial power-down mode, the AFE5808A typically dissipates only 26 mW/ch, representing an 80% power reduction compared to the normal operating mode. This mode can be set using either pins (PDN_VCA and PDN_ADC) or register bits (VCA_PARTIAL_PDN and ADC_PARTIAL_PDN).

8.4.5.4 Complete Power-Down Mode

To achieve the lowest power dissipation of 0.7 mW/CH, the AFE5808A device can be placed into a complete power-down mode. This mode is controlled through the registers ADC_COMPLETE_PDN, VCA_COMPLETE_PDN or PDN_GLOBAL pin. In the complete power-down mode, all circuits including reference circuits within the AFE5808A device are powered down; and the capacitors connected to the AFE5808A device are discharged. The wake-up time depends on the time needed to recharge these capacitors. The wake-up time depends on the time that the AFE5808A device spends in shutdown mode. 0.1 μF at INP and 15 nF at INM can give a wake-up time close to 2.5 ms.

8.4.5.5 Power Saving in CW Mode

Usually only half the number of channels in a system are active in the CW mode. Thus the individual channel control through ADC_PDN_CH <7:0> and VCA_PDN_CH <7:0> can power down unused channels and save power consumption greatly. Under the default register setting in the CW mode, the voltage controlled attenuator, PGA, and ADC are still active. During the debug phase, both the PW and CW paths can be running simultaneously. In real operation, these blocks need to be powered down manually.

8.5.1.1 Serial Register Write Description

Programming of different modes can be done through the serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET. All these pins have a pulldown resistor to GND of 20 kΩ. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every rising edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 24th SCLK rising edge when SEN is low. If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiple of 24-bit words within a single active SEN pulse (there is an internal counter that counts groups of 24 clocks after the falling edge of SEN). The interface can work with the SCLK frequency from 20 MHz down to low speeds (a few Hz) and even with non-50% duty cycle SCLK. The data is divided into two main portions: a register address (8 bits) and the data itself (16 bits) to load on the addressed register. When writing to a register with unused bits, these must be set to 0. Figure 77 shows this process.

Figure 77. SPI Timing

8.5.1.2 Register Readout Description

The device includes an option where the contents of the internal registers can be read back. This may be useful as a diagnostic test to verify the serial interface communication between the external controller and the AFE. First, the <REGISTER READOUT ENABLE> bit (Reg0[1]) needs to be set to '1', then the user should initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be read. The data bits are don’t care. The device will output the contents (D15-D0) of the selected register on the SDOUT pin. SDOUT has a typical delay t8 of 20 ns from the falling edge of the SCLK. For lower speed SCLK, SDOUT can be latched on the rising edge of SCLK. For higher speed SCLK, for example, the SCLK period lesser than 60 ns, TI recommends latching the SDOUT at the next falling edge of SCLK. Figure 78 shows this operation (the time specifications follow the same information provided. In the readout mode, users still can access the <REGISTER READOUT ENABLE> through SDATA/SCLK/SEN. To enable serial register writes, set the <REGISTER READOUT ENABLE> bit back to '0'.

Figure 78. Serial Interface Register Read

The AFE5808A SDOUT buffer is tri-stated and will get enabled only when 0[1] (REGISTER READOUT ENABLE) is enabled. SDOUT pins from multiple AFE5808As can be tied together without any pullup resistors. Level shifter SN74AUP1T04 can be used to convert 1.8-V logic to 2.5-V/3.3-V logics if needed.

Table 3. ADC Register Map

8.6.2.1 AVERAGING_ENABLE: Address: 2[11]

When set to 1, two samples, corresponding to two consecutive channels, are averaged (channel 1 with 2, 3 with 4, 5 with 6, and 7 with 8). If both channels receive the same input, the net effect is an improvement in SNR. The averaging is performed as:

• Channel 1 + channel 2 comes out on channel 3
• Channel 3 + channel 4 comes out on channel 4
• Channel 5 + channel 6 comes out on channel 5
• Channel 7 + channel 8 comes out on channel 6

8.6.2.2 ADC_OUTPUT_FORMAT: Address: 4[3]

The ADC output, by default, is in 2’s-complement mode. Programming the ADC_OUTPUT_FORMAT bit to 1 inverts the MSB, and the output becomes straight-offset binary mode.

8.6.2.3 DIGITAL_GAIN_ENABLE: Address: 3[12]

Setting this bit to 1 applies to each channel i the corresponding gain given by DIGTAL_GAIN_CHi <15:11>. The gain is given as 0dB + 0.2dB × DIGTAL_GAIN_CHi<15:11>. For instance, if DIGTAL_GAIN_CH5<15:11> = 3, channel 5 is increased by 0.6dB gain. DIGTAL_GAIN_CHi <15:11> = 31 produces the same effect as DIGTAL_GAIN_CHi <15:11> = 30, setting the gain of channel i to 6dB.

8.6.2.4 DIGITAL_HPF_ENABLE

• CH1-4: Address 21[0]
• CH5-8: Address 33[0]

8.6.2.5 DIGITAL_HPF_FILTER_K_CHX

• CH1-4: Address 21[4:1]
• CH5-8: Address 3[4:1]

This group of registers controls the characteristics of a digital high-pass transfer function applied to the output data, following Equation 4.

Equation 4.

These digital HPF registers (one for the first four channels and one for the second group of four channels) describe the setting of K. The digital high pass filter can be used to suppress low frequency noise which commonly exists in ultrasound echo signals. The digital filter can significantly benefit near field recovery time due to T/R switch low frequency response. Table 4 shows the cut-off frequency vs K, also see Figure 58.

8.6.2.6 LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]

The low-frequency noise suppression mode is especially useful in applications where good noise performance is desired in the frequency band of 0 MHz to 1 MHz (around DC). Setting this mode shifts the low-frequency noise of the AFE5808A device to approximately Fs / 2, thereby moving the noise floor around DC to a much lower value. Register bit 1[11] is used for enabling or disabling this feature. When this feature is enabled, power consumption of the device increases by approximately 1 mW/CH.

8.6.2.7 LVDS_OUTPUT_RATE_2X: Address: 1[14]

The output data always uses a DDR format, with valid/different bits on the positive as well as the negative edges of the LVDS bit clock, DCLK. The output rate is set by default to 1X (LVDS_OUTPUT_RATE_2X = 0), where each ADC has one LVDS stream associated with it. If the sampling rate is low enough, two ADCs can share one LVDS stream, thereby lowering the power consumption devoted to the interface. The unused outputs will output zero. To avoid consumption from those outputs, no termination must not be connected to them. The distribution on the used output pairs is done in the following way:

• Channel 1 and channel 2 come out on channel 3. Channel 1 comes out first.
• Channel 3 and channel 4 come out on channel 4. Channel 3 comes out first.
• Channel 5 and channel 6 come out on channel 5. Channel 5 comes out first.
• Channel 7 and channel 8 come out on channel 6. Channel 7 comes out first.

8.6.2.8 CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]

Setting this bit to 1 enables the subtraction of the value on the corresponding OFFSET_CHx<9:0> (offset for channel i) from the ADC output. The number is specified in 2s-complement format. For example, OFFSET_CHx<9:0> = 11 1000 0000 means subtract 128. For OFFSET_CHx<9:0> = 00 0111 1111 the effect is to subtract 127. In effect, both addition and subtraction can be performed. Note that the offset is applied before the digital gain (see ADC_OUTPUT_FORMAT: Address: 4[3]). The whole data path is 2s-complement throughout internally, with digital gain being the last step. Only when ADC_OUTPUT_FORMAT = 1 (straight binary output format) is the 2s-complement word translated into offset binary at the end.

8.6.2.9 SERIALIZED_DATA_RATE: Address: 3[14:13]

8.6.2.10 TEST_PATTERN_MODES: Address: 2[15:13]

The AFE5808A device can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal ADC data output. The device may also be made to output 6 preset patterns:

1. Ramp: Setting Register 2[15:13] = 111 causes all the channels to output a repeating full-scale ramp pattern. The ramp increments from zero code to full-scale code in steps of 1 LSB every clock cycle. After hitting the full-scale code, it returns back to zero code and ramps again.
2. Zeros: The device can be programmed to output all zeros by setting Register 2[15:13] = 110;
3. Ones: The device can be programmed to output all 1s by setting Register 2[15:13] = 100;
4. Deskew Patten: When 2[15:13] = 010; this mode replaces the 14-bit ADC output with the 01010101010101 word.
5. Sync Pattern: When 2[15:13] = 001, the normal ADC output is replaced by a fixed 11111110000000 word.
6. Toggle: When 2[15:13] = 101, the normal ADC output is alternating between 1's and 0's. The start state of ADC word can be either 1's or 0's.
7. Custom Pattern: It can be enabled when 2[15:13] = 011;. Users can write the required VALUE into register bits <CUSTOM PATTERN> which is Register 5[13:0]. Then the device will output VALUE at its outputs, about 3 to 4 ADC clock cycles after the 24th rising edge of SCLK. So, the time taken to write one value is 24 SCLK clock cycles + 4 ADC clock cycles. To change the customer pattern value, users can repeat writing Register 5[13:0] with a new value. Due to the speed limit of SPI, the refresh rate of the custom pattern may not be high. For example, 128 points custom pattern will take approximately 128 × (24 SCLK clock cycles + 4 ADC clock cycles).

NOTE

Only one of the above patterns can be active at any given instant.

8.6.2.11 SYNC_PATTERN: Address: 10[8]

By enabling this bit, all channels' test pattern outputs are synchronized. When 10[8] is set as 1, the ramp patterns of all 8 channels start simultaneously.

Table 6. VCA Register Map

8.6.4.1 LNA Input Impedances Configuration (Active Termination Programmability)

Different LNA input impedances can be configured through the register 52[4:0]. By enabling and disabling the feedback resistors between LNA outputs and ACTx pins, LNA input impedance is adjustable accordingly. Table 7 describes the relationship between LNA gain and 52[4:0] settings. The input impedance settings are the same for both TGC and CW paths.

The AFE5808A device also has 4 preset active termination impedances as described in 52[7:6]. An internal decoder is used to select appropriate resistors corresponding to different LNA gain.

The input impedance of AFE can be programmed through Register 52[8:0]. Each bit of Register 52[4:0] controls one active termination resistor. The below tables indicate the nominal impedance values when individual active termination resistors are selected. More details can be found in Active Termination. Table 8 shows the corresponding impedances under different Register 52[4:0] values, while Table 9 shows the Register 52[4:0] settings under different impedances.

8.6.4.2 Programmable Gain for CW Summing Amplifier

Different gain can be configured for the CW summing amplifier through the register 54[4:0]. By enabling and disabling the feedback resistors between the summing amplifier inputs and outputs, the gain is adjustable accordingly to maximize the dynamic range of CW path. Table 10 describes the relationship between the summing amplifier gain and 54[4:0] settings.

8.6.4.3 Programmable Phase Delay for CW Mixer

Accurate CW beamforming is achieved through adjusting the phase delay of each channel. In the AFE5808A device, 16 different phase delays can be applied to each LNA output, and it meets the standard requirement of typical ultrasound beamformer, that is beamformer resolution. Table 10 describes the relationship between the phase delays and the register 55 and 56 settings.