SLOS729D October   2011  – November 2015 AFE5808A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Digital Characteristics
    7. 7.7  Switching Characteristics
    8. 7.8  Timing Requirements
    9. 7.9  Output Interface Timing
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Noise Amplifier (LNA)
      2. 8.3.2 Voltage-Controlled Attenuator
      3. 8.3.3 Programmable Gain Amplifier
      4. 8.3.4 Analog-to-Digital Converter
      5. 8.3.5 Continuous-Wave (CW) Beamformer
        1. 8.3.5.1 16 × ƒcw Mode
        2. 8.3.5.2 8 × ƒcw and 4 × ƒcw Modes
        3. 8.3.5.3 1 × ƒcw Mode
      6. 8.3.6 Equivalent Circuits
      7. 8.3.7 LVDS Output Interface Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 TGC Mode
      2. 8.4.2 CW Mode
      3. 8.4.3 TGC + CW Mode
      4. 8.4.4 Test Modes
        1. 8.4.4.1 ADC Test Modes
        2. 8.4.4.2 VCA Test Mode
      5. 8.4.5 Power Management
        1. 8.4.5.1 Power and Performance Optimization
        2. 8.4.5.2 Power Management Priority
        3. 8.4.5.3 Partial Power Up and Power Down Mode
        4. 8.4.5.4 Complete Power-Down Mode
        5. 8.4.5.5 Power Saving in CW Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Register Timing
        1. 8.5.1.1 Serial Register Write Description
        2. 8.5.1.2 Register Readout Description
    6. 8.6 Register Maps
      1. 8.6.1 ADC Register Map
      2. 8.6.2 ADC Register/Digital Processing Description
        1. 8.6.2.1  AVERAGING_ENABLE: Address: 2[11]
        2. 8.6.2.2  ADC_OUTPUT_FORMAT: Address: 4[3]
        3. 8.6.2.3  DIGITAL_GAIN_ENABLE: Address: 3[12]
        4. 8.6.2.4  DIGITAL_HPF_ENABLE
        5. 8.6.2.5  DIGITAL_HPF_FILTER_K_CHX
        6. 8.6.2.6  LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]
        7. 8.6.2.7  LVDS_OUTPUT_RATE_2X: Address: 1[14]
        8. 8.6.2.8  CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]
        9. 8.6.2.9  SERIALIZED_DATA_RATE: Address: 3[14:13]
        10. 8.6.2.10 TEST_PATTERN_MODES: Address: 2[15:13]
        11. 8.6.2.11 SYNC_PATTERN: Address: 10[8]
      3. 8.6.3 VCA Register Map
      4. 8.6.4 AFE5808A VCA Register Description
        1. 8.6.4.1 LNA Input Impedances Configuration (Active Termination Programmability)
        2. 8.6.4.2 Programmable Gain for CW Summing Amplifier
        3. 8.6.4.3 Programmable Phase Delay for CW Mixer
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LNA Configuration
          1. 9.2.2.1.1 LNA Input Coupling and Decoupling
          2. 9.2.2.1.2 LNA Noise Contribution
          3. 9.2.2.1.3 Active Termination
          4. 9.2.2.1.4 LNA Gain Switch Response
        2. 9.2.2.2 Voltage-Controlled-Attenuator
        3. 9.2.2.3 CW Operation
          1. 9.2.2.3.1 CW Summing Amplifier
          2. 9.2.2.3.2 CW Clock Selection
          3. 9.2.2.3.3 CW Supporting Circuits
        4. 9.2.2.4 ADC Operation
          1. 9.2.2.4.1 ADC Clock Configurations
          2. 9.2.2.4.2 ADC Reference Circuit
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Driving the Inputs (Analog or Digital) Beyond the Power-Supply Rails
      2. 9.3.2 Driving the Device Signal Input With an Excessively High Level Signal
      3. 9.3.3 Driving the VCNTL Signal With an Excessive Noise Source
      4. 9.3.4 Using a Clock Source With Excessive Jitter, an Excessively Long Input Clock Signal Trace, or Having Other Signals Coupled to the ADC or CW Clock Signal Trace
      5. 9.3.5 LVDS Routing Length Mismatch
      6. 9.3.6 Failure to Provide Adequate Heat Removal
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.