SLOS738E September   2012  – August 2015 AFE5809

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Digital Demodulator Electrical Characteristics
    7. 7.7  Digital Characteristics
    8. 7.8  Switching Characteristics
    9. 7.9  SPI Switching Characteristics
    10. 7.10 Output Interface Timing Requirements (14-bit)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 LNA
      2. 8.3.2 Voltage-Controlled Attenuator
      3. 8.3.3 PGA
      4. 8.3.4 ADC
      5. 8.3.5 Continuous-Wave (CW) Beamformer
        1. 8.3.5.1 16 × ƒcw Mode
        2. 8.3.5.2 8 × ƒcw and 4 × ƒcw Modes
        3. 8.3.5.3 1 × ƒcw Mode
      6. 8.3.6 Digital I/Q Demodulator
      7. 8.3.7 Equivalent Circuits
      8. 8.3.8 LVDS Output Interface Description
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Operation
        1. 8.5.1.1 ADC/VCA Serial Register Write Description
        2. 8.5.1.2 ADC/VCA Serial Register Readout Description
        3. 8.5.1.3 Digital Demodulator SPI Description
    6. 8.6 Register Maps
      1. 8.6.1 ADC and VCA Register Description
        1. 8.6.1.1 ADC Register Map
        2. 8.6.1.2 AFE5809 ADC Register/Digital Processing Description
          1. 8.6.1.2.1  AVERAGING_ENABLE: Address: 2[11]
          2. 8.6.1.2.2  ADC_OUTPUT_FORMAT: Address: 4[3]
          3. 8.6.1.2.3  ADC Reference Mode: Address 1[13] and 3[15]
          4. 8.6.1.2.4  DIGITAL_GAIN_ENABLE: Address: 3[12]
          5. 8.6.1.2.5  DIGITAL_HPF_ENABLE
          6. 8.6.1.2.6  DIGITAL_HPF_FILTER_K_CHX
          7. 8.6.1.2.7  LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]
          8. 8.6.1.2.8  LVDS_OUTPUT_RATE_2X: Address: 1[14]
          9. 8.6.1.2.9  CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]
          10. 8.6.1.2.10 SERIALIZED_DATA_RATE: Address: 3[14:13]
          11. 8.6.1.2.11 TEST_PATTERN_MODES: Address: 2[15:13]
          12. 8.6.1.2.12 SYNC_PATTERN: Address: 10[8]
        3. 8.6.1.3 VCA Register Map
        4. 8.6.1.4 VCA Register Description
          1. 8.6.1.4.1 LNA Input Impedances Configuration (Active Termination Programmability)
          2. 8.6.1.4.2 Programmable Gain for CW Summing Amplifier
          3. 8.6.1.4.3 Programmable Phase Delay for CW Mixer
      2. 8.6.2 Digital Demodulator Register Description
        1. 8.6.2.1 Profile RAM and Coefficient RAM
          1. 8.6.2.1.1 Programming the Profile RAM
          2. 8.6.2.1.2 Procedure for Configuring Next Profile Vector
          3. 8.6.2.1.3 Programming the Coefficient RAM
          4. 8.6.2.1.4 Filter Coefficent Test Mode
          5. 8.6.2.1.5 TX_SYNC and SYNC_WORD Timing
          6. 8.6.2.1.6 FIR Filter Delay versus TX_TRIG Timing
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LNA Configuration
          1. 9.2.2.1.1 LNA Input Coupling and Decoupling
          2. 9.2.2.1.2 LNA Noise Contribution
          3. 9.2.2.1.3 Active Termination
          4. 9.2.2.1.4 LNA Gain Switch Response
        2. 9.2.2.2 Voltage-Controlled Attenuator
        3. 9.2.2.3 CW Operation
          1. 9.2.2.3.1 CW Summing Amplifier
          2. 9.2.2.3.2 CW Clock Selection
          3. 9.2.2.3.3 CW Supporting Circuits
        4. 9.2.2.4 Low Frequency Support
        5. 9.2.2.5 ADC Operation
          1. 9.2.2.5.1 ADC Clock Configurations
          2. 9.2.2.5.2 ADC Reference Circuit
      3. 9.2.3 Application Curves
    3. 9.3 System Example
      1. 9.3.1 ADC Debug
      2. 9.3.2 VCA Debug
    4. 9.4 Do's and Don'ts
      1. 9.4.1 Driving the Inputs (Analog or Digital) Beyond the Power-Supply Rails
      2. 9.4.2 Driving the Device Signal Input With an Excessively High Level Signal
      3. 9.4.3 Driving the VCNTL Signal With an Excessive Noise Source
      4. 9.4.4 Using a Clock Source With Excessive Jitter, an Excessively Long Input Clock Signal Trace, or Having Other Signals Coupled to the ADC or CW Clock Signal Trace
      5. 9.4.5 LVDS Routing Length Mismatch
      6. 9.4.6 Failure to Provide Adequate Heat Removal
  10. 10Power Supply Recommendations
    1. 10.1 Power/Performance Optimization
    2. 10.2 Power Management Priority
    3. 10.3 Partial Power-Up and Power-Down Mode
    4. 10.4 Complete Power-Down Mode
    5. 10.5 Power Saving in CW Mode
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

For the Power Stage Designer see www.ti.com/filterdesigner

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

  • MicroStar BGA Packaging Reference Guide, SSYZ015
  • Clocking High-Speed Data Converters, SLYT075

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.