Figure 113 shows the suggested power-up sequencing and reset timing for the device.

A. 10 μs < t₁ < 50 ms, 10 μs < t₂ < 50 ms, –10 ms < t₃ < 10 ms, t₄ > 10 ms, t₅ > 100 ns, t₆ > 100 ns, t₇ > 10 ms, and t₈ > 100 μs. When the demodulator power DVDD_LDO1 and DVDD_LDO2 are supplied externally, it should be powered up 1ms after DVDD. LDOs for external DVDD_LDO1 and DVDD_LDO2 can be powered down if the demodualtor is not used.

B. The AVDDx and DVDD power-on sequence does not matter as long as –10 ms < t₃ < 10 ms. Similar considerations apply while shutting down the device.

Figure 113. Recommended Power-Up Sequencing and Reset Timing with Internally Generated 1.4V Demod Supply

10.1 Power/Performance Optimization

The AFE5809 device has options to adjust power consumption and meet different noise performances. This feature would be useful for portable systems operated by batteries when low power is more desired. Refer to characteristics information listed in the Electrical Characteristics as well as the Typical Characteristics.

10.2 Power Management Priority

Power management plays a critical role to extend battery life and ensure long operation time. The AFE5809 device has fast and flexible power-down and power-up control which can maximize battery life. The AFE5809 can be powered down or up through external pins or internal registers. Table 29 indicates the affected circuit blocks and priorities when the power management is invoked. The higher priority controls can overwrite the lower priority controls.

In the device, all the power-down controls are logically ORed to generate final power down for different blocks. The higher priority controls can cover the lower priority controls.

10.3 Partial Power-Up and Power-Down Mode

The partial power-up and power-down mode is also called fast power-up and power-down mode. In this mode, most amplifiers in the signal path are powered down, while the internal reference circuits remain active as well as the LVDS clock circuit, that is, the LVDS circuit still generates its frame and bit clocks.

The partial power-down function allows the AFE5809 device to wake up from a low-power state quickly. This configuration ensures that the external capacitors are discharged slowly; thus, a minimum wake-up time is needed as long as the charges on those capacitors are restored. The VCA wake-up response is typically about 2 μs or 1% of the power-down duration, whichever is larger. The longest wake-up time depends on the capacitors connected at INP and INM, because the wake-up time is the time required to recharge the capacitors to the desired operating voltages. 0.1 μF at INP and 15 nF at INM can give a wake-up time of 2.5 ms. For larger capacitors, this time will be longer. The ADC wake-up time is about 1 μs. Thus, the AFE5809 wake-up time is more dependent on the VCA wake-up time. This also assumes that the ADC clock has been running for at least 50 µs before normal operating mode resumes. The power-down time is instantaneous, less than 1 µs.

This fast wake-up response is desired for portable ultrasound applications in which the power saving is critical. The pulse repetition frequency of an ultrasound system could vary from 50 kHz to 500 Hz, while the imaging depth (that is, the active period for a receive path) varies from 10 μs to hundreds of µs. The power saving can be significant when a system’s PRF is low. In some cases, only the VCA would be powered down while the ADC keeps running normally to ensure minimal impact to FPGAs.

In the partial power-down mode, the AFE5809 device typically dissipates only 26 mW/ch, representing an 80% power reduction compared to the normal operating mode. This mode can be set using either pins (PDN_VCA and PDN_ADC) or register bits (VCA_PARTIAL_PDN and ADC_PARTIAL_PDN).

10.4 Complete Power-Down Mode

To achieve the lowest power dissipation of 0.7 mW/CH, the AFE5809 device can be placed into a complete power-down mode. This mode is controlled through the registers ADC_COMPLETE_PDN, VCA_COMPLETE_PDN, or PDN_GLOBAL pin. In the complete power-down mode, all circuits including reference circuits within the AFE5809 device are powered down, and the capacitors connected to the AFE5809 device are discharged. The wake-up time depends on the time needed to recharge these capacitors. The wake-up time depends on the time that the AFE5809 device spends in shutdown mode. 0.1 μF at INP and 15 nF at INM can give a wake-up time close to 2.5 ms.

10.5 Power Saving in CW Mode

Usually, only half the number of channels in a system are active in the CW mode. Thus, the individual channel control through ADC_PDN_CH <7:0> and VCA_PDN_CH <7:0> can power down unused channels and save power consumption greatly. Under the default register setting in CW mode, the voltage controlled attenuator, PGA, and ADC are still active. During the debug phase, both the PW and CW paths can run simultaneously. In real operation, these blocks must be powered down manually.