SBASAC1A august   2021  – july 2023 AFE439A2 , AFE539A4 , AFE639D2

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Comparator Mode
    7. 6.7  Electrical Characteristics: ADC Input
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: PWM Output
    16. 6.16 Timing Requirements: I2C Controller
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics: Voltage Output
    19. 6.19 Typical Characteristics: ADC
    20. 6.20 Typical Characteristics: Comparator
    21. 6.21 Typical Characteristics: General
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
      2. 7.4.2 Voltage Reference and DAC Transfer Function
        1. 7.4.2.1 Power-Supply as Reference
        2. 7.4.2.2 Internal Reference
        3. 7.4.2.3 External Reference
      3. 7.4.3 Comparator Mode
      4. 7.4.4 Analog-to-Digital Converter (ADC) Mode
      5. 7.4.5 Pulse-Width Modulation (PWM)
      6. 7.4.6 Proportional-Integral (PI) Control
        1. 7.4.6.1 AFE439A2 PI Control
        2. 7.4.6.2 AFE539A4 PI Control
        3. 7.4.6.3 AFE639D2 PI Control
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h)
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh)
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  STATE-MACHINE-CONFIG1 Register (address = 29h) [reset = C800h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.6.1 AFE439A2 PI Control

The AFE439A2 provides a preprogrammed PI controller state machine, as shown in Figure 7-9. ADC channel 0 is used as the input and SDA/SCLK/PWM pin is used as the output. DAC channel 1 is used as a comparator that is used to set the output of PWM output to a value specified by the FIXED-OUTPUT field. Table 7-13 lists all the input/output pin names and functions.

GUID-20230619-SS0I-654N-LGB3-7SFPMTX6MQ7L-low.svg Figure 7-7 PI Controller Architecture of AFE439A2
Table 7-5 PI Controller Pin Definition of AFE439A2
PIN FUNCTION RANGE
AIN0 ADC0 input Hi-Z: 0 V to VFS / 3
AEN Not used for PI control—connect to VDD using a pullup resistor Not applicable
AIN1 DAC1 comparator input— connect to AGND if unused for fixed output clamping See Section 7.4.3
SDA/SCLK/PWM PWM output—connect to VDD or VIO using a pullup resistor 0 V to VDD or VIO
A0/SDI/DIR Direction output—connect to VDD or VIO using a pullup resistor 0 V to VDD or VIO

The PI controller provides many configuration parameters. The following Table 7-6list describes the function of each configuration parameter:

Table 7-6 PI Controller Parameters of AFE439A2: Description
REGISTER FIELD NAME STATIC ADDRESS
SETPOINT The 8-bit set point to which the ADC input is compared to by the PI controller. The unit of this value is the same as the value at the ADC input. The PI controller minimizes the error between the set point and the sensed ADC data.
KP This 16-bit parameter is used as the proportional gain. KP is multiplied with the instantaneous error. A higher KP enables the loop to correct the error faster. However, if the external process has a fast response time, a higher KP can cause system instability.
KI This 16-bit parameter is used as inverse integral gain. KI is inverted and multiplied to the accumulated error. This parameter is important to help minimize the steady-state error under different ambient conditions of the process. A higher KI means a weaker response to the steady-state error. A smaller KI can effectively correct the steady-state error, but can also lead to bigger oscillations. The integral function is disabled when KI = 0.
MAX-OUTPUT This 7-bit value limits the maximum value of the PI controller output.
MIN-OUTPUT This 7-bit value limits the minimum value of the PI controller output.
COMMON-MODE This 7-bit value is present at the PI output when the proportional and integral outputs are zero. This parameter is important to help achieve a uniform response for all set points with fixed KP and KI settings. COMMON-MODE represents the nominal output to achieve a given set point. Therefore, for best results, use empirically measured COMMON-MODE values for every set point.
LOOP-POLARITY This 1-bit parameter provides the option to invert the phase of the PI-controller loop. This function is useful when the loop external to the device has an additional phase inversion.
FIXED-OUTPUT This 8-bit parameter is used to take the output to this predefined value based on the output of comparator channel 2. This function is useful in failure scenarios.
CMP-THRESHOLD This 8-bit parameter is used to set the threshold for comparator.
Note: An SRAM location is accessed using the SRAM-ADDR and SRAM-DATA registers. Do not access the SRAM registers when the state machine is running. The state machine can be stopped by writing to the STATE-MACHINE-CONFIG0 register. The parameters in Table 8-37 are mapped to NVM. As the digital pins in are mapped to PWM when the VREF/MODE pin is high, the PI controller parameters cannot be read during run time.
Table 7-7 PI Controller Parameters of AFE439A2: Values
REGISTER FIELD NAME SRAM ADDRESS STATIC ADDRESS LOCATION DEFAULT VALUE (16‑BIT ALIGNED)
SETPOINT 0x22[9:3] SRAM 0x0200
KP 0x23[15:0] SRAM 0x0032
KI 0x26[15:0] SRAM 0x0000
MAX-OUTPUT 0x20[15:9] SRAM 0x7E00
MIN-OUTPUT 0x21[15:9] SRAM 0x0000
COMMON-MODE 0x25[11:5] SRAM 0x0000
LOOP-POLARITY 0x27[0] SRAM 0x0000
FIXED-OUTPUT 0x27[15:9] SRAM 0x8000
CMP-THRESHOLD 0x24[15:9] SRAM 0x8000

Table 7-16 shows the default device configuration.

Table 7-8 Device Configuration for AFE439A2
REGISTER NAME ADDRESS DEFAULT VALUE
COMMON-CONFIG 0x1F 0x13F9
DAC-A-VOUT-CMP-CONFIG 0x03 0x0405
DAC-D-VOUT-CMP-CONFIG 0x15 0x0401
STATE-MACHINE-CONFIG0 0x27 0x0003

Follow these steps to configure and operate the PI controller:

  1. Stop the state machine by writing 0004h to the STATE-MACHINE-CONFIG0 register.
  2. Connect the ADC input, comparator input, and DAC output as shown in Figure 7-9.
  3. Pull the VREF/MODE pin low enable programming mode.
  4. Write 0 to the START-FUNCTION bit in the COMMON-PWM-TRIG resistor to disable PWM.
  5. Write to the COMMON-CONFIG register to enable all the DAC channels.
  6. Write to the DAC-x-VOUT-CMP-CONFIG register for respective channels to select the voltage reference and output range for each channel. Configure channels A and D as comparators.
  7. Calculate the PWM output range and configure MIN-OUTPUT and MAX-OUTPUT accordingly.
    Note: The PWM-FREQUENCY (0x21[4:0]) shares SRAM location with MIN-OUTPUT (0x21[15:9]). Therefore, both these parameters must be written together.
  8. Program the PWM frequency as per Table 7-3 together with MIN-OUTPUT.
  9. Program the configuration parameters LOOP-POLARITY, CMP-THRESHOLD, and FIXED-OUTPUT as appropriate for the system.
  10. Program the initial values of KP and KI.
  11. Maintain a table to SETPOINT versus COMMON-MODE in the host processor and program these values as required by the system.
  12. Configure the STATE-MACHINE-CONFIG0 register to start the state machine.
  13. Tune the KP and KI iteratively to achieve the best transient and steady-state response.
  14. Store the values in the NVM by writing to the NVM-PROG bit in the COMMON-TRIGGER register.
  15. Pull the VREF/MODE pin high to enable PWM output.