SLASEQ7E May   2018  – March 2019 AFE7681 , AFE7683 , AFE7684 , AFE7685 , AFE7686

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Device and Documentation Support
    1. 4.1 Device Support
      1. 4.1.1 Third-Party Products Disclaimer
    2. 4.2 Documentation Support
      1. 4.2.1 Related Documentation
    3. 4.3 Related Links
    4. 4.4 Community Resources
    5. 4.5 Trademarks
    6. 4.6 Electrostatic Discharge Caution
    7. 4.7 Export Control Notice
    8. 4.8 Glossary
  5. 5Mechanical, Packaging, and Orderable Information
    1. 5.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1.1 Features

  • 14-Bit resolution
  • Sample rate:
    • DAC: 9GSPS
    • ADC: 3GSPS
  • RF Frequency range: up to 5.2 GHz
  • Maximum RF signal bandwidth
    • Quad-channel mode (4T4R): 800 MHz (single-band); 300 MHz (dual-band)
    • Dual-channel mode (2T2R): 1200 MHz (TX)/1000 MHz (RX) (single-band); 800MHz(dual-band)
  • On-chip dual selectable DSAs per RX channel
  • Integrated TX DSA functionality
  • Digital:
    • Dual band digital up-converters (DUCs)
    • Dual Band digital down-converters (DDCs)
    • 32-Bit NCOs for DUCs/DDCs
    • Interpolation ratio: 6x, 8x, 9x, 12x, 16x, 18x, 24x, 36x
    • Decimation ratio: /2, /3, /4, /6, /8, /9, /12, /16, /18, /24, /32
    • RX/FB Dynamic switching for TDD
  • Interface:
    • 8 SerDes Transceivers up to 15Gbps
    • 16-Bit and 12-bit JESD204B transport layer formatting with 8b/10b encoding
    • Subclass 1 multi-device synchronization
  • Clock:
    • Internal PLL/VCO to generate DAC and ADC clocks
  • Package: 17mm x 17mm FC BGA, 0.8mm pitch
  • Power supplies: 1.85 V, 1.15 V, 1.0 V, –1.8 V