SLASF21 December   2022 AFE78101 , AFE88101

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Timing Diagrams
    8. 6.8  Typical Characteristics: VOUT DAC
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: Reference
    11. 6.11 Typical Characteristics: Power Supply
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Overview
        1. 7.3.1.1 DAC Resistor String
        2. 7.3.1.2 DAC Buffer Amplifier
        3. 7.3.1.3 DAC Transfer Function
        4. 7.3.1.4 DAC Gain and Offset Calibration
        5. 7.3.1.5 Programmable Slew Rate
        6. 7.3.1.6 DAC Register Structure and CLEAR State
      2. 7.3.2 Analog-to-Digital Converter (ADC) Overview
        1. 7.3.2.1 ADC Operation
        2. 7.3.2.2 ADC Custom Channel Sequencer
        3. 7.3.2.3 ADC Synchronization
        4. 7.3.2.4 ADC Offset Calibration
        5. 7.3.2.5 External Monitoring Inputs
        6. 7.3.2.6 Temperature Sensor
        7. 7.3.2.7 Self-Diagnostic Multiplexer
        8. 7.3.2.8 ADC Bypass
      3. 7.3.3 Programmable Out-of-Range Alarms
        1. 7.3.3.1 Alarm Action Configuration Register
        2. 7.3.3.2 Alarm Voltage Generator
        3. 7.3.3.3 Temperature Sensor Alarm Function
        4. 7.3.3.4 Internal Reference Alarm Function
        5. 7.3.3.5 ADC Alarm Function
        6. 7.3.3.6 Fault Detection
      4. 7.3.4 IRQ
      5. 7.3.5 Internal Reference
      6. 7.3.6 Integrated Precision Oscillator
      7. 7.3.7 One-Time Programmable (OTP) Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Power-Down Mode
      2. 7.4.2 Reset
    5. 7.5 Programming
      1. 7.5.1 Communication Setup
        1. 7.5.1.1 SPI Mode
        2. 7.5.1.2 UART Mode
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 SPI Frame Definition
        2. 7.5.2.2 SPI Read and Write
        3. 7.5.2.3 Frame Error Checking
        4. 7.5.2.4 Synchronization
      3. 7.5.3 UART
        1. 7.5.3.1 UART Break Mode (UBM)
      4. 7.5.4 Status Bits
      5. 7.5.5 Watchdog Timer
    6. 7.6 Register Maps
      1. 7.6.1 AFEx8101 Registers
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Start-Up Circuit
          2. 8.2.1.2.2 Current Loop Control
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

IRQ

The devices include an interrupt request (IRQ) to communicate the occurrence of a variety of events to the host controller. The IRQ block initiates interrupts that are reported internally in a status register, externally on the IRQ pin if the function is enabled, or on the ALARM pin if the condition is from the ALARM_STATUS register. Figure 7-15 shows the IRQ block diagram.

Figure 7-15 IRQ Block Diagram

There are two registers that can generate interrupts: GEN_STATUS and ALARM_STATUS. Each of these registers has a corresponding STATUS_MASK register. The mask register controls which of the events trigger an interrupt. Writing a 1 in the mask register masks, or disables, the event from triggering an interrupt. Writing a 0 in the mask register allows the event to trigger an IRQ. All bits are masked by default. Some status bits are sticky. Reading the corresponding register clears a sticky bit, unless the condition still exists.

The IRQ is configured through CONFIG.IRQ_LVL to be edge- or level-sensitive. Set this bit to logic 1 to enable level-sensitive functionality (default). In edge-sensitive mode, the IRQ signal is a synchronous pulse, one internal clock period wide (813 ns). In level-sensitive mode, the IRQ is set and remains set as long as the condition exists. After the IRQ condition is removed, the condition is cleared by reading the corresponding status register. Trying to clear the bit while the condition still exists does not allow the bit to be cleared if the bit is sticky.

CONFIG.IRQ_POL determines the active level of the IRQ. A logic 1 configures IRQ to be active high.

When using edge-sensitive IRQ signals, there is a clock cycle delay for synchronization and edge detection. With a 307.2-kHz clock, this delay is up to 3.26 μs. For level-sensitive mode, the delay is approximately 10 ns to 20 ns.

Most status bits have two versions within the design. The first version is an edge event that is created when the status is asserted. This signal is used to generate edge-sensitive IRQs. This edge detection prevents multiple status events from blocking one another. The second version is the sticky version of the status bit. This signal is set upon assertion of the status bit and cleared when the corresponding status register is read, as long as the status condition does not still persist. Signals GEN_IRQ and ALARM_IRQ are driven by the logical OR of the of the status bits within the corresponding register.

If a status bit is unmasked and the sticky version of that bit has been asserted, and the IRQ is level-sensitive, then an interrupt is triggered as soon as the bit is unmasked. If the IRQ is edge-sensitive then a status event must occur after the bit has been unmasked to assert an interrupt.