Subject to the timing requirements listed in the Timing Requirements, the first SCLK falling edge immediately following the falling edge of CS captures the first frame bit. Subject to the same requirements, the last SCLK falling edge before the rising edge of CS captures the last bit of the frame. Figure 7-19 shows that the SPI shift register frame is 32-bits wide, and consists of an R/W bit, followed by a 7-bit address, and a 16-bit data word. The 8-bit CRC is optional (enabled by default) and is disabled by setting CONFIG.CRC_EN = 0 (see also Section 7.5.2.3). Figure 7-20 shows that when the CRC is disabled, the frame is 24-bits wide.

For a valid frame, a full frame length of data (24 bits if CRC is disabled or 32 bits if CRC is enabled) must be transmitted before CS is brought high. If CS is brought high before the last falling SCLK edge of a full frame, then the data word is not transferred into the internal registers. If more than a full frame length of falling SCLK edges are applied before CS is brought high, then the last full frame length number of bits are used. In other words, if the number of falling SCLK edges while CS = 0 is 34, then the last 32 SCLK cycles (or 24 if CRC is disabled) are treated as the valid frame. The device internal registers are updated from the SPI shift register on the rising edge of CS. To start another serial transfer, bring CS low again. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is high impedance.