SLASF43 December 2023 AFE782H1 , AFE882H1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The AFEx82H1 have an integrated timer for generating accurate time delays, pulse width modulation or oscillation. The devices have the ability to have timing parameters from the microseconds range to hours. The timer is brought out on the CLK_OUT pin by setting CONFIG.CLKO = Fh. The timer is controlled with three registers; TIMER_CFG_0, TIMER_CFG_1, and TIMER_CFG_2.
In the first of the three registers, TIMER_CFG_0.ENABLE turns the timer function on and off. If the timer is off, then the output defaults to 0. TIMER_CFG_0.INVERT inverts the output of the timer. If the INVERT bit is set, the output defaults to 1. TIMER_CFG_0.CLK_SEL selects the clock frequency according to Table 6-8. If 2'b00 is selected, and no clock is applied, then the timer pauses if the timer has previously been enabled and counting.
CLK_SEL | Clock Frequency | Resolution | Range |
---|---|---|---|
00 | No clock | - | - |
01 | 1.2288 MHz | 814 ns | 53.3 ms |
10 | 1.200 kHz | 833 μs | 54.6 s |
11 | 1.171 Hz | 853 ms | 55,923 s |
The second timer register, TIMER_CFG_1.PERIOD sets the period of the timer. The period of the timer is PERIOD + 1 cycles of the clock period.
The last timer register, TIMER_CFG_2.SET_TIME determines when the timer output goes to 1 (INVERT = 0). This effectively defines the duty cycle of the timer. The duty cycle can be calculated as (PERIOD – SET_TIME) × clock period.