SBASA44B august   2021  – june 2023 AFE7900

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Transmitter Electrical Characteristics
    6. 5.6  RF ADC Electrical Characteristics
    7. 5.7  PLL/VCO/Clock Electrical Characteristics
    8. 5.8  Digital Electrical Characteristics
    9. 5.9  Power Supply Electrical Characteristics
    10. 5.10 Timing Requirements
    11. 5.11 Switching Characteristics
    12. 5.12 Typical Characteristics
      1. 5.12.1  RX Typical Characteristics 30 MHz and 400 MHz
      2. 5.12.2  RX Typical Characteristics at 800MHz
      3. 5.12.3  RX Typical Characteristics 1.75GHz to 1.9GHz
      4. 5.12.4  RX Typical Characteristics 2.6GHz
      5. 5.12.5  RX Typical Characteristics 3.5GHz
      6. 5.12.6  RX Typical Characteristics 4.9GHz
      7. 5.12.7  TX Typical Characteristics at 30MHz and 400MHz
      8. 5.12.8  TX Typical Characteristics at 800MHz
      9. 5.12.9  TX Typical Characteristics at 1.8GHz
      10. 5.12.10 TX Typical Characteristics at 2.6GHz
      11. 5.12.11 TX Typical Characteristics at 3.5GHz
      12. 5.12.12 TX Typical Characteristics at 4.9GHz
      13. 5.12.13 TX Typical Characteristics at 7.1GHz
      14. 5.12.14 PLL and Clock Typical Characteristics
  7. 6Device and Documentation Support
    1. 6.1 Receiving Notification of Documentation Updates
    2. 6.2 Support Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Glossary
  8. 7Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.12.1 RX Typical Characteristics 30 MHz and 400 MHz

Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 62.5 MSPS (decimate by 24x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB. Default conditions at 400 MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 125 MSPS (decimate by 12x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB.

GUID-20210422-CA0I-MFRX-ZJPT-HVQ8NZNGN93M-low.svg
Normalized to 30 MHz
Figure 5-1 RX In-Band Gain Flatness, fIN = 30 MHz
GUID-20210422-CA0I-ZQJC-ZKKR-WCDQHSKD5JHP-low.svg
Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Setting) + 1
Figure 5-3 RX Calibrated Differential Amplitude Error vs DSA Setting at 30 MHz
GUID-20210422-CA0I-KTN3-RN08-XVGVCQHGMZ0R-low.svg
Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Setting = 0) + (DSA Setting)
Figure 5-5 RX Calibrated Integrated Amplitude Error vs DSA Setting at 30 MHz
GUID-20210422-CA0I-ZGST-BPLL-DQMKPP0VSN0J-low.svg
Differential Phase Error = PhaseIN(DSA Setting – 1) – PhaseIN(DSA Setting)
Figure 5-7 RX Calibrated Differential Phase Error vs DSA Setting at 30 MHz
GUID-20210422-CA0I-QZHN-MZSW-TKQTDHHCSK3T-low.svg
With 0.8 GHz matching
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)
Figure 5-9 RX Calibrated Integrated Phase Error vs DSA Setting at 30 MHz
GUID-20210422-CA0I-QBQ8-8FGS-NHLZ45RGLRH2-low.png
AIN = -6 dBFS, fADC = 1500 MSPS, fNCO = 32. , Decimate by 24x
Figure 5-11 RX Output FFT at 5 MHz
GUID-20210422-CA0I-SXD8-H1FM-H2LKZZZC9HVD-low.png
AIN = -30 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-13 RX Output FFT at 5 MHz
GUID-20210422-CA0I-PMTS-5Q0T-8Z0DVJJDNVCL-low.png
AIN = -3 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-15 RX Output FFT at 30 MHz
GUID-20210422-CA0I-JLVT-QNH8-BNQ3QMZFNFWP-low.png
AIN = -12 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-17 RX Output FFT at 30 MHz
GUID-20210422-CA0I-7JRK-RTSG-W2ZG3SX3F5HZ-low.png
AIN = -60 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-19 RX Output FFT at 30 MHz
GUID-20210422-CA0I-LNCJ-0KNG-V8LQWGHCDBPM-low.svg
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-21 NSD vs Input Amplitude at 30 MHz with DSA = 12
GUID-20210422-CA0I-7QDD-PXSP-GVKTDBXDMMCZ-low.svg
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-23 IMD3 vs Input Amplitude at 30 MHz
GUID-20210422-CA0I-WF8M-1BDV-3GTDJFV2SJ3T-low.svg
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-25 HD2 vs Input Amplitude at 30 MHz
GUID-20210422-CA0I-LPFR-RGNS-B3KFBZ6J1R7Z-low.svg
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-27 HD3 vs Input Amplitude at 30 MHz
GUID-20210430-CA0I-Z4SH-KFDF-QB7DP4M3GLRR-low.png
Normalized to 4000 MHz
Figure 5-29 RX In-Band Gain Flatness, fIN = 400 MHz
GUID-20210430-CA0I-CGDK-CLPZ-QFTXNPTGD5PX-low.png
Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Setting) + 1
Figure 5-31 RX Calibrated Differential Amplitude Error vs DSA Setting at 400 MHz
GUID-20210430-CA0I-HTTS-WLQS-LKHTDTRVT6JK-low.png
Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Setting = 0) + (DSA Setting)
Figure 5-33 RX Calibrated Integrated Amplitude Error vs DSA Setting at 400 MHz
GUID-20210430-CA0I-XVD1-FJHD-VQWZKHS3L0NS-low.png
Differential Phase Error = PhaseIN(DSA Setting – 1) – PhaseIN(DSA Setting)
Figure 5-35 RX Calibrated Differential Phase Error vs DSA Setting at 400 MHz
GUID-20210430-CA0I-ZNDP-LRKR-JGJX2X7LWMVQ-low.png
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)
Figure 5-37 RX Calibrated Integrated Phase Error vs DSA Setting at 400 MHz
GUID-20210430-CA0I-CW3S-8R8Z-TT98QGNTNXKR-low.png
fNCO = 400MHz
Figure 5-39 RX Output FFT at 405 MHz and -6dBFS
GUID-20210430-CA0I-6CK0-HCJN-4BFVGKBJWLBM-low.png
fNCO = 400MHz
Figure 5-41 RX Output FFT at 405 MHz and -30dBFS
GUID-20210430-CA0I-THKZ-DR6M-KXVNHTDJKRPX-low.png
fOFFSET = 50MHz
Figure 5-43 NSD vs Input Amplitude at 400MHz
GUID-20210430-CA0I-FNLJ-MCVS-5WTQ3HVWTCHJ-low.png
Figure 5-45 IMD3 vs Input Amplitude at 400MHz
GUID-20210430-CA0I-16SX-XWF8-X1BMFTBGNR87-low.png
Figure 5-47 IMD3 vs Tone Spacing at 400MHz
GUID-20210430-CA0I-KF3L-BWSZ-9L4FDKQLJJKK-low.png
Figure 5-49 HD3 vs DSA Setting at 400MHz
GUID-20210422-CA0I-RLZH-5MFV-WFQXNG1PDWDX-low.svg
Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Setting) + 1
Figure 5-2 RX Uncalibrated Differential Amplitude Error vs DSA Setting at 30 MHz
GUID-20210422-CA0I-RMXJ-DV5J-ZWSRJLWN3GXS-low.svg
Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Setting = 0) + (DSA Setting)
Figure 5-4 RX Uncalibrated Integrated Amplitude Error vs DSA Setting at 30 MHz
GUID-20210422-CA0I-VQN1-RR6K-M5HGMGRG13FD-low.svg
Differential Phase Error = PhaseIN(DSA Setting – 1) – PhaseIN(DSA Setting)
Figure 5-6 RX Uncalibrated Differential Phase Error vs DSA Setting at 30 MHz
GUID-20210422-CA0I-50DG-Z6VC-QC8VQBFNKHGZ-low.svg
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)
Figure 5-8 RX Uncalibrated Integrated Phase Error vs DSA Setting at 30 MHz
GUID-20210422-CA0I-VS6H-7NJM-G3VG0PX0GVH5-low.png
AIN = -3 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-10 RX Output FFT at 5 MHz
GUID-20210422-CA0I-FLWB-1FT6-KHDCTSB6231J-low.png
AIN = -12 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-12 RX Output FFT at 5 MHz
GUID-20210422-CA0I-GJTH-JSTM-FMDD7MBVFXMW-low.png
AIN = -60 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-14 RX Output FFT at 5 MHz
GUID-20210422-CA0I-KPGM-56P7-RRHTWXXBXCVB-low.png
AIN = -6 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-16 RX Output FFT at 30 MHz
GUID-20210422-CA0I-0NPP-6XPM-KGVXG1MVMDWZ-low.png
AIN = -30 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-18 RX Output FFT at 30 MHz
GUID-20210422-CA0I-RFVM-NH9C-Z6SBJHLNNKQ7-low.svg
fADC = 1500MSPS, fNCO = 32.13MHz, Decimate by 24x
Figure 5-20 NSD vs Input Amplitude at 30 MHz with DSA = 0 and 3dB
GUID-20210422-CA0I-LHQZ-V1QN-TC1WTNRNFR2H-low.svg
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-22 NSD vs DSA Attenuation at 30 MHz
GUID-20210422-CA0I-HS8Z-8TQQ-DXV8NHW4SDNX-low.svg
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-24 IMD3 vs DSA Setting at 30 MHz
GUID-20210422-CA0I-LVSG-PLHQ-CS807XRPF7RB-low.svg
fADC = 1500 MSPS, fNCO = 32. , Decimate by 24x
Figure 5-26 HD2 vs DSA Setting at 30 MHz
GUID-20210422-CA0I-6KXS-3ZLV-SP17DXMGHRZP-low.svg
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
Figure 5-28 HD3 vs DSA Setting at 30 MHz
GUID-20210430-CA0I-J4VN-JNJD-KQNC4N6LXDLB-low.png
Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Setting) + 1
Figure 5-30 RX Uncalibrated Differential Amplitude Error vs DSA Setting at 30 MHz
GUID-20210430-CA0I-NSN2-9NZT-GZ149Z8B2CSF-low.png
Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Setting = 0) + (DSA Setting)
Figure 5-32 RX Uncalibrated Integrated Amplitude Error vs DSA Setting at 400 MHz
GUID-20210430-CA0I-PTSD-NFVX-GL5XDNR2TCZC-low.png
Differential Phase Error = PhaseIN(DSA Setting – 1) – PhaseIN(DSA Setting)
Figure 5-34 RX Uncalibrated Differential Phase Error vs DSA Setting at 400 MHz
GUID-20210430-CA0I-MCLQ-49BR-LQVBRMBK97L3-low.png
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)
Figure 5-36 RX Uncalibrated Integrated Phase Error vs DSA Setting at 400 MHz
GUID-20210430-CA0I-SFGZ-TBZR-ZX28XVTSNGLC-low.png
fNCO = 400MHz
Figure 5-38 RX Output FFT at 405 MHz and -3dBFS
GUID-20210430-CA0I-NSS7-7S2W-PTS9LF3LC6MF-low.png
fNCO = 400MHz
Figure 5-40 RX Output FFT at 405 MHz and -12dBFS
GUID-20210430-CA0I-WBWQ-HJHH-FSH7CPNP2PGL-low.png
fNCO = 400MHz
Figure 5-42 RX Output FFT at 405 MHz and -60dBFS
GUID-20210430-CA0I-HSWK-MCMQ-HHD3XNXV2G1C-low.png
fOFFSET = 50MHz
Figure 5-44 NSD vs DSA Setting at 400MHz
GUID-20210430-CA0I-GND6-T7WB-PBBXMMPRZP8N-low.png
Figure 5-46 IMD3 vs DSA Setting at 400MHz
GUID-20210430-CA0I-LKBG-JC4C-RW7TM3NPFD1J-low.png
Figure 5-48 HD3 vs Input Amplitude at 400MHz