SBASAO5A april   2023  – june 2023 AFE7901

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Description (continued)
  6. 5Revision History
  7. 6Pin Configuration and Functions
  8. 7Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information AFE79xx
    5. 7.5  Transmitter Electrical Characteristics
    6. 7.6  RF ADC Electrical Characteristics
    7. 7.7  PLL/VCO/Clock Electrical Characteristics
    8. 7.8  Digital Electrical Characteristics
    9. 7.9  Power Supply Electrical Characteristics
    10. 7.10 Timing Requirements
    11. 7.11 Switching Characteristics
    12. 7.12 Typical Characteristics
      1. 7.12.1  RX Typical Characteristics 30 MHz and 400 MHz
      2. 7.12.2  RX Typical Characteristics at 800 MHz
      3. 7.12.3  RX Typical Characteristics 1.75 GHz to 1.9 GHz
      4. 7.12.4  RX Typical Characteristics 2.6 GHz
      5. 7.12.5  RX Typical Characteristics 3.5 GHz
      6. 7.12.6  RX Typical Characteristics 4.9 GHz
      7. 7.12.7  RX Typical Characteristics 6.8 GHz
      8. 7.12.8  TX Typical Characteristics at 30 MHz and 400 MHz
      9. 7.12.9  TX Typical Characteristics at 800 MHz
      10. 7.12.10 TX Typical Characteristics at 1.8 GHz
      11. 7.12.11 TX Typical Characteristics at 2.6 GHz
      12. 7.12.12 TX Typical Characteristics at 3.5 GHz
      13. 7.12.13 TX Typical Characteristics at 4.9 GHz
      14. 7.12.14 TX Typical Characteristics at 7.1 GHz
      15. 7.12.15 PLL and Clock Typical Characteristics
  9. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-20220831-SS0I-ZDFB-WPGL-FQJTNHRCK09M-low.svgFigure 6-1 FCBGA Package, 400-Pin
(Top View)
Table 6-1 Pin Functions
BALL NAMEBALL NUMBERTYPE(1)DESCRIPTION
RF INTERFACES
NCA15, A16, Y15, Y16IDo not connect.
1RXIN–A11IReceiver Channel 1 RF input: negative terminal.

Unused RX inputs can be left open.

1RXIN+A12IReceiver Channel 1 RF input: positive terminal. Unused RX inputs can be left open.
2RXIN–A8IReceiver Channel 2 RF input: negative terminal. Unused RX inputs can be left open.
2RXIN+A7IReceiver Channel 2 RF input: positive terminal. Unused RX inputs can be left open.
3RXIN–Y11IReceiver Channel 3 RF input: negative terminal.
3RXIN+Y12IReceiver Channel 3 RF input: positive terminal. Unused RX inputs can be left open.
4RXIN–Y8IReceiver Channel 4 RF input: negative terminal. Unused RX inputs can be left open.
4RXIN+Y7IReceiver Channel 4 RF input: positive terminal. Unused RX inputs can be left open.
1TXOUT–F20OTransmitter Channel 1 RF output: negative terminal. Connect to 1.8 V when not used.
1TXOUT+G20OTransmitter Channel 1 RF output: positive terminal. Connect to 1.8 V when not used.
2TXOUT–C20OTransmitter Channel 2 RF output: negative terminal. Connect to 1.8 V when not used.
2TXOUT+B20OTransmitter Channel 2 RF output: positive terminal. Connect to 1.8 V when not used.
3TXOUT–R20OTransmitter Channel 3 RF output: negative terminal. Connect to 1.8 V when not used.
3TXOUT+P20OTransmitter Channel 3 RF output: positive terminal. Connect to 1.8 V when not used.
4TXOUT–V20OTransmitter Channel 4 RF output: negative terminal. Connect to 1.8 V when not used.
4TXOUT+W20OTransmitter Channel 4 RF output: positive terminal. Connect to 1.8 V when not used.
DIFFERENTIAL CLOCKS INPUTS
REFCLK–L17IReference Clock Inputs: negative terminal
REFCLK+K17IReference Clock Inputs: positive terminal
SYSREF–L19ISYSREEF inputs: negative terminals
SYSREF+K19ISYSREEF inputs: positive terminals
SerDes CML INTERFACE
1SRX–A2ICML SerDes Interface Lane 1 input: negative terminal.

Unused Serdes inputs can be left open.

1SRX+A3ICML SerDes Interface Lane 1 input: positive terminal.

Unused Serdes inputs can be left open.

2SRX–C1ICML SerDes Interface Lane 2 input: negative terminal.

Unused Serdes inputs can be left open.

2SRX+B1ICML SerDes Interface Lane 2 input: positive terminal.

Unused Serdes inputs can be left open.

3SRX–F1ICML SerDes Interface Lane 3 input: negative terminal
3SRX+E1ICML SerDes Interface Lane 3 input: positive terminal.

Unused Serdes inputs can be left open.

4SRX–J1ICML SerDes Interface Lane 4 input: negative terminal
4SRX+H1ICML SerDes Interface Lane 4 input: positive terminal
5SRX–M1ICML SerDes Interface Lane 5 input: negative terminal.

Unused Serdes inputs can be left open.

5SRX+N1ICML SerDes Interface Lane 5 input: positive terminal
6SRX–R1ICML SerDes Interface Lane 6 input: negative terminal
6SRX+T1ICML SerDes Interface Lane 6 input: positive terminal.

Unused Serdes inputs can be left open.

7SRX–V1ICML SerDes Interface Lane 7 input: negative terminal
7SRX+W1ICML SerDes Interface Lane 7 input: positive terminal.

Unused Serdes inputs can be left open.

8SRX–Y2ICML SerDes Interface Lane 8 input: negative terminal
8SRX+Y3ICML SerDes Interface Lane 8 input: positive terminal.

Unused Serdes inputs can be left open.

1STX–C3OCML SerDes Interface Lane 1 output: negative terminal.

Unused Serdes outputs can be left open.

1STX+C4OCML SerDes Interface Lane 1 output: positive terminal.

Unused Serdes outputs can be left open.

2STX–E3OCML SerDes Interface Lane 2 output: negative terminal.

Unused Serdes outputs can be left open.

2STX+E4OCML SerDes Interface Lane 2 output: positive terminal.

Unused Serdes outputs can be left open.

3STX–G4OCML SerDes Interface Lane 3 output: negative terminal.

Unused Serdes outputs can be left open.

3STX+G3OCML SerDes Interface Lane 3 output: positive terminal.

Unused Serdes outputs can be left open.

4STX–J4OCML SerDes Interface Lane 4 output: negative terminal.

Unused Serdes outputs can be left open.

4STX+J3OCML SerDes Interface Lane 4 output: positive terminal.

Unused Serdes outputs can be left open.

5STX–M4OCML SerDes Interface Lane 5 output: negative terminal.

Unused Serdes outputs can be left open.

5STX+M3OCML SerDes Interface Lane 5 output: positive terminal.

Unused Serdes outputs can be left open.

6STX–P4OCML SerDes Interface Lane 6 output: negative terminal.

Unused Serdes outputs can be left open.

6STX+P3OCML SerDes Interface Lane 6 output: positive terminal.

Unused Serdes outputs can be left open.

7STX–T3OCML SerDes Interface Lane 7 output: negative terminal.

Unused Serdes outputs can be left open.

7STX+T4OCML SerDes Interface Lane 7 output: positive terminal.

Unused Serdes outputs can be left open.

8STX–V3OCML SerDes Interface Lane 8 output: negative terminal.

Unused Serdes outputs can be left open.

8STX+V4OCML SerDes Interface Lane 8 output: positive terminal.

Unused Serdes outputs can be left open.

GPIO FUNCTIONS
GBL_0_GPIO13V6I/OGPIO.
GBL_1_FBTDD2R6I/ODefault location of FB TDD2 input signal.
GBL_2_FSPICLKCU5I/ODefault and recommended location of FSPI C clock (FSPI for factory use only, available as generic GPIO).
GBL_3_GPIO14R5I/OGPIO.
GBL_4_RXDLNBT5I/ODefault location of RX channel D AGC LNA Bypass output signal.
GBL_5_GPIO15N10I/OGPIO.
GBL_6_GPIO16P10I/OGPIO.
GBL_7_SYNCB_OUT1+N9I/ODefault location of JESD Sync\ 1 output differential positive terminal.
GBL_8_SYNCB_IN1+N8I/ODefault location of JESD Sync\ 1 input differential positive terminal.
GBL_9_SYNCB_OUT1–P9I/ODefault location of JESD Sync\ 1 output differential negative terminal.
GBL_10_GPIO17T8I/OGPIO.
GBL_11_GPIO18T7I/OGPIO.
GBL_12_FSPICLKDP7I/ODefault and recommended location of FSPI D clock (FSPI for factory use only, available as generic GPIO).
GBL_13_GPIO19P8I/OGPIO.
GBL_14_FSPIDDR7I/ODefault and recommended location of FSPI D data (FSPI for factory use only, available as generic GPIO).
GBL_15_FSPIDCP6I/ODefault and recommended location of FSPI C clock (FSPI for factory use only, available as generic GPIO).
GBL_16_RXCLNBT6I/ODefault location of RX channel C AGC LNA Bypass output signal.
GBL_17_SYNCB_IN1–N7I/ODefault location of JESD Sync\ 1 input differential negative terminal.
GBL_18_TXTDD2V5I/ODefault location of TX TDD2 input signal.
GBL_19_GPIO20U6I/OGPIO.
GBR_0_GPIO4C6I/OGPIO.
GBR_1_GPIO5F6I/OGPIO.
GBR_2_RXALNBD5I/ODefault location of RX channel A AGC LNA Bypass output signal.
GBR_3_FSPICLKBF5I/ODefault and recommended location of FSPI B clock (FSPI for factory use only, available as generic GPIO).
GBR_4_GPIO6E5I/OGPIO.
GBR_5_FSPIDBH10I/ODefault and recommended location of FSPI B data (FSPI for factory use only, available as generic GPIO).
GBR_6_RXBLNBG10I/ODefault location of RX channel B AGC LNA Bypass output signal.
GBR_7_SYNCB_OUT0+H9I/ODefault location of JESD Sync\ 0 output differential positive terminal.
GBR_8_SYNCB_IN0+H8I/ODefault location of JESD Sync\ 0 input differential positive terminal.
GBR_9_SYNCB_OUT0–G9I/ODefault location of JESD Sync\ 0 output differential negative terminal.
GBR_10_FSPICLKAE8I/ODefault location of FSPI A clock (FSPI for factory use only, available as generic GPIO).
GBR_11_RXTDD1E7I/ODefault location of RX TDD1 input signal.
GBR_12_GPIO7G7I/OGPIO.
GBR_13_GPIO8G8I/OGPIO.
GBR_14_FSPIDAF7I/ODefault and recommended location of FSPI A clock (FSPI for factory use only, available as generic GPIO).
GBR_15_GPIO9G6I/OGPIO.
GBR_16_GPIO10E6I/OGPIO.
GBR_17_SYNCB_IN0–H7I/ODefault location of JESD Sync\ 0 input differential negative terminal.
GBR_18_GPIO11C5I/OGPIO.
GBR_19_GPIO12D6I/OGPIO.
GTL_0_GPIO2N13I/OGPIO.
GTL_1_SLEEPP14I/ODefault location of Sleep input signal.
GTL_2_ALARM2N15I/ODefault location of Alarm 2 output signal.
GTL_3_AUX0M15I/OGPIO or auxiliary low-speed ADC input 0
GTL_4_SPIACLKP15I/OFixed Location of SPI A Clock.
GTL_5_SPIASENR14I/OFixed Location of SPI A Send Enable.
GTL_6_RXTDD2R15I/ODefault location of RX TDD2 input signal.
GTL_7_ALARM1N16I/ODefault location of Alarm 1 output signal.
GTL_8_AUX1L14I/OGPIO or auxiliary low-speed ADC input 1.
GTL_9_AUX2M14I/OGPIO or auxiliary low-speed ADC input 2.
GTL_10_BIST0P11I/OFixed Location for BIST0 Function. Set low when using JTAG, set high for normal operation.
GTL_11_AUX3P13I/OGPIO or auxiliary low-speed ADC input 3.
GTL_12_BIST1P12I/OFixed Location for BIST1 Function. Set high when using JTAG, set low for normal operation.
GTL_13_AUX4N12I/OGPIO or auxiliary low-speed ADC input 4.
GTL_14_AUX5N11I/OGPIO or auxiliary low-speed ADC input 5.
GTL_15_GPIO3P16I/OGPIO.
GTL_17_SPIASDION14I/OFixed Location of SPI A Serial Data Input (3- and 4-wire mode) or Output (3 wire mode only).
GTL_18_SPIASDOR16I/OFixed Location of SPI A Serial Data Output in 4-wire mode.
GTR_0_RXGSWAPG13I/ODefault location of RX gain swap input.
GTR_1_GPIO1H12I/OGPIO.
GTR_2_SPIB2CLKJ14I/ODefault and recommended location of SPI B2 clock.
GTR_3_TXTDD1H15I/ODefault location of TX TDD1 input signal.
GTR_4_TCLKH14I/OFixed location for JTAG Test Clock.
GTR_5_TDOF14I/OFixed location for JTAG Test Data Out.
GTR_6_SPIB2_SDIOH13I/ODefault and recommended location of SPI B2 serial data input/output.
GTR_7_SPIB2SENF16I/ODefault and recommended location of SPI B2 enable input.
GTR_8_FBTDD1K14I/ODefault location of FB TDD1 input signal.
GTR_9_SPIB2SDOJ15I/ODefault and recommended location of SPI B2 serial data output (4-wire mode)
GTR_10_TMSG11I/OFixed location for JTAG Test Mode Select.
GTR_11_SPIB1_SDOG12I/ODefault and recommended location of SPI B1 serial data output (4-wire mode).
GTR_12_SPIB_SDIOH11I/ODefault and recommended location of SPI B1 serial data input/output.
GTR_13_TRSTG15I/OFixed location for JTAG Test Reset. Must be pulled low when the JTAG port is not used.
GTR_14_SPIB1SENH16I/ODefault and recommended location of SPI B1 enable input.
GTR_15_RESETZF15I/OFixed Location for reset function. Chip Reset to default register settings.
GTR_17_SPIB1CLKG16I/ODefault and recommended location of SPI B1 clock.
GTR_18_TDIG14I/OFixed location for JTAG Test Data Input.
POWER SUPPLIES
DVDDK2, K5, K6, K7, K8, K9, K10, K11, K12, K13, L2, L5, L6, L7, L8, L9, L10, L11, L12, L13—0.9-V digital power supply
VDD1P2FBD14, D15, D16, E15, U14, U15, U16, T15—1.2-V supply for FB ADCs.
VDD1P8FBC15, C16, V15, V16—1.8-V supply for FB ADC.
VDD1P8FBCLKA14, A17, Y17, Y14—1.8-V supply for FB ADC clock.
VDD1P2PLLCLKREFK20, K18, L18—1.2-V supply for PLL.
VDDPLL1P2FBCMLL15—1.2-V supply for PLL clock distribution to FB ADC.
VDDPLL1P2RXCMLK15—1.2-V supply for clock distribution to RX ADC.
VDD1P8PLLK16, L16—1.8-V supply for PLL.
VDD1P8PLLVCOL20—1.8-V supply for PLL/VCO. This is a sensitive net and requires extra care in layout.
VDD1P2RXA10, A13, E11, E12, E13, E14,F11, F12, F13, R11, R12, R13, T11, T12, T13, T14, Y10, Y13—1.2-V supply for RX ADCs.
VDD1P8RXC9, C10, C11, D9, D10, D11, E9, E10, F8, F9, F10, R8, R9, R10, T9, T10, U9, U10, U11, V9, V10, V11—1.8-V supply for RX ADCs.
VDD1P8RXCLKA6, A9, Y6, Y9—1.8-V supply for RX ADC clocks.
VDD1P2TXENCD17, U17—1.2-V supply for DAC encoder.
VDD1P2TXCLKA20, D20, U20, Y20—1.2-V supply for DAC clock.
VDD1P8TXE20, H20, N20, T20—1.8-V supply for DAC.
VDD1P8TXDACG17, H17, N17, P17—1.8-V supply for DAC.
VDD1P8GPIOH6, N6—1.8-V supply for GPIO.
VDDA1P8F3, F4, H3, H4, R3, R4, N3, N4—SerDes analog 1.8-V power supply.
VDDT0P9D3, D4, U3, U4—SerDes digital 0.9-V power supply.
GROUNDS
DGNDJ5, J6, J7, J8, J9, J10, J11, J12, M5, M6, M7, M8, M9, M10, M11, M12—Digital core ground
VSSGPIOH5, N5—GPIO ground.
VSSFBB14, B15, B16, B17, C14, V14, W14, W15, W16, W17—Ground for FB ADC supply.
VSSFBCLKA18, B18, W18, Y18—Ground for FB ADC 1.8-V clock supply.
GND_ESDD7, D8, J13, M13, U7, U8—Ground for ESD protection circuits.
VSSRXB7, B8, B10, B11, B12, C12, D12, B13, C13, D13, W7, W8, W10, W11, W13, U12, V12, W12, U13, V13—Ground for RX ADC.
VSSRXCLKA5, B5, B6, B9, C7, C8, W5, W6, W9, Y5, V7, V8—Ground for RX ADC clocks.
VSSTXB19, C17, C18, C19, D18, E18, E19, F17, F18, F19, G18, G19, H18, H19, J20, M20, N18, N19, P18, P19, R17, R18, R19, T18, T19, U18, V17, V18, V19, W19—Ground for TX DAC.
VSSTXENCE16, E17, T16, T17—Ground for TX DAC encoder.
VSSTXCLKA19, D19, U19, Y19—Ground for TX DAC clock.
VSSPLLM19—Ground for PLL.
VSSPLLFBCMLJ16, M16—Ground for FB ADC clock.
VSSPLLCLKREFJ18, M18—Ground for CLKREF PLL.
VSSPLLRXCMLJ17, M17—Ground for RX ADC clock.
VSSTA1, A4, B2, B3, B4, C2, D1, D2, E2, F2, G1, G2, H2, J2, K1, K4, L1, L4, M2, N2, P1, P2, R2, T2, U1, U2, V2, W2, W3, W4, Y1, Y4—SerDes ground.
OTHERS
IFORCEG5—Reserved for TI use only. Do not connect.
PLL_LDOUTJ19—Connect with 100-nF capacitor to GND
SerDes_AMUX1K3—Analog test pin for SerDes lane 1-4, can be left floating
SerDes_AMUX2L3—Analog test pin for SerDes lane 5-8, can be left floating
VSENSEP5—Process test: sense voltage (TI use only). Do not connect.
(1) Signal Types: I = Input, O = Output, I/O = Input or Output.