SBASAN3 may   2023 AFE7951

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Description (continued)
  6. 5Revision History
  7. 6Pin Configuration and Functions
  8. 7Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information AFE79xx
    5. 7.5  Transmitter Electrical Characteristics
    6. 7.6  RF ADC Electrical Characteristics
    7. 7.7  PLL/VCO/Clock Electrical Characteristics
    8. 7.8  Digital Electrical Characteristics
    9. 7.9  Power Supply Electrical Characteristics
    10. 7.10 Timing Requirements
    11. 7.11 Switching Characteristics
    12. 7.12 Typical Characteristics
      1. 7.12.1  TX Typical Characteristics 800 MHz
      2. 7.12.2  TX Typical Characteristics at 1.8 GHz
      3. 7.12.3  TX Typical Characteristics at 2.6 GHz
      4. 7.12.4  TX Typical Characteristics at 3.5 GHz
      5. 7.12.5  TX Typical Characteristics at 4.9 GHz
      6. 7.12.6  TX Typical Characteristics at 8.1 GHz
      7. 7.12.7  TX Typical Characteristics at 9.6 GHz
      8. 7.12.8  RX Typical Characteristics at 800 MHz
      9. 7.12.9  RX Typical Characteristics at 1.75-1.9 GHz
      10. 7.12.10 RX Typical Characteristics at 2.6 GHz
      11. 7.12.11 RX Typical Characteristics at 3.5 GHz
      12. 7.12.12 RX Typical Characteristics at 4.9 GHz
      13. 7.12.13 RX Typical Characteristics at 8.1 GHz
      14. 7.12.14 RX Typical Characteristics at 9.6 GHz
      15. 7.12.15 PLL and Clock Typical Characteristics
  9. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Description (continued)

Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of signal bandwidth of up to 400 MHz per RX channel.