SLASF43 December   2023 AFE782H1 , AFE882H1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Timing Diagrams
    8. 5.8  Typical Characteristics: VOUT DAC
    9. 5.9  Typical Characteristics: ADC
    10. 5.10 Typical Characteristics: Reference
    11. 5.11 Typical Characteristics: HART Modem
    12. 5.12 Typical Characteristics: Power Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Buffer Amplifier
        3. 6.3.1.3 DAC Transfer Function
        4. 6.3.1.4 DAC Gain and Offset Calibration
        5. 6.3.1.5 Programmable Slew Rate
        6. 6.3.1.6 DAC Register Structure and CLEAR State
      2. 6.3.2  Analog-to-Digital Converter (ADC) Overview
        1. 6.3.2.1 ADC Operation
        2. 6.3.2.2 ADC Custom Channel Sequencer
        3. 6.3.2.3 ADC Synchronization
        4. 6.3.2.4 ADC Offset Calibration
        5. 6.3.2.5 External Monitoring Inputs
        6. 6.3.2.6 Temperature Sensor
        7. 6.3.2.7 Self-Diagnostic Multiplexer
        8. 6.3.2.8 ADC Bypass
      3. 6.3.3  Programmable Out-of-Range Alarms
        1. 6.3.3.1 Alarm-Based Interrupts
        2. 6.3.3.2 Alarm Action Configuration Register
        3. 6.3.3.3 Alarm Voltage Generator
        4. 6.3.3.4 Temperature Sensor Alarm Function
        5. 6.3.3.5 Internal Reference Alarm Function
        6. 6.3.3.6 ADC Alarm Function
        7. 6.3.3.7 Fault Detection
      4. 6.3.4  IRQ
      5. 6.3.5  HART Interface
        1. 6.3.5.1  FIFO Buffers
          1. 6.3.5.1.1 FIFO Buffer Access
          2. 6.3.5.1.2 FIFO Buffer Flags
        2. 6.3.5.2  HART Modulator
        3. 6.3.5.3  HART Demodulator
        4. 6.3.5.4  HART Modem Modes
          1. 6.3.5.4.1 Half-Duplex Mode
          2. 6.3.5.4.2 Full-Duplex Mode
        5. 6.3.5.5  HART Modulation and Demodulation Arbitration
          1. 6.3.5.5.1 HART Receive Mode
          2. 6.3.5.5.2 HART Transmit Mode
        6. 6.3.5.6  HART Modulator Timing and Preamble Requirements
        7. 6.3.5.7  HART Demodulator Timing and Preamble Requirements
        8. 6.3.5.8  IRQ Configuration for HART Communication
        9. 6.3.5.9  HART Communication Using the SPI
        10. 6.3.5.10 HART Communication Using UART
        11. 6.3.5.11 Memory Built-In Self-Test (MBIST)
      6. 6.3.6  Internal Reference
      7. 6.3.7  Integrated Precision Oscillator
      8. 6.3.8  Precision Oscillator Diagnostics
      9. 6.3.9  One-Time Programmable (OTP) Memory
      10. 6.3.10 GPIO
      11. 6.3.11 Timer
      12. 6.3.12 Unique Chip Identifier (ID)
      13. 6.3.13 Scratch Pad Register
    4. 6.4 Device Functional Modes
      1. 6.4.1 DAC Power-Down Mode
      2. 6.4.2 Register Built-In Self-Test (RBIST)
      3. 6.4.3 Reset
    5. 6.5 Programming
      1. 6.5.1 Communication Setup
        1. 6.5.1.1 SPI Mode
        2. 6.5.1.2 UART Mode
        3. 6.5.1.3 SPI Plus UART Mode
        4. 6.5.1.4 HART Functionality Setup Options
      2. 6.5.2 GPIO Programming
      3. 6.5.3 Serial Peripheral Interface (SPI)
        1. 6.5.3.1 SPI Frame Definition
        2. 6.5.3.2 SPI Read and Write
        3. 6.5.3.3 Frame Error Checking
        4. 6.5.3.4 Synchronization
      4. 6.5.4 UART Interface
        1. 6.5.4.1 UART Break Mode (UBM)
          1. 6.5.4.1.1 Interface With FIFO Buffers and Register Map
      5. 6.5.5 Status Bits
      6. 6.5.6 Watchdog Timer
  8. 7 Register Maps
    1. 7.1 AFEx82H1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Current Loop Control
          2. 8.2.1.2.2 HART Connections
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RRU|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.3.2 SPI Read and Write

The SDI input bit is latched on the SCLK falling edge. The SDI pin receives right-justified data. At the rising edge of CS, the right-most (last) bits are evaluated as a frame. Extra clock cycles (exceeding frame length) during the frame begin to output on SDO the SDI data delayed by one frame length.

A read operation is started when R/W bit is 1. The data word input for SDI is ignored in the read command frame. Send the subsequent read or write command frame into SDI to clock out the data of the addressed register on SDO. If no other read or write commands are needed, then issue a NOP command to retrieve the requested data. The read register value is output most significant bit first on SDO on successive edges (rising or falling based on CONFIG.FSDO setting) of SCLK.

A write operation starts when R/W bit is 0. The SDO output to a write command, delivered in the next frame, contains status bits, data described in Table 6-13, and if the CRC is enabled, an 8-bit CRC for the output frame.

Table 6-12 Command Functions
COMMAND BIT SDI INPUT DATA WORD SDO RESPONSE DATA WORD(1)
Write (R/W = 0) Data to be written (16b) 0x0000
Read (R/W = 1) Ignored(2) Register output data (16b)
(1) Response data portion in next frame output.
(2) The input bits are included in the calculation for CRC, if enabled (see AFEx82H1 16-Bit and 14-Bit, Low-Power DACs With Internal HART® Modem, Voltage Reference, and Diagnostic ADC for Industrial Applications AFEx82H1 16-Bit and 14-Bit, Low-Power Digital-to-Analog Converters (DACs) With Internal HART® Modem, Voltage Reference, and Diagnostic ADC for Process Control AFEx82H1 16-Bit and 14-Bit, Low-Power Digital-to-Analog Converters (DACs) With Internal HART® Modem, Voltage Reference, and Diagnostic ADC for Process Control Features Features Applications Applications Description Description Table of Contents Table of Contents Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics Timing Requirements Timing Requirements Timing Diagrams Timing Diagrams Typical Characteristics: VOUT DAC Typical Characteristics: VOUT DAC Typical Characteristics: ADC Typical Characteristics: ADC Typical Characteristics: Reference Typical Characteristics: Reference Typical Characteristics: HART Modem Typical Characteristics: HART Modem Typical Characteristics: Power Supply Typical Characteristics: Power Supply Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description Digital-to-Analog Converter (DAC) Overview Digital-to-Analog Converter (DAC) Overview DAC Resistor String DAC Resistor String DAC Buffer Amplifier DAC Buffer Amplifier DAC Transfer Function DAC Transfer Function DAC Gain and Offset Calibration DAC Gain and Offset Calibration Programmable Slew Rate Programmable Slew Rate DAC Register Structure and CLEAR State DAC Register Structure and CLEAR State Analog-to-Digital Converter (ADC) Overview Analog-to-Digital Converter (ADC) Overview ADC Operation ADC Operation ADC Custom Channel Sequencer ADC Custom Channel Sequencer ADC Synchronization ADC Synchronization ADC Offset Calibration ADC Offset Calibration External Monitoring Inputs External Monitoring Inputs Temperature Sensor Temperature Sensor Self-Diagnostic Multiplexer Self-Diagnostic Multiplexer ADC Bypass ADC Bypass Programmable Out-of-Range Alarms Programmable Out-of-Range Alarms Alarm-Based Interrupts Alarm-Based Interrupts Alarm Action Configuration Register Alarm Action Configuration Register Alarm Voltage Generator Alarm Voltage Generator Temperature Sensor Alarm Function Temperature Sensor Alarm Function Internal Reference Alarm Function Internal Reference Alarm Function ADC Alarm Function ADC Alarm Function Fault Detection Fault Detection IRQ IRQ HART Interface HART Interface FIFO Buffers FIFO Buffers FIFO Buffer Access FIFO Buffer Access FIFO Buffer Flags FIFO Buffer Flags HART Modulator HART Modulator HART Demodulator HART Demodulator HART Modem Modes HART Modem Modes Half-Duplex Mode Half-Duplex Mode Full-Duplex Mode Full-Duplex Mode HART Modulation and Demodulation Arbitration HART Modulation and Demodulation Arbitration HART Receive Mode HART Receive Mode HART Transmit Mode HART Transmit Mode HART Modulator Timing and Preamble Requirements HART Modulator Timing and Preamble Requirements HART Demodulator Timing and Preamble Requirements HART Demodulator Timing and Preamble Requirements IRQ Configuration for HART Communication IRQ Configuration for HART Communication HART Communication Using the SPI HART Communication Using the SPI HART Communication Using UART HART Communication Using UART Memory Built-In Self-Test (MBIST) Memory Built-In Self-Test (MBIST) Internal Reference Internal Reference Integrated Precision Oscillator Integrated Precision Oscillator Precision Oscillator Diagnostics Precision Oscillator Diagnostics One-Time Programmable (OTP) Memory One-Time Programmable (OTP) Memory GPIO GPIO Timer Timer Unique Chip Identifier (ID) Unique Chip Identifier (ID) Scratch Pad Register Scratch Pad Register Device Functional Modes Device Functional Modes DAC Power-Down Mode DAC Power-Down Mode Register Built-In Self-Test (RBIST) Register Built-In Self-Test (RBIST) Reset Reset Programming Programming Communication Setup Communication Setup SPI Mode SPI Mode UART Mode UART Mode SPI Plus UART Mode SPI Plus UART Mode HART Functionality Setup Options HART Functionality Setup Options GPIO Programming GPIO Programming Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) SPI Frame Definition SPI Frame Definition SPI Read and Write SPI Read and Write Frame Error Checking Frame Error Checking Synchronization Synchronization UART Interface UART Interface UART Break Mode (UBM) UART Break Mode (UBM) Interface With FIFO Buffers and Register Map Interface With FIFO Buffers and Register Map Status Bits Status Bits Watchdog Timer Watchdog Timer Register Maps Register Maps AFEx82H1 Registers AFEx82H1 Registers Application and Implementation Application and Implementation Application Information Application Information Multichannel Configuration Multichannel Configuration Typical Application Typical Application 4-mA to 20-mA Current Transmitter 4-mA to 20-mA Current Transmitter Design Requirements Design Requirements Detailed Design Procedure Detailed Design Procedure Current Loop Control Current Loop Control HART Connections HART Connections Input Protection and Rectification Input Protection and Rectification System Current Budget System Current Budget Application Curves Application Curves Initialization Setup Initialization Setup Power Supply Recommendations Power Supply Recommendations Layout Layout Layout Guidelines Layout Guidelines Layout Example Layout Example Device and Documentation Support Device and Documentation Support Documentation Support Documentation Support Related Documentation Related Documentation Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History Mechanical, Packaging, and Orderable Information Mechanical, Packaging, and Orderable Information IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER AFEx82H1 16-Bit and 14-Bit, Low-Power Digital-to-Analog Converters (DACs) With Internal HART® Modem, Voltage Reference, and Diagnostic ADC for Process Control AFEx82H1 16-Bit and 14-Bit, Low-Power Digital-to-Analog Converters (DACs) With Internal HART® Modem, Voltage Reference, and Diagnostic ADC for Process ControlAFEx82H1 Features Functional Safety-Capable Documentation available to aid functional safety system design Low quiescent current: 180 µA (typical) HART-compliant physical layer modem Programmable amplitude of TX signals RX demodulator and band-pass filter 16-bit or 14-bit monotonic high-performance DAC DAC output range: 0 V to 2.5 V Digital DAC slew-rate control 4-LSB INL at 16 bits 0.07% FSR (max) TUE from –40°C to +125°C 12-bit 3.84-kSPS ADC for advanced diagnostics Integrated 1.25-V reference at 10 ppm/°C (max) Internal 1.2288-MHz oscillator with clock output Digital interface Serial peripheral interface (SPI): Shared bus for both DAC and HART Universal asynchronous receiver-transmitter (UART): Shared bus for both DAC and HART Both: SPI for DAC and UART for HART Fault detection: CRC bit error checking, windowed watchdog timer, diagnostic ADC Wide operating temperature: –55°C to +125°C Features Functional Safety-Capable Documentation available to aid functional safety system design Low quiescent current: 180 µA (typical) HART-compliant physical layer modem Programmable amplitude of TX signals RX demodulator and band-pass filter 16-bit or 14-bit monotonic high-performance DAC DAC output range: 0 V to 2.5 V Digital DAC slew-rate control 4-LSB INL at 16 bits 0.07% FSR (max) TUE from –40°C to +125°C 12-bit 3.84-kSPS ADC for advanced diagnostics Integrated 1.25-V reference at 10 ppm/°C (max) Internal 1.2288-MHz oscillator with clock output Digital interface Serial peripheral interface (SPI): Shared bus for both DAC and HART Universal asynchronous receiver-transmitter (UART): Shared bus for both DAC and HART Both: SPI for DAC and UART for HART Fault detection: CRC bit error checking, windowed watchdog timer, diagnostic ADC Wide operating temperature: –55°C to +125°C Functional Safety-Capable Documentation available to aid functional safety system design Low quiescent current: 180 µA (typical) HART-compliant physical layer modem Programmable amplitude of TX signals RX demodulator and band-pass filter 16-bit or 14-bit monotonic high-performance DAC DAC output range: 0 V to 2.5 V Digital DAC slew-rate control 4-LSB INL at 16 bits 0.07% FSR (max) TUE from –40°C to +125°C 12-bit 3.84-kSPS ADC for advanced diagnostics Integrated 1.25-V reference at 10 ppm/°C (max) Internal 1.2288-MHz oscillator with clock output Digital interface Serial peripheral interface (SPI): Shared bus for both DAC and HART Universal asynchronous receiver-transmitter (UART): Shared bus for both DAC and HART Both: SPI for DAC and UART for HART Fault detection: CRC bit error checking, windowed watchdog timer, diagnostic ADC Wide operating temperature: –55°C to +125°C Functional Safety-Capable Documentation available to aid functional safety system design Low quiescent current: 180 µA (typical) HART-compliant physical layer modem Programmable amplitude of TX signals RX demodulator and band-pass filter 16-bit or 14-bit monotonic high-performance DAC DAC output range: 0 V to 2.5 V Digital DAC slew-rate control 4-LSB INL at 16 bits 0.07% FSR (max) TUE from –40°C to +125°C 12-bit 3.84-kSPS ADC for advanced diagnostics Integrated 1.25-V reference at 10 ppm/°C (max) Internal 1.2288-MHz oscillator with clock output Digital interface Serial peripheral interface (SPI): Shared bus for both DAC and HART Universal asynchronous receiver-transmitter (UART): Shared bus for both DAC and HART Both: SPI for DAC and UART for HART Fault detection: CRC bit error checking, windowed watchdog timer, diagnostic ADC Wide operating temperature: –55°C to +125°C Functional Safety-Capable Documentation available to aid functional safety system design Functional Safety-Capable Documentation available to aid functional safety system design Documentation available to aid functional safety system design Documentation available to aid functional safety system designLow quiescent current: 180 µA (typical) HART-compliant physical layer modem Programmable amplitude of TX signals RX demodulator and band-pass filter HART Programmable amplitude of TX signals RX demodulator and band-pass filter Programmable amplitude of TX signalsRX demodulator and band-pass filter16-bit or 14-bit monotonic high-performance DAC DAC output range: 0 V to 2.5 V Digital DAC slew-rate control 4-LSB INL at 16 bits 0.07% FSR (max) TUE from –40°C to +125°C DAC output range: 0 V to 2.5 V Digital DAC slew-rate control 4-LSB INL at 16 bits 0.07% FSR (max) TUE from –40°C to +125°C DAC output range: 0 V to 2.5 VDigital DAC slew-rate control4-LSB INL at 16 bits0.07% FSR (max) TUE from –40°C to +125°C12-bit 3.84-kSPS ADC for advanced diagnosticsIntegrated 1.25-V reference at 10 ppm/°C (max)Internal 1.2288-MHz oscillator with clock outputDigital interface Serial peripheral interface (SPI): Shared bus for both DAC and HART Universal asynchronous receiver-transmitter (UART): Shared bus for both DAC and HART Both: SPI for DAC and UART for HART Serial peripheral interface (SPI): Shared bus for both DAC and HART Universal asynchronous receiver-transmitter (UART): Shared bus for both DAC and HART Both: SPI for DAC and UART for HART Serial peripheral interface (SPI): Shared bus for both DAC and HARTUniversal asynchronous receiver-transmitter (UART): Shared bus for both DAC and HARTBoth: SPI for DAC and UART for HARTFault detection: CRC bit error checking, windowed watchdog timer, diagnostic ADCWide operating temperature: –55°C to +125°C Applications Process control and industrial automation PLC or DCS I/O modules 3-wire and 4-wire transmitters 4-mA to 20-mA loop-powered applications Applications Process control and industrial automation PLC or DCS I/O modules 3-wire and 4-wire transmitters 4-mA to 20-mA loop-powered applications Process control and industrial automation PLC or DCS I/O modules 3-wire and 4-wire transmitters 4-mA to 20-mA loop-powered applications Process control and industrial automation PLC or DCS I/O modules 3-wire and 4-wire transmitters 4-mA to 20-mA loop-powered applications Process control and industrial automation Process control and industrial automationPLC or DCS I/O modules3-wire and 4-wire transmitters4-mA to 20-mA loop-powered applications Description The 16-bit AFE882H1 and 14-bit AFE782H1 (AFEx82H1) are highly-integrated, high-accuracy, extremely low-power DACs with voltage-outputs designed for HART-enabled process control and industrial automation applications. The AFEx82H1 devices include most of the components required to design a 4‑mA to 20‑mA, 3‑wire or 4-wire sensor transmitter or analog output module. In addition to the highly accurate DAC, these devices include a HART®-compliant FSK modem, 10-ppm/°C voltage reference, and diagnostic analog-to-digital converter (ADC). To accommodate intrinsic and functional safety concerns, external voltage-to-current conversion and power-regulation are required. The internal diagnostic ADC is multiplexed to several internal nodes that enable an automatic self-health check. This check is capable of detecting errors or malfunctions of the internal bias sources, power regulator, voltage reference, DAC output, die temperature, and optional external voltage source. If any fault is detected from the diagnostic ADC, CRC frame-error checking, or windowed watchdog timer, the devices can optionally issue an interrupt, enter a user-specified fail-safe state, or both. Device Information PART NUMBER RESOLUTION PACKAGE#GUID-2DABB303-E959-492C-A7EB-0EF84B9109DE/DEVINFONOTE AFE782H1 14-bit RRU (UQFN, 24) 4.00 mm × 4.00 mm AFE882H1 16-bit For more information, see . Functional Block Diagram Description The 16-bit AFE882H1 and 14-bit AFE782H1 (AFEx82H1) are highly-integrated, high-accuracy, extremely low-power DACs with voltage-outputs designed for HART-enabled process control and industrial automation applications. The AFEx82H1 devices include most of the components required to design a 4‑mA to 20‑mA, 3‑wire or 4-wire sensor transmitter or analog output module. In addition to the highly accurate DAC, these devices include a HART®-compliant FSK modem, 10-ppm/°C voltage reference, and diagnostic analog-to-digital converter (ADC). To accommodate intrinsic and functional safety concerns, external voltage-to-current conversion and power-regulation are required. The internal diagnostic ADC is multiplexed to several internal nodes that enable an automatic self-health check. This check is capable of detecting errors or malfunctions of the internal bias sources, power regulator, voltage reference, DAC output, die temperature, and optional external voltage source. If any fault is detected from the diagnostic ADC, CRC frame-error checking, or windowed watchdog timer, the devices can optionally issue an interrupt, enter a user-specified fail-safe state, or both. Device Information PART NUMBER RESOLUTION PACKAGE#GUID-2DABB303-E959-492C-A7EB-0EF84B9109DE/DEVINFONOTE AFE782H1 14-bit RRU (UQFN, 24) 4.00 mm × 4.00 mm AFE882H1 16-bit For more information, see . Functional Block Diagram The 16-bit AFE882H1 and 14-bit AFE782H1 (AFEx82H1) are highly-integrated, high-accuracy, extremely low-power DACs with voltage-outputs designed for HART-enabled process control and industrial automation applications. The AFEx82H1 devices include most of the components required to design a 4‑mA to 20‑mA, 3‑wire or 4-wire sensor transmitter or analog output module. In addition to the highly accurate DAC, these devices include a HART®-compliant FSK modem, 10-ppm/°C voltage reference, and diagnostic analog-to-digital converter (ADC). To accommodate intrinsic and functional safety concerns, external voltage-to-current conversion and power-regulation are required. The internal diagnostic ADC is multiplexed to several internal nodes that enable an automatic self-health check. This check is capable of detecting errors or malfunctions of the internal bias sources, power regulator, voltage reference, DAC output, die temperature, and optional external voltage source. If any fault is detected from the diagnostic ADC, CRC frame-error checking, or windowed watchdog timer, the devices can optionally issue an interrupt, enter a user-specified fail-safe state, or both. Device Information PART NUMBER RESOLUTION PACKAGE#GUID-2DABB303-E959-492C-A7EB-0EF84B9109DE/DEVINFONOTE AFE782H1 14-bit RRU (UQFN, 24) 4.00 mm × 4.00 mm AFE882H1 16-bit For more information, see . Functional Block Diagram The 16-bit AFE882H1 and 14-bit AFE782H1 (AFEx82H1) are highly-integrated, high-accuracy, extremely low-power DACs with voltage-outputs designed for HART-enabled process control and industrial automation applications.AFE882H1AFE782H1AFEx82H1The AFEx82H1 devices include most of the components required to design a 4‑mA to 20‑mA, 3‑wire or 4-wire sensor transmitter or analog output module. In addition to the highly accurate DAC, these devices include a HART®-compliant FSK modem, 10-ppm/°C voltage reference, and diagnostic analog-to-digital converter (ADC). To accommodate intrinsic and functional safety concerns, external voltage-to-current conversion and power-regulation are required.AFEx82H1®The internal diagnostic ADC is multiplexed to several internal nodes that enable an automatic self-health check. This check is capable of detecting errors or malfunctions of the internal bias sources, power regulator, voltage reference, DAC output, die temperature, and optional external voltage source. If any fault is detected from the diagnostic ADC, CRC frame-error checking, or windowed watchdog timer, the devices can optionally issue an interrupt, enter a user-specified fail-safe state, or both. Device Information PART NUMBER RESOLUTION PACKAGE#GUID-2DABB303-E959-492C-A7EB-0EF84B9109DE/DEVINFONOTE AFE782H1 14-bit RRU (UQFN, 24) 4.00 mm × 4.00 mm AFE882H1 16-bit Device Information PART NUMBER RESOLUTION PACKAGE#GUID-2DABB303-E959-492C-A7EB-0EF84B9109DE/DEVINFONOTE AFE782H1 14-bit RRU (UQFN, 24) 4.00 mm × 4.00 mm AFE882H1 16-bit PART NUMBER RESOLUTION PACKAGE#GUID-2DABB303-E959-492C-A7EB-0EF84B9109DE/DEVINFONOTE PART NUMBER RESOLUTION PACKAGE#GUID-2DABB303-E959-492C-A7EB-0EF84B9109DE/DEVINFONOTE PART NUMBERRESOLUTIONPACKAGE#GUID-2DABB303-E959-492C-A7EB-0EF84B9109DE/DEVINFONOTE #GUID-2DABB303-E959-492C-A7EB-0EF84B9109DE/DEVINFONOTE AFE782H1 14-bit RRU (UQFN, 24) 4.00 mm × 4.00 mm AFE882H1 16-bit AFE782H1 14-bit RRU (UQFN, 24) 4.00 mm × 4.00 mm AFE782H1 AFE782H114-bitRRU (UQFN, 24) 4.00 mm × 4.00 mm AFE882H1 16-bit AFE882H1 AFE882H116-bit For more information, see . For more information, see . Functional Block Diagram Functional Block Diagram Table of Contents yes Table of Contents yes yes yes Pin Configuration and Functions RRU Package, 24-pin UQFN (Top View) Pin Functions PIN TYPE#GUID-D302D845-F45E-4C27-8F2F-E85DFFD5A624/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. AIN0 15 AI ADC input voltage. The input range is 0 V to 2 × VREF. ALARM 24 DO Alarm notification pin, open drain, active low. When alarm condition is asserted, this pin is held to logic low; otherwise, this pin is in a high-impedance state (Hi-Z). GND 14 P Digital and analog ground. Ground reference point for all circuitry on the device. GPIO0/ CLK_OUT 11 DO/DI General-purpose input/output (GPIO) pin. Can be configured as a clock output for the 1.2288-MHz internal clock or as a timer. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO1/ CD 3 DO/DI General-purpose input/output (GPIO) pin. Configured as a carrier detect output at power up. A logic high on this pin indicates a valid carrier is present. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO2/ UARTOUT 2 DO/DI General-purpose input/output (GPIO) pin. Configured as UART data output at power up. This pin can be configured to function as IRQ pin in SPI only mode. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO3/ UARTIN 1 DI/DO General-purpose input/output (GPIO) pin. Configured as UART data input at power up. Connect to IOVDD or logic high if not used. An external pullup or pulldown resistor is required. GPIO4/ SDO 9 DO/DI General-purpose input/output (GPIO) pin. Can be configured as an SPI data output in SPI mode. Data are output on the rising edge of SCLK when CS is low. Interrupt request (IRQ) pin in the UART break mode (UBM). The output is in Hi-Z at power up and must be enabled in the CONFIG register. An external pullup or pulldown resistor is required. GPIO5/ SDI 8 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI data input at power up. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. SDI is a Schmitt-trigger logic input. An external pullup or pulldown resistor is required. GPIO6/ CS 10 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI chip-select input at power up. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in Hi-Z and data on SDI are ignored. An external pullup or pulldown resistor is required. IOVDD 12 P Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interfaces. MOD_OUT 23 AO FSK output sinusoid. Maximum supported parallel load capacitance is 2 nF. POL_SEL/ AIN1 16 DI/AI ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to 2 × VREF. Otherwise, this pin acts as ALMV_POL, which sets the polarity of the VOUT alarm voltage. PVDD 17 P Power supply for the internal low-dropout regulator (LDO), ADC input and VOUT DAC output. REF_EN 5 DI Internal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is required at the VREFIO pin. REF_GND 20 P GND reference for VREFIO pin. RESET 6 DI Reset pin, active low. Logic low on this pin turns off the internal oscillator and resets the device. Logic high returns the device to normal operation. Do not leave any digital pins floating. RTS 4 DI Request to send pin. A logic high on this pin enables the demodulator and disables the modulator. A logic low on this pin enables the modulator and disables the demodulator. Do not leave any digital pins floating. RX_IN 21 AI HART FSK input if no external filter is used; otherwise, no connect. RX_INF 22 AI HART FSK input if using the external band-pass filter. If using the internal band-pass filter by connecting the HART FSK to RX_IN, then connect 680-pF capacitor to this pin. SCLK 7 DI SPI clock. Data are transferred at rates up to 12.5 MHz. SCLK is a Schmitt-trigger logic input. Connect to GND or logic low if not used. Do not leave any digital pins floating. VDD 13 P/AO Internal low voltage LDO output. When 2.7 V to 5.5 V on PVDD pin is provided, the internal LDO is enabled. Connect a 1-μF to 10-μF capacitor on this pin. VOUT 18 AO DAC output voltage. VREFIO 19 AI/AO When the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this case, a load capacitance of 70 nF to 130 nF is required for stability. When disabled, this pin is the external 1.25‑V reference input. AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power. Pin Configuration and Functions RRU Package, 24-pin UQFN (Top View) Pin Functions PIN TYPE#GUID-D302D845-F45E-4C27-8F2F-E85DFFD5A624/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. AIN0 15 AI ADC input voltage. The input range is 0 V to 2 × VREF. ALARM 24 DO Alarm notification pin, open drain, active low. When alarm condition is asserted, this pin is held to logic low; otherwise, this pin is in a high-impedance state (Hi-Z). GND 14 P Digital and analog ground. Ground reference point for all circuitry on the device. GPIO0/ CLK_OUT 11 DO/DI General-purpose input/output (GPIO) pin. Can be configured as a clock output for the 1.2288-MHz internal clock or as a timer. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO1/ CD 3 DO/DI General-purpose input/output (GPIO) pin. Configured as a carrier detect output at power up. A logic high on this pin indicates a valid carrier is present. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO2/ UARTOUT 2 DO/DI General-purpose input/output (GPIO) pin. Configured as UART data output at power up. This pin can be configured to function as IRQ pin in SPI only mode. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO3/ UARTIN 1 DI/DO General-purpose input/output (GPIO) pin. Configured as UART data input at power up. Connect to IOVDD or logic high if not used. An external pullup or pulldown resistor is required. GPIO4/ SDO 9 DO/DI General-purpose input/output (GPIO) pin. Can be configured as an SPI data output in SPI mode. Data are output on the rising edge of SCLK when CS is low. Interrupt request (IRQ) pin in the UART break mode (UBM). The output is in Hi-Z at power up and must be enabled in the CONFIG register. An external pullup or pulldown resistor is required. GPIO5/ SDI 8 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI data input at power up. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. SDI is a Schmitt-trigger logic input. An external pullup or pulldown resistor is required. GPIO6/ CS 10 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI chip-select input at power up. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in Hi-Z and data on SDI are ignored. An external pullup or pulldown resistor is required. IOVDD 12 P Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interfaces. MOD_OUT 23 AO FSK output sinusoid. Maximum supported parallel load capacitance is 2 nF. POL_SEL/ AIN1 16 DI/AI ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to 2 × VREF. Otherwise, this pin acts as ALMV_POL, which sets the polarity of the VOUT alarm voltage. PVDD 17 P Power supply for the internal low-dropout regulator (LDO), ADC input and VOUT DAC output. REF_EN 5 DI Internal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is required at the VREFIO pin. REF_GND 20 P GND reference for VREFIO pin. RESET 6 DI Reset pin, active low. Logic low on this pin turns off the internal oscillator and resets the device. Logic high returns the device to normal operation. Do not leave any digital pins floating. RTS 4 DI Request to send pin. A logic high on this pin enables the demodulator and disables the modulator. A logic low on this pin enables the modulator and disables the demodulator. Do not leave any digital pins floating. RX_IN 21 AI HART FSK input if no external filter is used; otherwise, no connect. RX_INF 22 AI HART FSK input if using the external band-pass filter. If using the internal band-pass filter by connecting the HART FSK to RX_IN, then connect 680-pF capacitor to this pin. SCLK 7 DI SPI clock. Data are transferred at rates up to 12.5 MHz. SCLK is a Schmitt-trigger logic input. Connect to GND or logic low if not used. Do not leave any digital pins floating. VDD 13 P/AO Internal low voltage LDO output. When 2.7 V to 5.5 V on PVDD pin is provided, the internal LDO is enabled. Connect a 1-μF to 10-μF capacitor on this pin. VOUT 18 AO DAC output voltage. VREFIO 19 AI/AO When the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this case, a load capacitance of 70 nF to 130 nF is required for stability. When disabled, this pin is the external 1.25‑V reference input. AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power. RRU Package, 24-pin UQFN (Top View) Pin Functions PIN TYPE#GUID-D302D845-F45E-4C27-8F2F-E85DFFD5A624/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. AIN0 15 AI ADC input voltage. The input range is 0 V to 2 × VREF. ALARM 24 DO Alarm notification pin, open drain, active low. When alarm condition is asserted, this pin is held to logic low; otherwise, this pin is in a high-impedance state (Hi-Z). GND 14 P Digital and analog ground. Ground reference point for all circuitry on the device. GPIO0/ CLK_OUT 11 DO/DI General-purpose input/output (GPIO) pin. Can be configured as a clock output for the 1.2288-MHz internal clock or as a timer. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO1/ CD 3 DO/DI General-purpose input/output (GPIO) pin. Configured as a carrier detect output at power up. A logic high on this pin indicates a valid carrier is present. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO2/ UARTOUT 2 DO/DI General-purpose input/output (GPIO) pin. Configured as UART data output at power up. This pin can be configured to function as IRQ pin in SPI only mode. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO3/ UARTIN 1 DI/DO General-purpose input/output (GPIO) pin. Configured as UART data input at power up. Connect to IOVDD or logic high if not used. An external pullup or pulldown resistor is required. GPIO4/ SDO 9 DO/DI General-purpose input/output (GPIO) pin. Can be configured as an SPI data output in SPI mode. Data are output on the rising edge of SCLK when CS is low. Interrupt request (IRQ) pin in the UART break mode (UBM). The output is in Hi-Z at power up and must be enabled in the CONFIG register. An external pullup or pulldown resistor is required. GPIO5/ SDI 8 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI data input at power up. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. SDI is a Schmitt-trigger logic input. An external pullup or pulldown resistor is required. GPIO6/ CS 10 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI chip-select input at power up. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in Hi-Z and data on SDI are ignored. An external pullup or pulldown resistor is required. IOVDD 12 P Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interfaces. MOD_OUT 23 AO FSK output sinusoid. Maximum supported parallel load capacitance is 2 nF. POL_SEL/ AIN1 16 DI/AI ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to 2 × VREF. Otherwise, this pin acts as ALMV_POL, which sets the polarity of the VOUT alarm voltage. PVDD 17 P Power supply for the internal low-dropout regulator (LDO), ADC input and VOUT DAC output. REF_EN 5 DI Internal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is required at the VREFIO pin. REF_GND 20 P GND reference for VREFIO pin. RESET 6 DI Reset pin, active low. Logic low on this pin turns off the internal oscillator and resets the device. Logic high returns the device to normal operation. Do not leave any digital pins floating. RTS 4 DI Request to send pin. A logic high on this pin enables the demodulator and disables the modulator. A logic low on this pin enables the modulator and disables the demodulator. Do not leave any digital pins floating. RX_IN 21 AI HART FSK input if no external filter is used; otherwise, no connect. RX_INF 22 AI HART FSK input if using the external band-pass filter. If using the internal band-pass filter by connecting the HART FSK to RX_IN, then connect 680-pF capacitor to this pin. SCLK 7 DI SPI clock. Data are transferred at rates up to 12.5 MHz. SCLK is a Schmitt-trigger logic input. Connect to GND or logic low if not used. Do not leave any digital pins floating. VDD 13 P/AO Internal low voltage LDO output. When 2.7 V to 5.5 V on PVDD pin is provided, the internal LDO is enabled. Connect a 1-μF to 10-μF capacitor on this pin. VOUT 18 AO DAC output voltage. VREFIO 19 AI/AO When the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this case, a load capacitance of 70 nF to 130 nF is required for stability. When disabled, this pin is the external 1.25‑V reference input. AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power. RRU Package, 24-pin UQFN (Top View) RRU Package, 24-pin UQFN (Top View) Pin Functions PIN TYPE#GUID-D302D845-F45E-4C27-8F2F-E85DFFD5A624/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. AIN0 15 AI ADC input voltage. The input range is 0 V to 2 × VREF. ALARM 24 DO Alarm notification pin, open drain, active low. When alarm condition is asserted, this pin is held to logic low; otherwise, this pin is in a high-impedance state (Hi-Z). GND 14 P Digital and analog ground. Ground reference point for all circuitry on the device. GPIO0/ CLK_OUT 11 DO/DI General-purpose input/output (GPIO) pin. Can be configured as a clock output for the 1.2288-MHz internal clock or as a timer. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO1/ CD 3 DO/DI General-purpose input/output (GPIO) pin. Configured as a carrier detect output at power up. A logic high on this pin indicates a valid carrier is present. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO2/ UARTOUT 2 DO/DI General-purpose input/output (GPIO) pin. Configured as UART data output at power up. This pin can be configured to function as IRQ pin in SPI only mode. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO3/ UARTIN 1 DI/DO General-purpose input/output (GPIO) pin. Configured as UART data input at power up. Connect to IOVDD or logic high if not used. An external pullup or pulldown resistor is required. GPIO4/ SDO 9 DO/DI General-purpose input/output (GPIO) pin. Can be configured as an SPI data output in SPI mode. Data are output on the rising edge of SCLK when CS is low. Interrupt request (IRQ) pin in the UART break mode (UBM). The output is in Hi-Z at power up and must be enabled in the CONFIG register. An external pullup or pulldown resistor is required. GPIO5/ SDI 8 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI data input at power up. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. SDI is a Schmitt-trigger logic input. An external pullup or pulldown resistor is required. GPIO6/ CS 10 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI chip-select input at power up. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in Hi-Z and data on SDI are ignored. An external pullup or pulldown resistor is required. IOVDD 12 P Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interfaces. MOD_OUT 23 AO FSK output sinusoid. Maximum supported parallel load capacitance is 2 nF. POL_SEL/ AIN1 16 DI/AI ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to 2 × VREF. Otherwise, this pin acts as ALMV_POL, which sets the polarity of the VOUT alarm voltage. PVDD 17 P Power supply for the internal low-dropout regulator (LDO), ADC input and VOUT DAC output. REF_EN 5 DI Internal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is required at the VREFIO pin. REF_GND 20 P GND reference for VREFIO pin. RESET 6 DI Reset pin, active low. Logic low on this pin turns off the internal oscillator and resets the device. Logic high returns the device to normal operation. Do not leave any digital pins floating. RTS 4 DI Request to send pin. A logic high on this pin enables the demodulator and disables the modulator. A logic low on this pin enables the modulator and disables the demodulator. Do not leave any digital pins floating. RX_IN 21 AI HART FSK input if no external filter is used; otherwise, no connect. RX_INF 22 AI HART FSK input if using the external band-pass filter. If using the internal band-pass filter by connecting the HART FSK to RX_IN, then connect 680-pF capacitor to this pin. SCLK 7 DI SPI clock. Data are transferred at rates up to 12.5 MHz. SCLK is a Schmitt-trigger logic input. Connect to GND or logic low if not used. Do not leave any digital pins floating. VDD 13 P/AO Internal low voltage LDO output. When 2.7 V to 5.5 V on PVDD pin is provided, the internal LDO is enabled. Connect a 1-μF to 10-μF capacitor on this pin. VOUT 18 AO DAC output voltage. VREFIO 19 AI/AO When the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this case, a load capacitance of 70 nF to 130 nF is required for stability. When disabled, this pin is the external 1.25‑V reference input. Pin Functions PIN TYPE#GUID-D302D845-F45E-4C27-8F2F-E85DFFD5A624/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. AIN0 15 AI ADC input voltage. The input range is 0 V to 2 × VREF. ALARM 24 DO Alarm notification pin, open drain, active low. When alarm condition is asserted, this pin is held to logic low; otherwise, this pin is in a high-impedance state (Hi-Z). GND 14 P Digital and analog ground. Ground reference point for all circuitry on the device. GPIO0/ CLK_OUT 11 DO/DI General-purpose input/output (GPIO) pin. Can be configured as a clock output for the 1.2288-MHz internal clock or as a timer. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO1/ CD 3 DO/DI General-purpose input/output (GPIO) pin. Configured as a carrier detect output at power up. A logic high on this pin indicates a valid carrier is present. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO2/ UARTOUT 2 DO/DI General-purpose input/output (GPIO) pin. Configured as UART data output at power up. This pin can be configured to function as IRQ pin in SPI only mode. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO3/ UARTIN 1 DI/DO General-purpose input/output (GPIO) pin. Configured as UART data input at power up. Connect to IOVDD or logic high if not used. An external pullup or pulldown resistor is required. GPIO4/ SDO 9 DO/DI General-purpose input/output (GPIO) pin. Can be configured as an SPI data output in SPI mode. Data are output on the rising edge of SCLK when CS is low. Interrupt request (IRQ) pin in the UART break mode (UBM). The output is in Hi-Z at power up and must be enabled in the CONFIG register. An external pullup or pulldown resistor is required. GPIO5/ SDI 8 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI data input at power up. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. SDI is a Schmitt-trigger logic input. An external pullup or pulldown resistor is required. GPIO6/ CS 10 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI chip-select input at power up. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in Hi-Z and data on SDI are ignored. An external pullup or pulldown resistor is required. IOVDD 12 P Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interfaces. MOD_OUT 23 AO FSK output sinusoid. Maximum supported parallel load capacitance is 2 nF. POL_SEL/ AIN1 16 DI/AI ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to 2 × VREF. Otherwise, this pin acts as ALMV_POL, which sets the polarity of the VOUT alarm voltage. PVDD 17 P Power supply for the internal low-dropout regulator (LDO), ADC input and VOUT DAC output. REF_EN 5 DI Internal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is required at the VREFIO pin. REF_GND 20 P GND reference for VREFIO pin. RESET 6 DI Reset pin, active low. Logic low on this pin turns off the internal oscillator and resets the device. Logic high returns the device to normal operation. Do not leave any digital pins floating. RTS 4 DI Request to send pin. A logic high on this pin enables the demodulator and disables the modulator. A logic low on this pin enables the modulator and disables the demodulator. Do not leave any digital pins floating. RX_IN 21 AI HART FSK input if no external filter is used; otherwise, no connect. RX_INF 22 AI HART FSK input if using the external band-pass filter. If using the internal band-pass filter by connecting the HART FSK to RX_IN, then connect 680-pF capacitor to this pin. SCLK 7 DI SPI clock. Data are transferred at rates up to 12.5 MHz. SCLK is a Schmitt-trigger logic input. Connect to GND or logic low if not used. Do not leave any digital pins floating. VDD 13 P/AO Internal low voltage LDO output. When 2.7 V to 5.5 V on PVDD pin is provided, the internal LDO is enabled. Connect a 1-μF to 10-μF capacitor on this pin. VOUT 18 AO DAC output voltage. VREFIO 19 AI/AO When the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this case, a load capacitance of 70 nF to 130 nF is required for stability. When disabled, this pin is the external 1.25‑V reference input. PIN TYPE#GUID-D302D845-F45E-4C27-8F2F-E85DFFD5A624/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION NAME NO. PIN TYPE#GUID-D302D845-F45E-4C27-8F2F-E85DFFD5A624/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 DESCRIPTION PINTYPE#GUID-D302D845-F45E-4C27-8F2F-E85DFFD5A624/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1 #GUID-D302D845-F45E-4C27-8F2F-E85DFFD5A624/GUID-5271DA12-D57C-46F2-8BEA-2C409D73BCF1DESCRIPTION NAME NO. NAMENO. AIN0 15 AI ADC input voltage. The input range is 0 V to 2 × VREF. ALARM 24 DO Alarm notification pin, open drain, active low. When alarm condition is asserted, this pin is held to logic low; otherwise, this pin is in a high-impedance state (Hi-Z). GND 14 P Digital and analog ground. Ground reference point for all circuitry on the device. GPIO0/ CLK_OUT 11 DO/DI General-purpose input/output (GPIO) pin. Can be configured as a clock output for the 1.2288-MHz internal clock or as a timer. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO1/ CD 3 DO/DI General-purpose input/output (GPIO) pin. Configured as a carrier detect output at power up. A logic high on this pin indicates a valid carrier is present. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO2/ UARTOUT 2 DO/DI General-purpose input/output (GPIO) pin. Configured as UART data output at power up. This pin can be configured to function as IRQ pin in SPI only mode. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO3/ UARTIN 1 DI/DO General-purpose input/output (GPIO) pin. Configured as UART data input at power up. Connect to IOVDD or logic high if not used. An external pullup or pulldown resistor is required. GPIO4/ SDO 9 DO/DI General-purpose input/output (GPIO) pin. Can be configured as an SPI data output in SPI mode. Data are output on the rising edge of SCLK when CS is low. Interrupt request (IRQ) pin in the UART break mode (UBM). The output is in Hi-Z at power up and must be enabled in the CONFIG register. An external pullup or pulldown resistor is required. GPIO5/ SDI 8 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI data input at power up. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. SDI is a Schmitt-trigger logic input. An external pullup or pulldown resistor is required. GPIO6/ CS 10 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI chip-select input at power up. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in Hi-Z and data on SDI are ignored. An external pullup or pulldown resistor is required. IOVDD 12 P Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interfaces. MOD_OUT 23 AO FSK output sinusoid. Maximum supported parallel load capacitance is 2 nF. POL_SEL/ AIN1 16 DI/AI ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to 2 × VREF. Otherwise, this pin acts as ALMV_POL, which sets the polarity of the VOUT alarm voltage. PVDD 17 P Power supply for the internal low-dropout regulator (LDO), ADC input and VOUT DAC output. REF_EN 5 DI Internal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is required at the VREFIO pin. REF_GND 20 P GND reference for VREFIO pin. RESET 6 DI Reset pin, active low. Logic low on this pin turns off the internal oscillator and resets the device. Logic high returns the device to normal operation. Do not leave any digital pins floating. RTS 4 DI Request to send pin. A logic high on this pin enables the demodulator and disables the modulator. A logic low on this pin enables the modulator and disables the demodulator. Do not leave any digital pins floating. RX_IN 21 AI HART FSK input if no external filter is used; otherwise, no connect. RX_INF 22 AI HART FSK input if using the external band-pass filter. If using the internal band-pass filter by connecting the HART FSK to RX_IN, then connect 680-pF capacitor to this pin. SCLK 7 DI SPI clock. Data are transferred at rates up to 12.5 MHz. SCLK is a Schmitt-trigger logic input. Connect to GND or logic low if not used. Do not leave any digital pins floating. VDD 13 P/AO Internal low voltage LDO output. When 2.7 V to 5.5 V on PVDD pin is provided, the internal LDO is enabled. Connect a 1-μF to 10-μF capacitor on this pin. VOUT 18 AO DAC output voltage. VREFIO 19 AI/AO When the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this case, a load capacitance of 70 nF to 130 nF is required for stability. When disabled, this pin is the external 1.25‑V reference input. AIN0 15 AI ADC input voltage. The input range is 0 V to 2 × VREF. AIN015AIADC input voltage. The input range is 0 V to 2 × VREF. ALARM 24 DO Alarm notification pin, open drain, active low. When alarm condition is asserted, this pin is held to logic low; otherwise, this pin is in a high-impedance state (Hi-Z). ALARM ALARM24DOAlarm notification pin, open drain, active low. When alarm condition is asserted, this pin is held to logic low; otherwise, this pin is in a high-impedance state (Hi-Z). GND 14 P Digital and analog ground. Ground reference point for all circuitry on the device. GND14PDigital and analog ground. Ground reference point for all circuitry on the device. GPIO0/ CLK_OUT 11 DO/DI General-purpose input/output (GPIO) pin. Can be configured as a clock output for the 1.2288-MHz internal clock or as a timer. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO0/ CLK_OUT11DO/DIGeneral-purpose input/output (GPIO) pin. Can be configured as a clock output for the 1.2288-MHz internal clock or as a timer. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO1/ CD 3 DO/DI General-purpose input/output (GPIO) pin. Configured as a carrier detect output at power up. A logic high on this pin indicates a valid carrier is present. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO1/ CD3DO/DIGeneral-purpose input/output (GPIO) pin. Configured as a carrier detect output at power up. A logic high on this pin indicates a valid carrier is present. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO2/ UARTOUT 2 DO/DI General-purpose input/output (GPIO) pin. Configured as UART data output at power up. This pin can be configured to function as IRQ pin in SPI only mode. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO2/ UARTOUT2DO/DIGeneral-purpose input/output (GPIO) pin. Configured as UART data output at power up. This pin can be configured to function as IRQ pin in SPI only mode. In Hi-Z if not driven. An external pullup or pulldown resistor is required. GPIO3/ UARTIN 1 DI/DO General-purpose input/output (GPIO) pin. Configured as UART data input at power up. Connect to IOVDD or logic high if not used. An external pullup or pulldown resistor is required. GPIO3/ UARTIN1DI/DOGeneral-purpose input/output (GPIO) pin. Configured as UART data input at power up. Connect to IOVDD or logic high if not used. An external pullup or pulldown resistor is required. GPIO4/ SDO 9 DO/DI General-purpose input/output (GPIO) pin. Can be configured as an SPI data output in SPI mode. Data are output on the rising edge of SCLK when CS is low. Interrupt request (IRQ) pin in the UART break mode (UBM). The output is in Hi-Z at power up and must be enabled in the CONFIG register. An external pullup or pulldown resistor is required. GPIO4/ SDO9DO/DIGeneral-purpose input/output (GPIO) pin. Can be configured as an SPI data output in SPI mode. Data are output on the rising edge of SCLK when CS is low. Interrupt request (IRQ) pin in the UART break mode (UBM). The output is in Hi-Z at power up and must be enabled in the CONFIG register. An external pullup or pulldown resistor is required.CS GPIO5/ SDI 8 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI data input at power up. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. SDI is a Schmitt-trigger logic input. An external pullup or pulldown resistor is required. GPIO5/ SDI8DI/DOGeneral-purpose input/output (GPIO) pin. Configured as an SPI data input at power up. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. SDI is a Schmitt-trigger logic input. An external pullup or pulldown resistor is required. GPIO6/ CS 10 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI chip-select input at power up. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in Hi-Z and data on SDI are ignored. An external pullup or pulldown resistor is required. GPIO6/ CS CS10DI/DOGeneral-purpose input/output (GPIO) pin. Configured as an SPI chip-select input at power up. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in Hi-Z and data on SDI are ignored. An external pullup or pulldown resistor is required.CSCS IOVDD 12 P Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interfaces. IOVDD12PInterface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interfaces. MOD_OUT 23 AO FSK output sinusoid. Maximum supported parallel load capacitance is 2 nF. MOD_OUT23AOFSK output sinusoid. Maximum supported parallel load capacitance is 2 nF. POL_SEL/ AIN1 16 DI/AI ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to 2 × VREF. Otherwise, this pin acts as ALMV_POL, which sets the polarity of the VOUT alarm voltage. POL_SEL/ AIN116DI/AIADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to 2 × VREF. Otherwise, this pin acts as ALMV_POL, which sets the polarity of the VOUT alarm voltage. PVDD 17 P Power supply for the internal low-dropout regulator (LDO), ADC input and VOUT DAC output. PVDD17PPower supply for the internal low-dropout regulator (LDO), ADC input and VOUT DAC output. REF_EN 5 DI Internal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is required at the VREFIO pin. REF_EN5DIInternal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is required at the VREFIO pin. REF_GND 20 P GND reference for VREFIO pin. REF_GND20PGND reference for VREFIO pin. RESET 6 DI Reset pin, active low. Logic low on this pin turns off the internal oscillator and resets the device. Logic high returns the device to normal operation. Do not leave any digital pins floating. RESET RESET6DIReset pin, active low. Logic low on this pin turns off the internal oscillator and resets the device. Logic high returns the device to normal operation. Do not leave any digital pins floating. RTS 4 DI Request to send pin. A logic high on this pin enables the demodulator and disables the modulator. A logic low on this pin enables the modulator and disables the demodulator. Do not leave any digital pins floating. RTS RTS4DIRequest to send pin. A logic high on this pin enables the demodulator and disables the modulator. A logic low on this pin enables the modulator and disables the demodulator. Do not leave any digital pins floating. RX_IN 21 AI HART FSK input if no external filter is used; otherwise, no connect. RX_IN21AIHART FSK input if no external filter is used; otherwise, no connect. RX_INF 22 AI HART FSK input if using the external band-pass filter. If using the internal band-pass filter by connecting the HART FSK to RX_IN, then connect 680-pF capacitor to this pin. RX_INF22AIHART FSK input if using the external band-pass filter. If using the internal band-pass filter by connecting the HART FSK to RX_IN, then connect 680-pF capacitor to this pin. SCLK 7 DI SPI clock. Data are transferred at rates up to 12.5 MHz. SCLK is a Schmitt-trigger logic input. Connect to GND or logic low if not used. Do not leave any digital pins floating. SCLK7DISPI clock. Data are transferred at rates up to 12.5 MHz. SCLK is a Schmitt-trigger logic input. Connect to GND or logic low if not used. Do not leave any digital pins floating. VDD 13 P/AO Internal low voltage LDO output. When 2.7 V to 5.5 V on PVDD pin is provided, the internal LDO is enabled. Connect a 1-μF to 10-μF capacitor on this pin. VDD13P/AOInternal low voltage LDO output. When 2.7 V to 5.5 V on PVDD pin is provided, the internal LDO is enabled. Connect a 1-μF to 10-μF capacitor on this pin. VOUT 18 AO DAC output voltage. VOUT18AODAC output voltage. VREFIO 19 AI/AO When the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this case, a load capacitance of 70 nF to 130 nF is required for stability. When disabled, this pin is the external 1.25‑V reference input. VREFIO19AI/AOWhen the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this case, a load capacitance of 70 nF to 130 nF is required for stability. When disabled, this pin is the external 1.25‑V reference input. AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power. AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power. Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275839/A_1462557802_ABSMAX_FOOTER1_SF1 MIN MAX UNIT Voltage PVDD, IOVDD to GND –0.3 5.5 V VDD to GND –0.3 1.98 V AIN0, POL_SEL/AIN1, VOUT to GND –0.3 PVDD + 0.3 V Digital Input/Output to GND –0.3 IOVDD + 0.3 V VREFIO to GND –0.3 VDD + 0.3 V REF_GND to GND –0.3 0.3 V HART voltage RX_IN, RX_INF, MOD_OUT to GND –0.3 VDD + 0.3 V Input current into any pin –10 10 mA TJ Junction temperature –55 150 °C Tstg Storage temperature –65 150 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT PVDD to GND 2.7 5.5 V VDD to GND 1.71 1.89 V IOVDD to GND 1.71 5.5 V VREFIO to GND, external VREF 1.2 1.25 1.3 V TA Ambient temperature Specified –40 125 °C Operating –55 125 °C Thermal Information THERMAL METRIC1 AFEx82H1 UNIT RRU (UQFN) 24 PINS RθJA Junction-to-ambient thermal resistance 103.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 84.4 °C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance N/A °C/W RθJB Junction-to-board thermal resistance 69.5 °C/W ΨJT Junction-to-top characterization parameter 0.4 °C/W ΨJB Junction-to-board characterization parameter 68.4 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT DAC STATIC PERFORMANCE Resolution AFE882H1 16 Bits AFE782H1 14 INL Integral nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 AFE882H1, TA = –40°C to +125°C –12 12 LSB AFE882H1, TA = –40°C to +85°C –4 4 AFE782H1 –3 3 DNL Differential nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 –1 1 LSB TUE Total unadjusted error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Zero code error, no load TA = –40°C to +125°C 1 mV TA = –40°C to +85°C 1 TA = 25°C 0.5 Zero code error temperature coefficient ±3 ppm/°C Offset error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.07 0.07 %FSR TA = –40°C to +85°C –0.05 0.05 TA = 25°C –0.03 0.03 Offset error temperature coefficient #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm/°C Gain error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Gain error temperature coefficient#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm FSR/°C Full-scale error TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Full-scale error temperature coefficient ±3 ppm FSR/°C VOUT DAC DYNAMIC PERFORMANCE ts Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB 65 µs 10-mV step settling to ±2 LSB 30 Slew rate Full-scale transition measured from 10% to 90% 30 mV/µs Vn Output noise 0.1 Hz to 10 Hz, DAC at midscale 0.25 LSBpp 100-kHz bandwidth, DAC at midscale 32 µVrms Vn Output noise density Measured at 1 kHz, DAC at midscale, PVDD = 3 V 180 nV/√Hz Measured at 1 kHz, DAC at midscale, PVDD = 5 V 260 Power supply rejection ratio (ac) 200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. 85 dB Code change glitch impulse Midcode ±1 LSB (including feedthrough) 4.5 nV-s Code change glitch magnitude Midcode ±1 LSB (including feedthrough), PVDD = 5 V 1.5 mV Digital feedthrough At SCLK = 1 MHz, DAC output at midscale 1 nV-s VOUT DAC OUTPUT CHARACTERISTICS Output voltage 0 2.5 V VOUT alarm output high 2.35 2.5 2.65 V VOUT alarm output low 0.285 0.3 0.315 V RLOAD Resistive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 10 kΩ CLOAD Capacitive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 100 pF Load regulation DAC at midscale, –1 mA ≤ IOUT ≤ +1 mA 10 µV/mA Short-circuit current Full scale output shorted to GND 5 mA Zero output shorted to VDD 5 Output voltage headroom to PVDD DAC at full code, IOUT = 1 mA (sourcing) 200 mV ZO Large signal dc output impedance To GND, DAC at code 0 60 Ω DAC at midscale 10 mΩ DAC at code 65535 10 Output Hi-Z 500 kΩ Power supply rejection ratio (dc) DAC at midscale 0.1 mV/V Output voltage drift vs time, ideal VREF TA = 35°C, VOUT = midscale, 1000 hours ±5 ppmFSR DIAGNOSTIC ADC Input voltage 0 2.5 V Resolution 12 Bits DNL Differential nonlinearity Specified 12-bit monotonic –1 ±0.2 1 LSB INL Integral nonlinearity –4 ±1 4 LSB Offset error After calibration –10 ±1.6 10 LSB Gain error –0.8 ±0.13 0.8 %FSR Noise ±4 LSB Input capacitance 6 pF Input bias current ADC not converting –50 50 nA Acquisition time 52 µs Conversion time 210 µs Conversion rate 3.84 kSPS Temperature sensor accuracy 5 °C INTERNAL OSCILLATOR Frequency TA = –40°C to +125°C 1.2165 1.2288 1.2411 MHz HART MODEM RX_IN INPUT (HART MODE) Input voltage range External or internal reference source, design architecture. Signal applied at the input to the dc blocking capacitor. 0 1.5 VPP Receiver sensitivity Threshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter. 80 100 120 mVPP Carrier detect time 1200 Hz of carrier frequency present at the input before CD asserted 3 baud MOD_OUT OUTPUT (HART MODE) Output voltage Measured at MOD_OUT pin with 160-Ω load,ac-coupled (2.2 µF) 400 500 800 mVPP Mark frequency 1200 Hz Space frequency 2200 Hz Frequency error –40°C to +125°C –1 1 % Phase continuity error Design architecture 0 Degrees Minimum resistive load AC-coupled with 2.2 µF 160 Ω Transmit impedance RTS low, measured at the MOD_OUT pin,1-mA measurement current 25 mΩ Transmit impedance RTS high, measured at the MOD_OUT pin, ±200-nA measurement current 50 kΩ VOLTAGE REFERENCE INPUT ZVREFIO Reference input impedance (VREFIO) 125 kΩ CVREFIO Reference input capacitance (VREFIO) 100 pF VOLTAGE REFERENCE OUTPUT Output (initial accuracy)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 25°C 1.248 1.25 1.252 V Output drift#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = –40°C to +125°C 10 ppm/℃ Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Ω Output noise#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Hz to 10 Hz 7.5 µVPP Output noise density#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Measured at 10 kHz, reference load = 100 nF 200 nV/√Hz Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.1% VREF change from nominal 2.5 mA Sinking, 0.1% VREF change from nominal 0.3 Load regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0 mA to 2.5 mA 4 µV/mA COUT Stable output capacitance TA = –40°C to +125°C, ESR from 10 mΩ to 400 mΩ 70 100 130 nF Line regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 100 µV/V Output voltage drift vs time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 35°C, 1000 hours ±100 ppm Thermal hysteresis#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 1st cycle 500 µV Additional cycles 25 µV VDD VOLTAGE REGULATOR OUTPUT Output voltage 1.71 1.8 1.89 V Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.5 mA to 2.5 mA 3 Ω Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 1% VDD change from nominal 4 mA THERMAL ALARM Alarm trip point 130 °C Warning trip point 85 °C Hysteresis 12 °C Trip point absolute accuracy 5 °C Trip point relative accuracy 2 °C DIGITAL INPUT CHARACTERISTICS VIH High-level input voltage 0.7 V/IOVDD VIL Low-level input voltage 0.3 V/IOVDD Hysteresis voltage 0.05 V/IOVDD Input current –1.56 1.56 µA Pin capacitance Per pin 10 pF DIGITAL OUTPUT CHARACTERISTICS VOH High-level output voltage ISOURCE = 1 mA 0.8 V/IOVDD VOL Low-level output voltage ISINK = 1 mA 0.2 V/IOVDD VOL Open-drain low-level output voltage ISINK = 2 mA 0.3 V Output pin capacitance 10 pF POWER REQUIREMENTS IPVDD Current flowing into PVDD DAC at zero-scale, SPI static 180 220 µA IREFIO Internal reference current consumption 52 70 µA IHART HART Tx modem current consumption 10 µA IADC ADC current consumption ADC converting at 3.84 kSPS 10 µA CVDD Recommended VDD decoupling capacitance 1 10 µF IIOVDD Current flowing into IOVDD SPI static 10 25 µA IVREFIO Current flowing into VREFIO DAC at midscale code 10 µA End point fit between code 512 to code 65,535 for 16-bit, code 128 to code 16,383 for 14-bit, DAC output unloaded, performance under resistive and capacitive load conditions are specified by design and characterization. Not production tested. Design target. Not production tested. Derived from the characterization data. Timing Requirements all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2, 2.7 V ≤ PVDD ≤ 5.5 V,VIH = 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V and TA = –40°C to +125°C (unless otherwise noted) PARAMETER MIN NOM MAX UNIT SERIAL INTERFACE - WRITE AND READ OPERATION fSCLK Serial clock frequency 12.5 MHz tSCLKHIGH SCLK high time 36 ns tSCLKLOW SCLK low time 36 ns tCSHIGH CS high time 80 ns tCSS CS to SCLK falling edge setup time 30 ns tCSH SCLK falling edge to CS rising edge 30 ns tCSRI CS rising edge to SCLK falling edge ignore 30 ns tCSFI SCLK falling edge ignore to CS falling edge 5 ns tSDIS SDI setup time 5 ns tSDIH SDI hold time 5 ns tSDOZD CS falling edge to SDO tri-state condition to driven 40 ns tSDODZ CS rising edge to SDO driven to tri-state condition 40 ns tSDODLY SCLK to SDO output delay 40 ns UART tBAUDUART Baud rate = 9600 ±1% 104 µs tBAUDUART Baud rate = 1200 ±1% 833 µs HART tBAUDHART Baud rate = 1200 ± 1% 833 µs DIGITAL LOGIC tDACWAIT Sequential DAC update wait time 2.1 µs tPOR POR reset delay 100 µs tRESET RESET pulse duration 100 ns tRESETWAIT Wait time after RESET pulse 10 µs tPULSE_GPIO GPIO input pulse duration 10 ns Timing Diagrams SPI Timing UBM Timing Typical Characteristics: VOUT DAC at TA = 25°C, PVDD = 2.7 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) DAC DNL vs Digital Input Code   MIN and MAX DAC DNL Range vs Temperature   DAC INL vs Digital Input Code   MIN and MAX DAC INL Range vs Temperature   DAC TUE vs Digital Input Code   MIN and MAX DAC TUE vs Temperature   Zero-code Impedance   DAC Footroom Over Temperature and Load   DAC Source and Sink Current Capability DAC at midcode DAC Output Voltage Long-Term Stability Ideal reference DAC Glitch Impulse Rising Edge PVDD = 5.5 V DAC Glitch Impulse Falling Edge PVDD = 5.5 V DAC Gain Error vs Temperature DAC Offset Error vs Temperature DAC Full Scale Error vs Temperature DAC Zero Scale Error vs Temperature DAC Output Noise, 0.1 Hz to 10 Hz DAC at midcode PVDD = 5.5 V DAC Output Noise Density vs Frequency DAC at midcode PVDD = 5.5 V DAC Rising Settling Time   DAC Falling Settling Time   DAC Settling Time With Linear Slew Rate Control   DAC Settling Time With Sinusoidal Slew Rate Control   DAC RESET Response   DAC Supply Power On, PVDD = 2.7 V   DAC AC PSRR vs Frequency Internal reference Typical Characteristics: ADC at TA = 25°C, PVDD = 3.3 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) ADC DNL vs Digital Input Code   ADC INL vs Digital Input Code   ADC DNL Range vs Temperature   ADC INL Range vs Temperature   ADC Offset Error vs Temperature   ADC Gain Error vs Temperature   Typical Characteristics: Reference at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Reference Voltage Temperature Drift Pre-soldered 30 units Reference Voltage Temperature Drift Post-soldered 30 units Multiple Temperature Cycle Hysteresis   –40°C to +85°C cycles, 60 minutes per cycle, 30 units Multiple Temperature Cycle Hysteresis –40°C to +85°C cycles, 60 minutes per cycle Ambient Temperature Change Settling Two minutes after 25°C to 85°C temperature step, 30 units Reference Voltage Long-Term Stability 30 units  Reference Output Noise, 0.1 Hz to 10 Hz   Reference AC PSRR vs frequency   Reference Source and Sink Current Capability   Initial Accuracy Distribution Typical Characteristics: HART Modem at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) HART Internal Mode First Stage Band-Pass Filter Response (From HART_RX Signal to RX_INF Pin)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground HART Internal Mode Complete Band-Pass Filter Response (From HART_RX Signal to Internal Demodulator)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground Typical Characteristics: Power Supply at TA = 25°C, PVDD = IOVDD = 3.3 V, internal VREFIO, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) PVDD Supply Current vs Temperature   IOVDD Supply Current vs Temperature   VDD Voltage vs Load Current   Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275839/A_1462557802_ABSMAX_FOOTER1_SF1 MIN MAX UNIT Voltage PVDD, IOVDD to GND –0.3 5.5 V VDD to GND –0.3 1.98 V AIN0, POL_SEL/AIN1, VOUT to GND –0.3 PVDD + 0.3 V Digital Input/Output to GND –0.3 IOVDD + 0.3 V VREFIO to GND –0.3 VDD + 0.3 V REF_GND to GND –0.3 0.3 V HART voltage RX_IN, RX_INF, MOD_OUT to GND –0.3 VDD + 0.3 V Input current into any pin –10 10 mA TJ Junction temperature –55 150 °C Tstg Storage temperature –65 150 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275839/A_1462557802_ABSMAX_FOOTER1_SF1 MIN MAX UNIT Voltage PVDD, IOVDD to GND –0.3 5.5 V VDD to GND –0.3 1.98 V AIN0, POL_SEL/AIN1, VOUT to GND –0.3 PVDD + 0.3 V Digital Input/Output to GND –0.3 IOVDD + 0.3 V VREFIO to GND –0.3 VDD + 0.3 V REF_GND to GND –0.3 0.3 V HART voltage RX_IN, RX_INF, MOD_OUT to GND –0.3 VDD + 0.3 V Input current into any pin –10 10 mA TJ Junction temperature –55 150 °C Tstg Storage temperature –65 150 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275839/A_1462557802_ABSMAX_FOOTER1_SF1 MIN MAX UNIT Voltage PVDD, IOVDD to GND –0.3 5.5 V VDD to GND –0.3 1.98 V AIN0, POL_SEL/AIN1, VOUT to GND –0.3 PVDD + 0.3 V Digital Input/Output to GND –0.3 IOVDD + 0.3 V VREFIO to GND –0.3 VDD + 0.3 V REF_GND to GND –0.3 0.3 V HART voltage RX_IN, RX_INF, MOD_OUT to GND –0.3 VDD + 0.3 V Input current into any pin –10 10 mA TJ Junction temperature –55 150 °C Tstg Storage temperature –65 150 over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275839/A_1462557802_ABSMAX_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275839/A_1462557802_ABSMAX_FOOTER1_SF1 MIN MAX UNIT Voltage PVDD, IOVDD to GND –0.3 5.5 V VDD to GND –0.3 1.98 V AIN0, POL_SEL/AIN1, VOUT to GND –0.3 PVDD + 0.3 V Digital Input/Output to GND –0.3 IOVDD + 0.3 V VREFIO to GND –0.3 VDD + 0.3 V REF_GND to GND –0.3 0.3 V HART voltage RX_IN, RX_INF, MOD_OUT to GND –0.3 VDD + 0.3 V Input current into any pin –10 10 mA TJ Junction temperature –55 150 °C Tstg Storage temperature –65 150 MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Voltage PVDD, IOVDD to GND –0.3 5.5 V VDD to GND –0.3 1.98 V AIN0, POL_SEL/AIN1, VOUT to GND –0.3 PVDD + 0.3 V Digital Input/Output to GND –0.3 IOVDD + 0.3 V VREFIO to GND –0.3 VDD + 0.3 V REF_GND to GND –0.3 0.3 V HART voltage RX_IN, RX_INF, MOD_OUT to GND –0.3 VDD + 0.3 V Input current into any pin –10 10 mA TJ Junction temperature –55 150 °C Tstg Storage temperature –65 150 Voltage PVDD, IOVDD to GND –0.3 5.5 V VoltagePVDD, IOVDD to GND–0.35.5V VDD to GND –0.3 1.98 V VDD to GND–0.31.98V AIN0, POL_SEL/AIN1, VOUT to GND –0.3 PVDD + 0.3 V AIN0, POL_SEL/AIN1, VOUT to GND–0.3PVDD + 0.3V Digital Input/Output to GND –0.3 IOVDD + 0.3 V Digital Input/Output to GND–0.3IOVDD + 0.3V VREFIO to GND –0.3 VDD + 0.3 V VREFIO to GND–0.3VDD + 0.3V REF_GND to GND –0.3 0.3 V REF_GND to GND–0.30.3V HART voltage RX_IN, RX_INF, MOD_OUT to GND –0.3 VDD + 0.3 V HART voltageRX_IN, RX_INF, MOD_OUT to GND–0.3VDD + 0.3V Input current into any pin –10 10 mA Input current into any pin–1010mA TJ Junction temperature –55 150 °C TJ JJunction temperature–55150°C Tstg Storage temperature –65 150 Tstg stgStorage temperature–65150 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. Absolute Maximum Ratings Absolute Maximum RatingsRecommended Operating ConditionsRecommended Operating Conditions Absolute Maximum Ratings ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER2_SF1 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER1_SF1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER1_SF1±2000V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER2_SF1 ±500 Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275840/A_1462557802_HANDRATINGS_COMERCIAL_FOOTER2_SF1±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT PVDD to GND 2.7 5.5 V VDD to GND 1.71 1.89 V IOVDD to GND 1.71 5.5 V VREFIO to GND, external VREF 1.2 1.25 1.3 V TA Ambient temperature Specified –40 125 °C Operating –55 125 °C Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT PVDD to GND 2.7 5.5 V VDD to GND 1.71 1.89 V IOVDD to GND 1.71 5.5 V VREFIO to GND, external VREF 1.2 1.25 1.3 V TA Ambient temperature Specified –40 125 °C Operating –55 125 °C over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT PVDD to GND 2.7 5.5 V VDD to GND 1.71 1.89 V IOVDD to GND 1.71 5.5 V VREFIO to GND, external VREF 1.2 1.25 1.3 V TA Ambient temperature Specified –40 125 °C Operating –55 125 °C over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT PVDD to GND 2.7 5.5 V VDD to GND 1.71 1.89 V IOVDD to GND 1.71 5.5 V VREFIO to GND, external VREF 1.2 1.25 1.3 V TA Ambient temperature Specified –40 125 °C Operating –55 125 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT PVDD to GND 2.7 5.5 V VDD to GND 1.71 1.89 V IOVDD to GND 1.71 5.5 V VREFIO to GND, external VREF 1.2 1.25 1.3 V TA Ambient temperature Specified –40 125 °C Operating –55 125 °C PVDD to GND 2.7 5.5 V PVDD to GND 2.75.5V VDD to GND 1.71 1.89 V VDD to GND1.711.89V IOVDD to GND 1.71 5.5 V IOVDD to GND1.715.5V VREFIO to GND, external VREF 1.2 1.25 1.3 V VREFIO to GND, external VREF1.21.251.3V TA Ambient temperature Specified –40 125 °C TA AAmbient temperatureSpecified–40125°C Operating –55 125 °C Operating–55125°C Thermal Information THERMAL METRIC1 AFEx82H1 UNIT RRU (UQFN) 24 PINS RθJA Junction-to-ambient thermal resistance 103.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 84.4 °C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance N/A °C/W RθJB Junction-to-board thermal resistance 69.5 °C/W ΨJT Junction-to-top characterization parameter 0.4 °C/W ΨJB Junction-to-board characterization parameter 68.4 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC1 AFEx82H1 UNIT RRU (UQFN) 24 PINS RθJA Junction-to-ambient thermal resistance 103.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 84.4 °C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance N/A °C/W RθJB Junction-to-board thermal resistance 69.5 °C/W ΨJT Junction-to-top characterization parameter 0.4 °C/W ΨJB Junction-to-board characterization parameter 68.4 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC1 AFEx82H1 UNIT RRU (UQFN) 24 PINS RθJA Junction-to-ambient thermal resistance 103.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 84.4 °C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance N/A °C/W RθJB Junction-to-board thermal resistance 69.5 °C/W ΨJT Junction-to-top characterization parameter 0.4 °C/W ΨJB Junction-to-board characterization parameter 68.4 °C/W THERMAL METRIC1 AFEx82H1 UNIT RRU (UQFN) 24 PINS RθJA Junction-to-ambient thermal resistance 103.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 84.4 °C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance N/A °C/W RθJB Junction-to-board thermal resistance 69.5 °C/W ΨJT Junction-to-top characterization parameter 0.4 °C/W ΨJB Junction-to-board characterization parameter 68.4 °C/W THERMAL METRIC1 AFEx82H1 UNIT RRU (UQFN) 24 PINS THERMAL METRIC1 AFEx82H1 UNIT THERMAL METRIC1 1 AFEx82H1 AFEx82H1UNIT RRU (UQFN) RRU (UQFN) 24 PINS 24 PINS RθJA Junction-to-ambient thermal resistance 103.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 84.4 °C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance N/A °C/W RθJB Junction-to-board thermal resistance 69.5 °C/W ΨJT Junction-to-top characterization parameter 0.4 °C/W ΨJB Junction-to-board characterization parameter 68.4 °C/W RθJA Junction-to-ambient thermal resistance 103.1 °C/W RθJA θJA Junction-to-ambient thermal resistance103.1°C/W RθJC(top) Junction-to-case (top) thermal resistance 84.4 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance84.4°C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance N/A °C/W RθJC(bottom) θJC(bottom)Junction-to-case (bottom) thermal resistanceN/A°C/W RθJB Junction-to-board thermal resistance 69.5 °C/W RθJB θJBJunction-to-board thermal resistance69.5°C/W ΨJT Junction-to-top characterization parameter 0.4 °C/W ΨJT JTJunction-to-top characterization parameter0.4°C/W ΨJB Junction-to-board characterization parameter 68.4 °C/W ΨJB JBJunction-to-board characterization parameter68.4°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Semiconductor and IC Package Thermal Metrics application report. Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT DAC STATIC PERFORMANCE Resolution AFE882H1 16 Bits AFE782H1 14 INL Integral nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 AFE882H1, TA = –40°C to +125°C –12 12 LSB AFE882H1, TA = –40°C to +85°C –4 4 AFE782H1 –3 3 DNL Differential nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 –1 1 LSB TUE Total unadjusted error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Zero code error, no load TA = –40°C to +125°C 1 mV TA = –40°C to +85°C 1 TA = 25°C 0.5 Zero code error temperature coefficient ±3 ppm/°C Offset error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.07 0.07 %FSR TA = –40°C to +85°C –0.05 0.05 TA = 25°C –0.03 0.03 Offset error temperature coefficient #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm/°C Gain error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Gain error temperature coefficient#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm FSR/°C Full-scale error TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Full-scale error temperature coefficient ±3 ppm FSR/°C VOUT DAC DYNAMIC PERFORMANCE ts Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB 65 µs 10-mV step settling to ±2 LSB 30 Slew rate Full-scale transition measured from 10% to 90% 30 mV/µs Vn Output noise 0.1 Hz to 10 Hz, DAC at midscale 0.25 LSBpp 100-kHz bandwidth, DAC at midscale 32 µVrms Vn Output noise density Measured at 1 kHz, DAC at midscale, PVDD = 3 V 180 nV/√Hz Measured at 1 kHz, DAC at midscale, PVDD = 5 V 260 Power supply rejection ratio (ac) 200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. 85 dB Code change glitch impulse Midcode ±1 LSB (including feedthrough) 4.5 nV-s Code change glitch magnitude Midcode ±1 LSB (including feedthrough), PVDD = 5 V 1.5 mV Digital feedthrough At SCLK = 1 MHz, DAC output at midscale 1 nV-s VOUT DAC OUTPUT CHARACTERISTICS Output voltage 0 2.5 V VOUT alarm output high 2.35 2.5 2.65 V VOUT alarm output low 0.285 0.3 0.315 V RLOAD Resistive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 10 kΩ CLOAD Capacitive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 100 pF Load regulation DAC at midscale, –1 mA ≤ IOUT ≤ +1 mA 10 µV/mA Short-circuit current Full scale output shorted to GND 5 mA Zero output shorted to VDD 5 Output voltage headroom to PVDD DAC at full code, IOUT = 1 mA (sourcing) 200 mV ZO Large signal dc output impedance To GND, DAC at code 0 60 Ω DAC at midscale 10 mΩ DAC at code 65535 10 Output Hi-Z 500 kΩ Power supply rejection ratio (dc) DAC at midscale 0.1 mV/V Output voltage drift vs time, ideal VREF TA = 35°C, VOUT = midscale, 1000 hours ±5 ppmFSR DIAGNOSTIC ADC Input voltage 0 2.5 V Resolution 12 Bits DNL Differential nonlinearity Specified 12-bit monotonic –1 ±0.2 1 LSB INL Integral nonlinearity –4 ±1 4 LSB Offset error After calibration –10 ±1.6 10 LSB Gain error –0.8 ±0.13 0.8 %FSR Noise ±4 LSB Input capacitance 6 pF Input bias current ADC not converting –50 50 nA Acquisition time 52 µs Conversion time 210 µs Conversion rate 3.84 kSPS Temperature sensor accuracy 5 °C INTERNAL OSCILLATOR Frequency TA = –40°C to +125°C 1.2165 1.2288 1.2411 MHz HART MODEM RX_IN INPUT (HART MODE) Input voltage range External or internal reference source, design architecture. Signal applied at the input to the dc blocking capacitor. 0 1.5 VPP Receiver sensitivity Threshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter. 80 100 120 mVPP Carrier detect time 1200 Hz of carrier frequency present at the input before CD asserted 3 baud MOD_OUT OUTPUT (HART MODE) Output voltage Measured at MOD_OUT pin with 160-Ω load,ac-coupled (2.2 µF) 400 500 800 mVPP Mark frequency 1200 Hz Space frequency 2200 Hz Frequency error –40°C to +125°C –1 1 % Phase continuity error Design architecture 0 Degrees Minimum resistive load AC-coupled with 2.2 µF 160 Ω Transmit impedance RTS low, measured at the MOD_OUT pin,1-mA measurement current 25 mΩ Transmit impedance RTS high, measured at the MOD_OUT pin, ±200-nA measurement current 50 kΩ VOLTAGE REFERENCE INPUT ZVREFIO Reference input impedance (VREFIO) 125 kΩ CVREFIO Reference input capacitance (VREFIO) 100 pF VOLTAGE REFERENCE OUTPUT Output (initial accuracy)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 25°C 1.248 1.25 1.252 V Output drift#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = –40°C to +125°C 10 ppm/℃ Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Ω Output noise#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Hz to 10 Hz 7.5 µVPP Output noise density#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Measured at 10 kHz, reference load = 100 nF 200 nV/√Hz Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.1% VREF change from nominal 2.5 mA Sinking, 0.1% VREF change from nominal 0.3 Load regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0 mA to 2.5 mA 4 µV/mA COUT Stable output capacitance TA = –40°C to +125°C, ESR from 10 mΩ to 400 mΩ 70 100 130 nF Line regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 100 µV/V Output voltage drift vs time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 35°C, 1000 hours ±100 ppm Thermal hysteresis#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 1st cycle 500 µV Additional cycles 25 µV VDD VOLTAGE REGULATOR OUTPUT Output voltage 1.71 1.8 1.89 V Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.5 mA to 2.5 mA 3 Ω Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 1% VDD change from nominal 4 mA THERMAL ALARM Alarm trip point 130 °C Warning trip point 85 °C Hysteresis 12 °C Trip point absolute accuracy 5 °C Trip point relative accuracy 2 °C DIGITAL INPUT CHARACTERISTICS VIH High-level input voltage 0.7 V/IOVDD VIL Low-level input voltage 0.3 V/IOVDD Hysteresis voltage 0.05 V/IOVDD Input current –1.56 1.56 µA Pin capacitance Per pin 10 pF DIGITAL OUTPUT CHARACTERISTICS VOH High-level output voltage ISOURCE = 1 mA 0.8 V/IOVDD VOL Low-level output voltage ISINK = 1 mA 0.2 V/IOVDD VOL Open-drain low-level output voltage ISINK = 2 mA 0.3 V Output pin capacitance 10 pF POWER REQUIREMENTS IPVDD Current flowing into PVDD DAC at zero-scale, SPI static 180 220 µA IREFIO Internal reference current consumption 52 70 µA IHART HART Tx modem current consumption 10 µA IADC ADC current consumption ADC converting at 3.84 kSPS 10 µA CVDD Recommended VDD decoupling capacitance 1 10 µF IIOVDD Current flowing into IOVDD SPI static 10 25 µA IVREFIO Current flowing into VREFIO DAC at midscale code 10 µA End point fit between code 512 to code 65,535 for 16-bit, code 128 to code 16,383 for 14-bit, DAC output unloaded, performance under resistive and capacitive load conditions are specified by design and characterization. Not production tested. Design target. Not production tested. Derived from the characterization data. Electrical Characteristics all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT DAC STATIC PERFORMANCE Resolution AFE882H1 16 Bits AFE782H1 14 INL Integral nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 AFE882H1, TA = –40°C to +125°C –12 12 LSB AFE882H1, TA = –40°C to +85°C –4 4 AFE782H1 –3 3 DNL Differential nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 –1 1 LSB TUE Total unadjusted error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Zero code error, no load TA = –40°C to +125°C 1 mV TA = –40°C to +85°C 1 TA = 25°C 0.5 Zero code error temperature coefficient ±3 ppm/°C Offset error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.07 0.07 %FSR TA = –40°C to +85°C –0.05 0.05 TA = 25°C –0.03 0.03 Offset error temperature coefficient #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm/°C Gain error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Gain error temperature coefficient#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm FSR/°C Full-scale error TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Full-scale error temperature coefficient ±3 ppm FSR/°C VOUT DAC DYNAMIC PERFORMANCE ts Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB 65 µs 10-mV step settling to ±2 LSB 30 Slew rate Full-scale transition measured from 10% to 90% 30 mV/µs Vn Output noise 0.1 Hz to 10 Hz, DAC at midscale 0.25 LSBpp 100-kHz bandwidth, DAC at midscale 32 µVrms Vn Output noise density Measured at 1 kHz, DAC at midscale, PVDD = 3 V 180 nV/√Hz Measured at 1 kHz, DAC at midscale, PVDD = 5 V 260 Power supply rejection ratio (ac) 200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. 85 dB Code change glitch impulse Midcode ±1 LSB (including feedthrough) 4.5 nV-s Code change glitch magnitude Midcode ±1 LSB (including feedthrough), PVDD = 5 V 1.5 mV Digital feedthrough At SCLK = 1 MHz, DAC output at midscale 1 nV-s VOUT DAC OUTPUT CHARACTERISTICS Output voltage 0 2.5 V VOUT alarm output high 2.35 2.5 2.65 V VOUT alarm output low 0.285 0.3 0.315 V RLOAD Resistive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 10 kΩ CLOAD Capacitive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 100 pF Load regulation DAC at midscale, –1 mA ≤ IOUT ≤ +1 mA 10 µV/mA Short-circuit current Full scale output shorted to GND 5 mA Zero output shorted to VDD 5 Output voltage headroom to PVDD DAC at full code, IOUT = 1 mA (sourcing) 200 mV ZO Large signal dc output impedance To GND, DAC at code 0 60 Ω DAC at midscale 10 mΩ DAC at code 65535 10 Output Hi-Z 500 kΩ Power supply rejection ratio (dc) DAC at midscale 0.1 mV/V Output voltage drift vs time, ideal VREF TA = 35°C, VOUT = midscale, 1000 hours ±5 ppmFSR DIAGNOSTIC ADC Input voltage 0 2.5 V Resolution 12 Bits DNL Differential nonlinearity Specified 12-bit monotonic –1 ±0.2 1 LSB INL Integral nonlinearity –4 ±1 4 LSB Offset error After calibration –10 ±1.6 10 LSB Gain error –0.8 ±0.13 0.8 %FSR Noise ±4 LSB Input capacitance 6 pF Input bias current ADC not converting –50 50 nA Acquisition time 52 µs Conversion time 210 µs Conversion rate 3.84 kSPS Temperature sensor accuracy 5 °C INTERNAL OSCILLATOR Frequency TA = –40°C to +125°C 1.2165 1.2288 1.2411 MHz HART MODEM RX_IN INPUT (HART MODE) Input voltage range External or internal reference source, design architecture. Signal applied at the input to the dc blocking capacitor. 0 1.5 VPP Receiver sensitivity Threshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter. 80 100 120 mVPP Carrier detect time 1200 Hz of carrier frequency present at the input before CD asserted 3 baud MOD_OUT OUTPUT (HART MODE) Output voltage Measured at MOD_OUT pin with 160-Ω load,ac-coupled (2.2 µF) 400 500 800 mVPP Mark frequency 1200 Hz Space frequency 2200 Hz Frequency error –40°C to +125°C –1 1 % Phase continuity error Design architecture 0 Degrees Minimum resistive load AC-coupled with 2.2 µF 160 Ω Transmit impedance RTS low, measured at the MOD_OUT pin,1-mA measurement current 25 mΩ Transmit impedance RTS high, measured at the MOD_OUT pin, ±200-nA measurement current 50 kΩ VOLTAGE REFERENCE INPUT ZVREFIO Reference input impedance (VREFIO) 125 kΩ CVREFIO Reference input capacitance (VREFIO) 100 pF VOLTAGE REFERENCE OUTPUT Output (initial accuracy)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 25°C 1.248 1.25 1.252 V Output drift#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = –40°C to +125°C 10 ppm/℃ Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Ω Output noise#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Hz to 10 Hz 7.5 µVPP Output noise density#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Measured at 10 kHz, reference load = 100 nF 200 nV/√Hz Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.1% VREF change from nominal 2.5 mA Sinking, 0.1% VREF change from nominal 0.3 Load regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0 mA to 2.5 mA 4 µV/mA COUT Stable output capacitance TA = –40°C to +125°C, ESR from 10 mΩ to 400 mΩ 70 100 130 nF Line regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 100 µV/V Output voltage drift vs time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 35°C, 1000 hours ±100 ppm Thermal hysteresis#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 1st cycle 500 µV Additional cycles 25 µV VDD VOLTAGE REGULATOR OUTPUT Output voltage 1.71 1.8 1.89 V Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.5 mA to 2.5 mA 3 Ω Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 1% VDD change from nominal 4 mA THERMAL ALARM Alarm trip point 130 °C Warning trip point 85 °C Hysteresis 12 °C Trip point absolute accuracy 5 °C Trip point relative accuracy 2 °C DIGITAL INPUT CHARACTERISTICS VIH High-level input voltage 0.7 V/IOVDD VIL Low-level input voltage 0.3 V/IOVDD Hysteresis voltage 0.05 V/IOVDD Input current –1.56 1.56 µA Pin capacitance Per pin 10 pF DIGITAL OUTPUT CHARACTERISTICS VOH High-level output voltage ISOURCE = 1 mA 0.8 V/IOVDD VOL Low-level output voltage ISINK = 1 mA 0.2 V/IOVDD VOL Open-drain low-level output voltage ISINK = 2 mA 0.3 V Output pin capacitance 10 pF POWER REQUIREMENTS IPVDD Current flowing into PVDD DAC at zero-scale, SPI static 180 220 µA IREFIO Internal reference current consumption 52 70 µA IHART HART Tx modem current consumption 10 µA IADC ADC current consumption ADC converting at 3.84 kSPS 10 µA CVDD Recommended VDD decoupling capacitance 1 10 µF IIOVDD Current flowing into IOVDD SPI static 10 25 µA IVREFIO Current flowing into VREFIO DAC at midscale code 10 µA End point fit between code 512 to code 65,535 for 16-bit, code 128 to code 16,383 for 14-bit, DAC output unloaded, performance under resistive and capacitive load conditions are specified by design and characterization. Not production tested. Design target. Not production tested. Derived from the characterization data. all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT DAC STATIC PERFORMANCE Resolution AFE882H1 16 Bits AFE782H1 14 INL Integral nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 AFE882H1, TA = –40°C to +125°C –12 12 LSB AFE882H1, TA = –40°C to +85°C –4 4 AFE782H1 –3 3 DNL Differential nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 –1 1 LSB TUE Total unadjusted error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Zero code error, no load TA = –40°C to +125°C 1 mV TA = –40°C to +85°C 1 TA = 25°C 0.5 Zero code error temperature coefficient ±3 ppm/°C Offset error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.07 0.07 %FSR TA = –40°C to +85°C –0.05 0.05 TA = 25°C –0.03 0.03 Offset error temperature coefficient #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm/°C Gain error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Gain error temperature coefficient#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm FSR/°C Full-scale error TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Full-scale error temperature coefficient ±3 ppm FSR/°C VOUT DAC DYNAMIC PERFORMANCE ts Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB 65 µs 10-mV step settling to ±2 LSB 30 Slew rate Full-scale transition measured from 10% to 90% 30 mV/µs Vn Output noise 0.1 Hz to 10 Hz, DAC at midscale 0.25 LSBpp 100-kHz bandwidth, DAC at midscale 32 µVrms Vn Output noise density Measured at 1 kHz, DAC at midscale, PVDD = 3 V 180 nV/√Hz Measured at 1 kHz, DAC at midscale, PVDD = 5 V 260 Power supply rejection ratio (ac) 200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. 85 dB Code change glitch impulse Midcode ±1 LSB (including feedthrough) 4.5 nV-s Code change glitch magnitude Midcode ±1 LSB (including feedthrough), PVDD = 5 V 1.5 mV Digital feedthrough At SCLK = 1 MHz, DAC output at midscale 1 nV-s VOUT DAC OUTPUT CHARACTERISTICS Output voltage 0 2.5 V VOUT alarm output high 2.35 2.5 2.65 V VOUT alarm output low 0.285 0.3 0.315 V RLOAD Resistive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 10 kΩ CLOAD Capacitive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 100 pF Load regulation DAC at midscale, –1 mA ≤ IOUT ≤ +1 mA 10 µV/mA Short-circuit current Full scale output shorted to GND 5 mA Zero output shorted to VDD 5 Output voltage headroom to PVDD DAC at full code, IOUT = 1 mA (sourcing) 200 mV ZO Large signal dc output impedance To GND, DAC at code 0 60 Ω DAC at midscale 10 mΩ DAC at code 65535 10 Output Hi-Z 500 kΩ Power supply rejection ratio (dc) DAC at midscale 0.1 mV/V Output voltage drift vs time, ideal VREF TA = 35°C, VOUT = midscale, 1000 hours ±5 ppmFSR DIAGNOSTIC ADC Input voltage 0 2.5 V Resolution 12 Bits DNL Differential nonlinearity Specified 12-bit monotonic –1 ±0.2 1 LSB INL Integral nonlinearity –4 ±1 4 LSB Offset error After calibration –10 ±1.6 10 LSB Gain error –0.8 ±0.13 0.8 %FSR Noise ±4 LSB Input capacitance 6 pF Input bias current ADC not converting –50 50 nA Acquisition time 52 µs Conversion time 210 µs Conversion rate 3.84 kSPS Temperature sensor accuracy 5 °C INTERNAL OSCILLATOR Frequency TA = –40°C to +125°C 1.2165 1.2288 1.2411 MHz HART MODEM RX_IN INPUT (HART MODE) Input voltage range External or internal reference source, design architecture. Signal applied at the input to the dc blocking capacitor. 0 1.5 VPP Receiver sensitivity Threshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter. 80 100 120 mVPP Carrier detect time 1200 Hz of carrier frequency present at the input before CD asserted 3 baud MOD_OUT OUTPUT (HART MODE) Output voltage Measured at MOD_OUT pin with 160-Ω load,ac-coupled (2.2 µF) 400 500 800 mVPP Mark frequency 1200 Hz Space frequency 2200 Hz Frequency error –40°C to +125°C –1 1 % Phase continuity error Design architecture 0 Degrees Minimum resistive load AC-coupled with 2.2 µF 160 Ω Transmit impedance RTS low, measured at the MOD_OUT pin,1-mA measurement current 25 mΩ Transmit impedance RTS high, measured at the MOD_OUT pin, ±200-nA measurement current 50 kΩ VOLTAGE REFERENCE INPUT ZVREFIO Reference input impedance (VREFIO) 125 kΩ CVREFIO Reference input capacitance (VREFIO) 100 pF VOLTAGE REFERENCE OUTPUT Output (initial accuracy)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 25°C 1.248 1.25 1.252 V Output drift#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = –40°C to +125°C 10 ppm/℃ Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Ω Output noise#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Hz to 10 Hz 7.5 µVPP Output noise density#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Measured at 10 kHz, reference load = 100 nF 200 nV/√Hz Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.1% VREF change from nominal 2.5 mA Sinking, 0.1% VREF change from nominal 0.3 Load regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0 mA to 2.5 mA 4 µV/mA COUT Stable output capacitance TA = –40°C to +125°C, ESR from 10 mΩ to 400 mΩ 70 100 130 nF Line regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 100 µV/V Output voltage drift vs time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 35°C, 1000 hours ±100 ppm Thermal hysteresis#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 1st cycle 500 µV Additional cycles 25 µV VDD VOLTAGE REGULATOR OUTPUT Output voltage 1.71 1.8 1.89 V Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.5 mA to 2.5 mA 3 Ω Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 1% VDD change from nominal 4 mA THERMAL ALARM Alarm trip point 130 °C Warning trip point 85 °C Hysteresis 12 °C Trip point absolute accuracy 5 °C Trip point relative accuracy 2 °C DIGITAL INPUT CHARACTERISTICS VIH High-level input voltage 0.7 V/IOVDD VIL Low-level input voltage 0.3 V/IOVDD Hysteresis voltage 0.05 V/IOVDD Input current –1.56 1.56 µA Pin capacitance Per pin 10 pF DIGITAL OUTPUT CHARACTERISTICS VOH High-level output voltage ISOURCE = 1 mA 0.8 V/IOVDD VOL Low-level output voltage ISINK = 1 mA 0.2 V/IOVDD VOL Open-drain low-level output voltage ISINK = 2 mA 0.3 V Output pin capacitance 10 pF POWER REQUIREMENTS IPVDD Current flowing into PVDD DAC at zero-scale, SPI static 180 220 µA IREFIO Internal reference current consumption 52 70 µA IHART HART Tx modem current consumption 10 µA IADC ADC current consumption ADC converting at 3.84 kSPS 10 µA CVDD Recommended VDD decoupling capacitance 1 10 µF IIOVDD Current flowing into IOVDD SPI static 10 25 µA IVREFIO Current flowing into VREFIO DAC at midscale code 10 µA all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted)AALOADLOAD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT DAC STATIC PERFORMANCE Resolution AFE882H1 16 Bits AFE782H1 14 INL Integral nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 AFE882H1, TA = –40°C to +125°C –12 12 LSB AFE882H1, TA = –40°C to +85°C –4 4 AFE782H1 –3 3 DNL Differential nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 –1 1 LSB TUE Total unadjusted error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Zero code error, no load TA = –40°C to +125°C 1 mV TA = –40°C to +85°C 1 TA = 25°C 0.5 Zero code error temperature coefficient ±3 ppm/°C Offset error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.07 0.07 %FSR TA = –40°C to +85°C –0.05 0.05 TA = 25°C –0.03 0.03 Offset error temperature coefficient #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm/°C Gain error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Gain error temperature coefficient#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm FSR/°C Full-scale error TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Full-scale error temperature coefficient ±3 ppm FSR/°C VOUT DAC DYNAMIC PERFORMANCE ts Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB 65 µs 10-mV step settling to ±2 LSB 30 Slew rate Full-scale transition measured from 10% to 90% 30 mV/µs Vn Output noise 0.1 Hz to 10 Hz, DAC at midscale 0.25 LSBpp 100-kHz bandwidth, DAC at midscale 32 µVrms Vn Output noise density Measured at 1 kHz, DAC at midscale, PVDD = 3 V 180 nV/√Hz Measured at 1 kHz, DAC at midscale, PVDD = 5 V 260 Power supply rejection ratio (ac) 200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. 85 dB Code change glitch impulse Midcode ±1 LSB (including feedthrough) 4.5 nV-s Code change glitch magnitude Midcode ±1 LSB (including feedthrough), PVDD = 5 V 1.5 mV Digital feedthrough At SCLK = 1 MHz, DAC output at midscale 1 nV-s VOUT DAC OUTPUT CHARACTERISTICS Output voltage 0 2.5 V VOUT alarm output high 2.35 2.5 2.65 V VOUT alarm output low 0.285 0.3 0.315 V RLOAD Resistive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 10 kΩ CLOAD Capacitive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 100 pF Load regulation DAC at midscale, –1 mA ≤ IOUT ≤ +1 mA 10 µV/mA Short-circuit current Full scale output shorted to GND 5 mA Zero output shorted to VDD 5 Output voltage headroom to PVDD DAC at full code, IOUT = 1 mA (sourcing) 200 mV ZO Large signal dc output impedance To GND, DAC at code 0 60 Ω DAC at midscale 10 mΩ DAC at code 65535 10 Output Hi-Z 500 kΩ Power supply rejection ratio (dc) DAC at midscale 0.1 mV/V Output voltage drift vs time, ideal VREF TA = 35°C, VOUT = midscale, 1000 hours ±5 ppmFSR DIAGNOSTIC ADC Input voltage 0 2.5 V Resolution 12 Bits DNL Differential nonlinearity Specified 12-bit monotonic –1 ±0.2 1 LSB INL Integral nonlinearity –4 ±1 4 LSB Offset error After calibration –10 ±1.6 10 LSB Gain error –0.8 ±0.13 0.8 %FSR Noise ±4 LSB Input capacitance 6 pF Input bias current ADC not converting –50 50 nA Acquisition time 52 µs Conversion time 210 µs Conversion rate 3.84 kSPS Temperature sensor accuracy 5 °C INTERNAL OSCILLATOR Frequency TA = –40°C to +125°C 1.2165 1.2288 1.2411 MHz HART MODEM RX_IN INPUT (HART MODE) Input voltage range External or internal reference source, design architecture. Signal applied at the input to the dc blocking capacitor. 0 1.5 VPP Receiver sensitivity Threshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter. 80 100 120 mVPP Carrier detect time 1200 Hz of carrier frequency present at the input before CD asserted 3 baud MOD_OUT OUTPUT (HART MODE) Output voltage Measured at MOD_OUT pin with 160-Ω load,ac-coupled (2.2 µF) 400 500 800 mVPP Mark frequency 1200 Hz Space frequency 2200 Hz Frequency error –40°C to +125°C –1 1 % Phase continuity error Design architecture 0 Degrees Minimum resistive load AC-coupled with 2.2 µF 160 Ω Transmit impedance RTS low, measured at the MOD_OUT pin,1-mA measurement current 25 mΩ Transmit impedance RTS high, measured at the MOD_OUT pin, ±200-nA measurement current 50 kΩ VOLTAGE REFERENCE INPUT ZVREFIO Reference input impedance (VREFIO) 125 kΩ CVREFIO Reference input capacitance (VREFIO) 100 pF VOLTAGE REFERENCE OUTPUT Output (initial accuracy)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 25°C 1.248 1.25 1.252 V Output drift#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = –40°C to +125°C 10 ppm/℃ Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Ω Output noise#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Hz to 10 Hz 7.5 µVPP Output noise density#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Measured at 10 kHz, reference load = 100 nF 200 nV/√Hz Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.1% VREF change from nominal 2.5 mA Sinking, 0.1% VREF change from nominal 0.3 Load regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0 mA to 2.5 mA 4 µV/mA COUT Stable output capacitance TA = –40°C to +125°C, ESR from 10 mΩ to 400 mΩ 70 100 130 nF Line regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 100 µV/V Output voltage drift vs time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 35°C, 1000 hours ±100 ppm Thermal hysteresis#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 1st cycle 500 µV Additional cycles 25 µV VDD VOLTAGE REGULATOR OUTPUT Output voltage 1.71 1.8 1.89 V Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.5 mA to 2.5 mA 3 Ω Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 1% VDD change from nominal 4 mA THERMAL ALARM Alarm trip point 130 °C Warning trip point 85 °C Hysteresis 12 °C Trip point absolute accuracy 5 °C Trip point relative accuracy 2 °C DIGITAL INPUT CHARACTERISTICS VIH High-level input voltage 0.7 V/IOVDD VIL Low-level input voltage 0.3 V/IOVDD Hysteresis voltage 0.05 V/IOVDD Input current –1.56 1.56 µA Pin capacitance Per pin 10 pF DIGITAL OUTPUT CHARACTERISTICS VOH High-level output voltage ISOURCE = 1 mA 0.8 V/IOVDD VOL Low-level output voltage ISINK = 1 mA 0.2 V/IOVDD VOL Open-drain low-level output voltage ISINK = 2 mA 0.3 V Output pin capacitance 10 pF POWER REQUIREMENTS IPVDD Current flowing into PVDD DAC at zero-scale, SPI static 180 220 µA IREFIO Internal reference current consumption 52 70 µA IHART HART Tx modem current consumption 10 µA IADC ADC current consumption ADC converting at 3.84 kSPS 10 µA CVDD Recommended VDD decoupling capacitance 1 10 µF IIOVDD Current flowing into IOVDD SPI static 10 25 µA IVREFIO Current flowing into VREFIO DAC at midscale code 10 µA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT VOUT DAC STATIC PERFORMANCE Resolution AFE882H1 16 Bits AFE782H1 14 INL Integral nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 AFE882H1, TA = –40°C to +125°C –12 12 LSB AFE882H1, TA = –40°C to +85°C –4 4 AFE782H1 –3 3 DNL Differential nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 –1 1 LSB TUE Total unadjusted error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Zero code error, no load TA = –40°C to +125°C 1 mV TA = –40°C to +85°C 1 TA = 25°C 0.5 Zero code error temperature coefficient ±3 ppm/°C Offset error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.07 0.07 %FSR TA = –40°C to +85°C –0.05 0.05 TA = 25°C –0.03 0.03 Offset error temperature coefficient #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm/°C Gain error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Gain error temperature coefficient#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm FSR/°C Full-scale error TA = –40°C to +125°C –0.1 0.1 %FSR TA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Full-scale error temperature coefficient ±3 ppm FSR/°C VOUT DAC DYNAMIC PERFORMANCE ts Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB 65 µs 10-mV step settling to ±2 LSB 30 Slew rate Full-scale transition measured from 10% to 90% 30 mV/µs Vn Output noise 0.1 Hz to 10 Hz, DAC at midscale 0.25 LSBpp 100-kHz bandwidth, DAC at midscale 32 µVrms Vn Output noise density Measured at 1 kHz, DAC at midscale, PVDD = 3 V 180 nV/√Hz Measured at 1 kHz, DAC at midscale, PVDD = 5 V 260 Power supply rejection ratio (ac) 200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. 85 dB Code change glitch impulse Midcode ±1 LSB (including feedthrough) 4.5 nV-s Code change glitch magnitude Midcode ±1 LSB (including feedthrough), PVDD = 5 V 1.5 mV Digital feedthrough At SCLK = 1 MHz, DAC output at midscale 1 nV-s VOUT DAC OUTPUT CHARACTERISTICS Output voltage 0 2.5 V VOUT alarm output high 2.35 2.5 2.65 V VOUT alarm output low 0.285 0.3 0.315 V RLOAD Resistive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 10 kΩ CLOAD Capacitive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 100 pF Load regulation DAC at midscale, –1 mA ≤ IOUT ≤ +1 mA 10 µV/mA Short-circuit current Full scale output shorted to GND 5 mA Zero output shorted to VDD 5 Output voltage headroom to PVDD DAC at full code, IOUT = 1 mA (sourcing) 200 mV ZO Large signal dc output impedance To GND, DAC at code 0 60 Ω DAC at midscale 10 mΩ DAC at code 65535 10 Output Hi-Z 500 kΩ Power supply rejection ratio (dc) DAC at midscale 0.1 mV/V Output voltage drift vs time, ideal VREF TA = 35°C, VOUT = midscale, 1000 hours ±5 ppmFSR DIAGNOSTIC ADC Input voltage 0 2.5 V Resolution 12 Bits DNL Differential nonlinearity Specified 12-bit monotonic –1 ±0.2 1 LSB INL Integral nonlinearity –4 ±1 4 LSB Offset error After calibration –10 ±1.6 10 LSB Gain error –0.8 ±0.13 0.8 %FSR Noise ±4 LSB Input capacitance 6 pF Input bias current ADC not converting –50 50 nA Acquisition time 52 µs Conversion time 210 µs Conversion rate 3.84 kSPS Temperature sensor accuracy 5 °C INTERNAL OSCILLATOR Frequency TA = –40°C to +125°C 1.2165 1.2288 1.2411 MHz HART MODEM RX_IN INPUT (HART MODE) Input voltage range External or internal reference source, design architecture. Signal applied at the input to the dc blocking capacitor. 0 1.5 VPP Receiver sensitivity Threshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter. 80 100 120 mVPP Carrier detect time 1200 Hz of carrier frequency present at the input before CD asserted 3 baud MOD_OUT OUTPUT (HART MODE) Output voltage Measured at MOD_OUT pin with 160-Ω load,ac-coupled (2.2 µF) 400 500 800 mVPP Mark frequency 1200 Hz Space frequency 2200 Hz Frequency error –40°C to +125°C –1 1 % Phase continuity error Design architecture 0 Degrees Minimum resistive load AC-coupled with 2.2 µF 160 Ω Transmit impedance RTS low, measured at the MOD_OUT pin,1-mA measurement current 25 mΩ Transmit impedance RTS high, measured at the MOD_OUT pin, ±200-nA measurement current 50 kΩ VOLTAGE REFERENCE INPUT ZVREFIO Reference input impedance (VREFIO) 125 kΩ CVREFIO Reference input capacitance (VREFIO) 100 pF VOLTAGE REFERENCE OUTPUT Output (initial accuracy)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 25°C 1.248 1.25 1.252 V Output drift#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = –40°C to +125°C 10 ppm/℃ Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Ω Output noise#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Hz to 10 Hz 7.5 µVPP Output noise density#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Measured at 10 kHz, reference load = 100 nF 200 nV/√Hz Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.1% VREF change from nominal 2.5 mA Sinking, 0.1% VREF change from nominal 0.3 Load regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0 mA to 2.5 mA 4 µV/mA COUT Stable output capacitance TA = –40°C to +125°C, ESR from 10 mΩ to 400 mΩ 70 100 130 nF Line regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 100 µV/V Output voltage drift vs time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 35°C, 1000 hours ±100 ppm Thermal hysteresis#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 1st cycle 500 µV Additional cycles 25 µV VDD VOLTAGE REGULATOR OUTPUT Output voltage 1.71 1.8 1.89 V Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.5 mA to 2.5 mA 3 Ω Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 1% VDD change from nominal 4 mA THERMAL ALARM Alarm trip point 130 °C Warning trip point 85 °C Hysteresis 12 °C Trip point absolute accuracy 5 °C Trip point relative accuracy 2 °C DIGITAL INPUT CHARACTERISTICS VIH High-level input voltage 0.7 V/IOVDD VIL Low-level input voltage 0.3 V/IOVDD Hysteresis voltage 0.05 V/IOVDD Input current –1.56 1.56 µA Pin capacitance Per pin 10 pF DIGITAL OUTPUT CHARACTERISTICS VOH High-level output voltage ISOURCE = 1 mA 0.8 V/IOVDD VOL Low-level output voltage ISINK = 1 mA 0.2 V/IOVDD VOL Open-drain low-level output voltage ISINK = 2 mA 0.3 V Output pin capacitance 10 pF POWER REQUIREMENTS IPVDD Current flowing into PVDD DAC at zero-scale, SPI static 180 220 µA IREFIO Internal reference current consumption 52 70 µA IHART HART Tx modem current consumption 10 µA IADC ADC current consumption ADC converting at 3.84 kSPS 10 µA CVDD Recommended VDD decoupling capacitance 1 10 µF IIOVDD Current flowing into IOVDD SPI static 10 25 µA IVREFIO Current flowing into VREFIO DAC at midscale code 10 µA VOUT DAC STATIC PERFORMANCE VOUT DAC STATIC PERFORMANCE Resolution AFE882H1 16 Bits ResolutionAFE882H116Bits AFE782H1 14 AFE782H114 INL Integral nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 AFE882H1, TA = –40°C to +125°C –12 12 LSB INLIntegral nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1AFE882H1, TA = –40°C to +125°CA–1212LSB AFE882H1, TA = –40°C to +85°C –4 4 AFE882H1, TA = –40°C to +85°CA–44 AFE782H1 –3 3 AFE782H1–33 DNL Differential nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 –1 1 LSB DNLDifferential nonlinearity#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1–11LSB TUE Total unadjusted error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR TUETotal unadjusted error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1TA = –40°C to +125°CA–0.10.1%FSR TA = –40°C to +85°C –0.08 0.08 TA = –40°C to +85°CA–0.080.08 TA = 25°C –0.05 0.05 TA = 25°CA–0.050.05 Zero code error, no load TA = –40°C to +125°C 1 mV Zero code error, no loadTA = –40°C to +125°CA1mV TA = –40°C to +85°C 1 TA = –40°C to +85°CA1 TA = 25°C 0.5 TA = 25°CA0.5 Zero code error temperature coefficient ±3 ppm/°C Zero code error temperature coefficient±3ppm/°C Offset error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.07 0.07 %FSR Offset error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1TA = –40°C to +125°CA–0.070.07%FSR TA = –40°C to +85°C –0.05 0.05 TA = –40°C to +85°CA–0.050.05 TA = 25°C –0.03 0.03 TA = 25°CA–0.030.03 Offset error temperature coefficient #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm/°C Offset error temperature coefficient #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1±3ppm/°C Gain error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 TA = –40°C to +125°C –0.1 0.1 %FSR Gain error#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1TA = –40°C to +125°CA–0.10.1%FSR TA = –40°C to +85°C –0.08 0.08 TA = –40°C to +85°CA–0.080.08 TA = 25°C –0.05 0.05 TA = 25°CA–0.050.05 Gain error temperature coefficient#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 ±3 ppm FSR/°C Gain error temperature coefficient#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER1±3ppm FSR/°C Full-scale error TA = –40°C to +125°C –0.1 0.1 %FSR Full-scale errorTA = –40°C to +125°CA–0.10.1%FSR TA = –40°C to +85°C –0.08 0.08 TA = –40°C to +85°CA–0.080.08 TA = 25°C –0.05 0.05 TA = 25°CA–0.050.05 Full-scale error temperature coefficient ±3 ppm FSR/°C Full-scale error temperature coefficient±3ppm FSR/°C VOUT DAC DYNAMIC PERFORMANCE VOUT DAC DYNAMIC PERFORMANCE ts Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB 65 µs ts sOutput voltage settling time¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB65µs 10-mV step settling to ±2 LSB 30 10-mV step settling to ±2 LSB30 Slew rate Full-scale transition measured from 10% to 90% 30 mV/µs Slew rateFull-scale transition measured from 10% to 90%30mV/µs Vn Output noise 0.1 Hz to 10 Hz, DAC at midscale 0.25 LSBpp Vn nOutput noise0.1 Hz to 10 Hz, DAC at midscale0.25LSBpp 100-kHz bandwidth, DAC at midscale 32 µVrms 100-kHz bandwidth, DAC at midscale32µVrms Vn Output noise density Measured at 1 kHz, DAC at midscale, PVDD = 3 V 180 nV/√Hz Vn nOutput noise densityMeasured at 1 kHz, DAC at midscale, PVDD = 3 V180nV/√Hz Hz Measured at 1 kHz, DAC at midscale, PVDD = 5 V 260 Measured at 1 kHz, DAC at midscale, PVDD = 5 V260 Power supply rejection ratio (ac) 200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. 85 dB Power supply rejection ratio (ac)200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale.85dB Code change glitch impulse Midcode ±1 LSB (including feedthrough) 4.5 nV-s Code change glitch impulseMidcode ±1 LSB (including feedthrough)4.5nV-s Code change glitch magnitude Midcode ±1 LSB (including feedthrough), PVDD = 5 V 1.5 mV Code change glitch magnitudeMidcode ±1 LSB (including feedthrough), PVDD = 5 V1.5mV Digital feedthrough At SCLK = 1 MHz, DAC output at midscale 1 nV-s Digital feedthroughAt SCLK = 1 MHz, DAC output at midscale1nV-s VOUT DAC OUTPUT CHARACTERISTICS VOUT DAC OUTPUT CHARACTERISTICS Output voltage 0 2.5 V Output voltage02.5V VOUT alarm output high 2.35 2.5 2.65 V VOUT alarm output high2.352.52.65V VOUT alarm output low 0.285 0.3 0.315 V VOUT alarm output low0.2850.30.315V RLOAD Resistive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 10 kΩ RLOAD LOADResistive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER410kΩ CLOAD Capacitive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 100 pF CLOAD LOADCapacitive load#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/A_1462557802_ELECTCHAR_FOOTER4100pF Load regulation DAC at midscale, –1 mA ≤ IOUT ≤ +1 mA 10 µV/mA Load regulationDAC at midscale, –1 mA ≤ IOUT ≤ +1 mAOUT10µV/mA Short-circuit current Full scale output shorted to GND 5 mA Short-circuit currentFull scale output shorted to GND5mA Zero output shorted to VDD 5 Zero output shorted to VDD5 Output voltage headroom to PVDD DAC at full code, IOUT = 1 mA (sourcing) 200 mV Output voltage headroom to PVDDDAC at full code, IOUT = 1 mA (sourcing)OUT200mV ZO Large signal dc output impedance To GND, DAC at code 0 60 Ω ZO OLarge signal dc output impedanceTo GND, DAC at code 060Ω DAC at midscale 10 mΩ DAC at midscale10mΩ DAC at code 65535 10 DAC at code 6553510 Output Hi-Z 500 kΩ Output Hi-Z500kΩ Power supply rejection ratio (dc) DAC at midscale 0.1 mV/V Power supply rejection ratio (dc)DAC at midscale0.1mV/V Output voltage drift vs time, ideal VREF TA = 35°C, VOUT = midscale, 1000 hours ±5 ppmFSR Output voltage drift vs time, ideal VREFTA = 35°C, VOUT = midscale, 1000 hoursA±5ppmFSR DIAGNOSTIC ADC DIAGNOSTIC ADC Input voltage 0 2.5 V Input voltage02.5V Resolution 12 Bits Resolution12Bits DNL Differential nonlinearity Specified 12-bit monotonic –1 ±0.2 1 LSB DNLDifferential nonlinearitySpecified 12-bit monotonic–1±0.21LSB INL Integral nonlinearity –4 ±1 4 LSB INLIntegral nonlinearity–4±14LSB Offset error After calibration –10 ±1.6 10 LSB Offset errorAfter calibration–10±1.610LSB Gain error –0.8 ±0.13 0.8 %FSR Gain error–0.8±0.130.8%FSR Noise ±4 LSB Noise±4LSB Input capacitance 6 pF Input capacitance6pF Input bias current ADC not converting –50 50 nA Input bias currentADC not converting–5050nA Acquisition time 52 µs Acquisition time52µs Conversion time 210 µs Conversion time210µs Conversion rate 3.84 kSPS Conversion rate3.84kSPS Temperature sensor accuracy 5 °C Temperature sensor accuracy5°C INTERNAL OSCILLATOR INTERNAL OSCILLATOR Frequency TA = –40°C to +125°C 1.2165 1.2288 1.2411 MHz FrequencyTA = –40°C to +125°CA1.21651.22881.2411MHz HART MODEM HART MODEM RX_IN INPUT (HART MODE) RX_IN INPUT (HART MODE) RX_IN INPUT (HART MODE) Input voltage range External or internal reference source, design architecture. Signal applied at the input to the dc blocking capacitor. 0 1.5 VPP Input voltage rangeExternal or internal reference source, design architecture. Signal applied at the input to the dc blocking capacitor.01.5VPP PP Receiver sensitivity Threshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter. 80 100 120 mVPP Receiver sensitivityThreshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter.80100120mVPP PP Carrier detect time 1200 Hz of carrier frequency present at the input before CD asserted 3 baud Carrier detect time1200 Hz of carrier frequency present at the input before CD asserted3baud MOD_OUT OUTPUT (HART MODE) MOD_OUT OUTPUT (HART MODE) MOD_OUT OUTPUT (HART MODE) Output voltage Measured at MOD_OUT pin with 160-Ω load,ac-coupled (2.2 µF) 400 500 800 mVPP Output voltageMeasured at MOD_OUT pin with 160-Ω load,ac-coupled (2.2 µF)400500800mVPP PP Mark frequency 1200 Hz Mark frequency1200Hz Space frequency 2200 Hz Space frequency2200Hz Frequency error –40°C to +125°C –1 1 % Frequency error–40°C to +125°C–11% Phase continuity error Design architecture 0 Degrees Phase continuity errorDesign architecture0Degrees Minimum resistive load AC-coupled with 2.2 µF 160 Ω Minimum resistive loadAC-coupled with 2.2 µF160Ω Transmit impedance RTS low, measured at the MOD_OUT pin,1-mA measurement current 25 mΩ Transmit impedance RTS low, measured at the MOD_OUT pin,1-mA measurement currentRTS25mΩ Transmit impedance RTS high, measured at the MOD_OUT pin, ±200-nA measurement current 50 kΩ Transmit impedance RTS high, measured at the MOD_OUT pin, ±200-nA measurement currentRTS±50kΩ VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT ZVREFIO Reference input impedance (VREFIO) 125 kΩ ZVREFIO VREFIOReference input impedance (VREFIO)125kΩ CVREFIO Reference input capacitance (VREFIO) 100 pF CVREFIO VREFIOReference input capacitance (VREFIO)100pF VOLTAGE REFERENCE OUTPUT VOLTAGE REFERENCE OUTPUT Output (initial accuracy)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 25°C 1.248 1.25 1.252 V Output (initial accuracy)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVHTA = 25°CA1.2481.251.252V Output drift#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = –40°C to +125°C 10 ppm/℃ Output drift#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVHTA = –40°C to +125°CA10ppm/℃ Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Ω Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH0.1Ω Output noise#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 0.1 Hz to 10 Hz 7.5 µVPP Output noise#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH0.1 Hz to 10 Hz7.5µVPP PP Output noise density#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Measured at 10 kHz, reference load = 100 nF 200 nV/√Hz Output noise density#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVHMeasured at 10 kHz, reference load = 100 nF200nV/√Hz Hz Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.1% VREF change from nominal 2.5 mA Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVHSourcing, 0.1% VREF change from nominal2.5mA Sinking, 0.1% VREF change from nominal 0.3 Sinking, 0.1% VREF change from nominal0.3 Load regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0 mA to 2.5 mA 4 µV/mA Load regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVHSourcing, 0 mA to 2.5 mA4µV/mA COUT Stable output capacitance TA = –40°C to +125°C, ESR from 10 mΩ to 400 mΩ 70 100 130 nF COUT OUTStable output capacitanceTA = –40°C to +125°C, ESR from 10 mΩ to 400 mΩA70100130nF Line regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 100 µV/V Line regulation#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH100µV/V Output voltage drift vs time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH TA = 35°C, 1000 hours ±100 ppm Output voltage drift vs time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVHTA = 35°C, 1000 hoursA±100ppm Thermal hysteresis#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH 1st cycle 500 µV Thermal hysteresis#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH1st cycle500µV Additional cycles 25 µV Additional cycles25µV VDD VOLTAGE REGULATOR OUTPUT VDD VOLTAGE REGULATOR OUTPUT Output voltage 1.71 1.8 1.89 V Output voltage1.711.81.89V Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 0.5 mA to 2.5 mA 3 Ω Output impedance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVHSourcing, 0.5 mA to 2.5 mA3Ω Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH Sourcing, 1% VDD change from nominal 4 mA Load current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVH #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000275820/SFAWOO51NZVHSourcing, 1% VDD change from nominal4mA THERMAL ALARM THERMAL ALARM Alarm trip point 130 °C Alarm trip point130°C Warning trip point 85 °C Warning trip point85°C Hysteresis 12 °C Hysteresis12°C Trip point absolute accuracy 5 °C Trip point absolute accuracy5°C Trip point relative accuracy 2 °C Trip point relative accuracy2°C DIGITAL INPUT CHARACTERISTICS DIGITAL INPUT CHARACTERISTICS VIH High-level input voltage 0.7 V/IOVDD VIH IHHigh-level input voltage0.7V/IOVDD VIL Low-level input voltage 0.3 V/IOVDD VIL ILLow-level input voltage0.3V/IOVDD Hysteresis voltage 0.05 V/IOVDD Hysteresis voltage0.05V/IOVDD Input current –1.56 1.56 µA Input current–1.561.56µA Pin capacitance Per pin 10 pF Pin capacitancePer pin10pF DIGITAL OUTPUT CHARACTERISTICS DIGITAL OUTPUT CHARACTERISTICS VOH High-level output voltage ISOURCE = 1 mA 0.8 V/IOVDD VOH OHHigh-level output voltageISOURCE = 1 mASOURCE0.8V/IOVDD VOL Low-level output voltage ISINK = 1 mA 0.2 V/IOVDD VOL OLLow-level output voltageISINK = 1 mASINK0.2V/IOVDD VOL Open-drain low-level output voltage ISINK = 2 mA 0.3 V VOL OLOpen-drain low-level output voltageISINK = 2 mASINK 0.3V Output pin capacitance 10 pF Output pin capacitance10pF POWER REQUIREMENTS POWER REQUIREMENTS IPVDD Current flowing into PVDD DAC at zero-scale, SPI static 180 220 µA IPVDD PVDDCurrent flowing into PVDDDAC at zero-scale, SPI static180220µA IREFIO Internal reference current consumption 52 70 µA IREFIO REFIOInternal reference current consumption5270µA IHART HART Tx modem current consumption 10 µA IHART HARTHART Tx modem current consumption10µA IADC ADC current consumption ADC converting at 3.84 kSPS 10 µA IADC ADCADC current consumptionADC converting at 3.84 kSPS10µA CVDD Recommended VDD decoupling capacitance 1 10 µF CVDD VDDRecommended VDD decoupling capacitance110µF IIOVDD Current flowing into IOVDD SPI static 10 25 µA IIOVDD IOVDDCurrent flowing into IOVDDSPI static1025µA IVREFIO Current flowing into VREFIO DAC at midscale code 10 µA IVREFIO VREFIOCurrent flowing into VREFIODAC at midscale code10µA End point fit between code 512 to code 65,535 for 16-bit, code 128 to code 16,383 for 14-bit, DAC output unloaded, performance under resistive and capacitive load conditions are specified by design and characterization. Not production tested. Design target. Not production tested. Derived from the characterization data. End point fit between code 512 to code 65,535 for 16-bit, code 128 to code 16,383 for 14-bit, DAC output unloaded, performance under resistive and capacitive load conditions are specified by design and characterization.Not production tested. Design target.Not production tested. Derived from the characterization data. Timing Requirements all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2, 2.7 V ≤ PVDD ≤ 5.5 V,VIH = 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V and TA = –40°C to +125°C (unless otherwise noted) PARAMETER MIN NOM MAX UNIT SERIAL INTERFACE - WRITE AND READ OPERATION fSCLK Serial clock frequency 12.5 MHz tSCLKHIGH SCLK high time 36 ns tSCLKLOW SCLK low time 36 ns tCSHIGH CS high time 80 ns tCSS CS to SCLK falling edge setup time 30 ns tCSH SCLK falling edge to CS rising edge 30 ns tCSRI CS rising edge to SCLK falling edge ignore 30 ns tCSFI SCLK falling edge ignore to CS falling edge 5 ns tSDIS SDI setup time 5 ns tSDIH SDI hold time 5 ns tSDOZD CS falling edge to SDO tri-state condition to driven 40 ns tSDODZ CS rising edge to SDO driven to tri-state condition 40 ns tSDODLY SCLK to SDO output delay 40 ns UART tBAUDUART Baud rate = 9600 ±1% 104 µs tBAUDUART Baud rate = 1200 ±1% 833 µs HART tBAUDHART Baud rate = 1200 ± 1% 833 µs DIGITAL LOGIC tDACWAIT Sequential DAC update wait time 2.1 µs tPOR POR reset delay 100 µs tRESET RESET pulse duration 100 ns tRESETWAIT Wait time after RESET pulse 10 µs tPULSE_GPIO GPIO input pulse duration 10 ns Timing Requirements all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2, 2.7 V ≤ PVDD ≤ 5.5 V,VIH = 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V and TA = –40°C to +125°C (unless otherwise noted) PARAMETER MIN NOM MAX UNIT SERIAL INTERFACE - WRITE AND READ OPERATION fSCLK Serial clock frequency 12.5 MHz tSCLKHIGH SCLK high time 36 ns tSCLKLOW SCLK low time 36 ns tCSHIGH CS high time 80 ns tCSS CS to SCLK falling edge setup time 30 ns tCSH SCLK falling edge to CS rising edge 30 ns tCSRI CS rising edge to SCLK falling edge ignore 30 ns tCSFI SCLK falling edge ignore to CS falling edge 5 ns tSDIS SDI setup time 5 ns tSDIH SDI hold time 5 ns tSDOZD CS falling edge to SDO tri-state condition to driven 40 ns tSDODZ CS rising edge to SDO driven to tri-state condition 40 ns tSDODLY SCLK to SDO output delay 40 ns UART tBAUDUART Baud rate = 9600 ±1% 104 µs tBAUDUART Baud rate = 1200 ±1% 833 µs HART tBAUDHART Baud rate = 1200 ± 1% 833 µs DIGITAL LOGIC tDACWAIT Sequential DAC update wait time 2.1 µs tPOR POR reset delay 100 µs tRESET RESET pulse duration 100 ns tRESETWAIT Wait time after RESET pulse 10 µs tPULSE_GPIO GPIO input pulse duration 10 ns all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2, 2.7 V ≤ PVDD ≤ 5.5 V,VIH = 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V and TA = –40°C to +125°C (unless otherwise noted) PARAMETER MIN NOM MAX UNIT SERIAL INTERFACE - WRITE AND READ OPERATION fSCLK Serial clock frequency 12.5 MHz tSCLKHIGH SCLK high time 36 ns tSCLKLOW SCLK low time 36 ns tCSHIGH CS high time 80 ns tCSS CS to SCLK falling edge setup time 30 ns tCSH SCLK falling edge to CS rising edge 30 ns tCSRI CS rising edge to SCLK falling edge ignore 30 ns tCSFI SCLK falling edge ignore to CS falling edge 5 ns tSDIS SDI setup time 5 ns tSDIH SDI hold time 5 ns tSDOZD CS falling edge to SDO tri-state condition to driven 40 ns tSDODZ CS rising edge to SDO driven to tri-state condition 40 ns tSDODLY SCLK to SDO output delay 40 ns UART tBAUDUART Baud rate = 9600 ±1% 104 µs tBAUDUART Baud rate = 1200 ±1% 833 µs HART tBAUDHART Baud rate = 1200 ± 1% 833 µs DIGITAL LOGIC tDACWAIT Sequential DAC update wait time 2.1 µs tPOR POR reset delay 100 µs tRESET RESET pulse duration 100 ns tRESETWAIT Wait time after RESET pulse 10 µs tPULSE_GPIO GPIO input pulse duration 10 ns all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2, 2.7 V ≤ PVDD ≤ 5.5 V,VIH = 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V and TA = –40°C to +125°C (unless otherwise noted)RFILIHIHILA PARAMETER MIN NOM MAX UNIT SERIAL INTERFACE - WRITE AND READ OPERATION fSCLK Serial clock frequency 12.5 MHz tSCLKHIGH SCLK high time 36 ns tSCLKLOW SCLK low time 36 ns tCSHIGH CS high time 80 ns tCSS CS to SCLK falling edge setup time 30 ns tCSH SCLK falling edge to CS rising edge 30 ns tCSRI CS rising edge to SCLK falling edge ignore 30 ns tCSFI SCLK falling edge ignore to CS falling edge 5 ns tSDIS SDI setup time 5 ns tSDIH SDI hold time 5 ns tSDOZD CS falling edge to SDO tri-state condition to driven 40 ns tSDODZ CS rising edge to SDO driven to tri-state condition 40 ns tSDODLY SCLK to SDO output delay 40 ns UART tBAUDUART Baud rate = 9600 ±1% 104 µs tBAUDUART Baud rate = 1200 ±1% 833 µs HART tBAUDHART Baud rate = 1200 ± 1% 833 µs DIGITAL LOGIC tDACWAIT Sequential DAC update wait time 2.1 µs tPOR POR reset delay 100 µs tRESET RESET pulse duration 100 ns tRESETWAIT Wait time after RESET pulse 10 µs tPULSE_GPIO GPIO input pulse duration 10 ns PARAMETER MIN NOM MAX UNIT PARAMETER MIN NOM MAX UNIT PARAMETERMINNOMMAXUNIT SERIAL INTERFACE - WRITE AND READ OPERATION fSCLK Serial clock frequency 12.5 MHz tSCLKHIGH SCLK high time 36 ns tSCLKLOW SCLK low time 36 ns tCSHIGH CS high time 80 ns tCSS CS to SCLK falling edge setup time 30 ns tCSH SCLK falling edge to CS rising edge 30 ns tCSRI CS rising edge to SCLK falling edge ignore 30 ns tCSFI SCLK falling edge ignore to CS falling edge 5 ns tSDIS SDI setup time 5 ns tSDIH SDI hold time 5 ns tSDOZD CS falling edge to SDO tri-state condition to driven 40 ns tSDODZ CS rising edge to SDO driven to tri-state condition 40 ns tSDODLY SCLK to SDO output delay 40 ns UART tBAUDUART Baud rate = 9600 ±1% 104 µs tBAUDUART Baud rate = 1200 ±1% 833 µs HART tBAUDHART Baud rate = 1200 ± 1% 833 µs DIGITAL LOGIC tDACWAIT Sequential DAC update wait time 2.1 µs tPOR POR reset delay 100 µs tRESET RESET pulse duration 100 ns tRESETWAIT Wait time after RESET pulse 10 µs tPULSE_GPIO GPIO input pulse duration 10 ns SERIAL INTERFACE - WRITE AND READ OPERATION SERIAL INTERFACE - WRITE AND READ OPERATION fSCLK Serial clock frequency 12.5 MHz fSCLK SCLKSerial clock frequency12.5MHz tSCLKHIGH SCLK high time 36 ns tSCLKHIGH SCLKHIGHSCLK high time36ns tSCLKLOW SCLK low time 36 ns tSCLKLOW SCLKLOWSCLK low time36ns tCSHIGH CS high time 80 ns tCSHIGH CSHIGH CS high timeCS80ns tCSS CS to SCLK falling edge setup time 30 ns tCSS CSS CS to SCLK falling edge setup timeCS30ns tCSH SCLK falling edge to CS rising edge 30 ns tCSH CSHSCLK falling edge to CS rising edgeCS30ns tCSRI CS rising edge to SCLK falling edge ignore 30 ns tCSRI CSRI CS rising edge to SCLK falling edge ignoreCS30ns tCSFI SCLK falling edge ignore to CS falling edge 5 ns tCSFI CSFISCLK falling edge ignore to CS falling edgeCS5ns tSDIS SDI setup time 5 ns tSDIS SDISSDI setup time5ns tSDIH SDI hold time 5 ns tSDIH SDIHSDI hold time5ns tSDOZD CS falling edge to SDO tri-state condition to driven 40 ns tSDOZD SDOZD CS falling edge to SDO tri-state condition to drivenCS40ns tSDODZ CS rising edge to SDO driven to tri-state condition 40 ns tSDODZ SDODZ CS rising edge to SDO driven to tri-state conditionCS40ns tSDODLY SCLK to SDO output delay 40 ns tSDODLY SDODLYSCLK to SDO output delay40ns UART UART tBAUDUART Baud rate = 9600 ±1% 104 µs tBAUDUART BAUDUARTBaud rate = 9600 ±1%104µs tBAUDUART Baud rate = 1200 ±1% 833 µs tBAUDUART BAUDUARTBaud rate = 1200 ±1%833µs HART HART tBAUDHART Baud rate = 1200 ± 1% 833 µs tBAUDHART BAUDHARTBaud rate = 1200 ± 1%833µs DIGITAL LOGIC DIGITAL LOGIC tDACWAIT Sequential DAC update wait time 2.1 µs tDACWAIT DACWAITSequential DAC update wait time2.1µs tPOR POR reset delay 100 µs tPOR PORPOR reset delay100µs tRESET RESET pulse duration 100 ns tRESET RESET RESET pulse durationRESET100ns tRESETWAIT Wait time after RESET pulse 10 µs tRESETWAIT RESETWAITWait time after RESET pulseRESET10µs tPULSE_GPIO GPIO input pulse duration 10 ns tPULSE_GPIO PULSE_GPIOGPIO input pulse duration10ns Timing Diagrams SPI Timing UBM Timing Timing Diagrams SPI Timing UBM Timing SPI Timing UBM Timing SPI Timing SPI Timing UBM Timing UBM Timing Typical Characteristics: VOUT DAC at TA = 25°C, PVDD = 2.7 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) DAC DNL vs Digital Input Code   MIN and MAX DAC DNL Range vs Temperature   DAC INL vs Digital Input Code   MIN and MAX DAC INL Range vs Temperature   DAC TUE vs Digital Input Code   MIN and MAX DAC TUE vs Temperature   Zero-code Impedance   DAC Footroom Over Temperature and Load   DAC Source and Sink Current Capability DAC at midcode DAC Output Voltage Long-Term Stability Ideal reference DAC Glitch Impulse Rising Edge PVDD = 5.5 V DAC Glitch Impulse Falling Edge PVDD = 5.5 V DAC Gain Error vs Temperature DAC Offset Error vs Temperature DAC Full Scale Error vs Temperature DAC Zero Scale Error vs Temperature DAC Output Noise, 0.1 Hz to 10 Hz DAC at midcode PVDD = 5.5 V DAC Output Noise Density vs Frequency DAC at midcode PVDD = 5.5 V DAC Rising Settling Time   DAC Falling Settling Time   DAC Settling Time With Linear Slew Rate Control   DAC Settling Time With Sinusoidal Slew Rate Control   DAC RESET Response   DAC Supply Power On, PVDD = 2.7 V   DAC AC PSRR vs Frequency Internal reference Typical Characteristics: VOUT DAC at TA = 25°C, PVDD = 2.7 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) DAC DNL vs Digital Input Code   MIN and MAX DAC DNL Range vs Temperature   DAC INL vs Digital Input Code   MIN and MAX DAC INL Range vs Temperature   DAC TUE vs Digital Input Code   MIN and MAX DAC TUE vs Temperature   Zero-code Impedance   DAC Footroom Over Temperature and Load   DAC Source and Sink Current Capability DAC at midcode DAC Output Voltage Long-Term Stability Ideal reference DAC Glitch Impulse Rising Edge PVDD = 5.5 V DAC Glitch Impulse Falling Edge PVDD = 5.5 V DAC Gain Error vs Temperature DAC Offset Error vs Temperature DAC Full Scale Error vs Temperature DAC Zero Scale Error vs Temperature DAC Output Noise, 0.1 Hz to 10 Hz DAC at midcode PVDD = 5.5 V DAC Output Noise Density vs Frequency DAC at midcode PVDD = 5.5 V DAC Rising Settling Time   DAC Falling Settling Time   DAC Settling Time With Linear Slew Rate Control   DAC Settling Time With Sinusoidal Slew Rate Control   DAC RESET Response   DAC Supply Power On, PVDD = 2.7 V   DAC AC PSRR vs Frequency Internal reference at TA = 25°C, PVDD = 2.7 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) DAC DNL vs Digital Input Code   MIN and MAX DAC DNL Range vs Temperature   DAC INL vs Digital Input Code   MIN and MAX DAC INL Range vs Temperature   DAC TUE vs Digital Input Code   MIN and MAX DAC TUE vs Temperature   Zero-code Impedance   DAC Footroom Over Temperature and Load   DAC Source and Sink Current Capability DAC at midcode DAC Output Voltage Long-Term Stability Ideal reference DAC Glitch Impulse Rising Edge PVDD = 5.5 V DAC Glitch Impulse Falling Edge PVDD = 5.5 V DAC Gain Error vs Temperature DAC Offset Error vs Temperature DAC Full Scale Error vs Temperature DAC Zero Scale Error vs Temperature DAC Output Noise, 0.1 Hz to 10 Hz DAC at midcode PVDD = 5.5 V DAC Output Noise Density vs Frequency DAC at midcode PVDD = 5.5 V DAC Rising Settling Time   DAC Falling Settling Time   DAC Settling Time With Linear Slew Rate Control   DAC Settling Time With Sinusoidal Slew Rate Control   DAC RESET Response   DAC Supply Power On, PVDD = 2.7 V   DAC AC PSRR vs Frequency Internal reference at TA = 25°C, PVDD = 2.7 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted)ALOADLOAD DAC DNL vs Digital Input Code   MIN and MAX DAC DNL Range vs Temperature   DAC INL vs Digital Input Code   MIN and MAX DAC INL Range vs Temperature   DAC TUE vs Digital Input Code   MIN and MAX DAC TUE vs Temperature   Zero-code Impedance   DAC Footroom Over Temperature and Load   DAC Source and Sink Current Capability DAC at midcode DAC Output Voltage Long-Term Stability Ideal reference DAC Glitch Impulse Rising Edge PVDD = 5.5 V DAC Glitch Impulse Falling Edge PVDD = 5.5 V DAC Gain Error vs Temperature DAC Offset Error vs Temperature DAC Full Scale Error vs Temperature DAC Zero Scale Error vs Temperature DAC Output Noise, 0.1 Hz to 10 Hz DAC at midcode PVDD = 5.5 V DAC Output Noise Density vs Frequency DAC at midcode PVDD = 5.5 V DAC Rising Settling Time   DAC Falling Settling Time   DAC Settling Time With Linear Slew Rate Control   DAC Settling Time With Sinusoidal Slew Rate Control   DAC RESET Response   DAC Supply Power On, PVDD = 2.7 V   DAC AC PSRR vs Frequency Internal reference DAC DNL vs Digital Input Code   DAC DNL vs Digital Input Code             MIN and MAX DAC DNL Range vs Temperature   MIN and MAX DAC DNL Range vs Temperature             DAC INL vs Digital Input Code   DAC INL vs Digital Input Code             MIN and MAX DAC INL Range vs Temperature   MIN and MAX DAC INL Range vs Temperature             DAC TUE vs Digital Input Code   DAC TUE vs Digital Input Code             MIN and MAX DAC TUE vs Temperature   MIN and MAX DAC TUE vs Temperature             Zero-code Impedance   Zero-code Impedance             DAC Footroom Over Temperature and Load   DAC Footroom Over Temperature and Load             DAC Source and Sink Current Capability DAC at midcode DAC Source and Sink Current Capability DAC at midcode DAC at midcode DAC at midcode DAC at midcode DAC at midcode DAC at midcode DAC Output Voltage Long-Term Stability Ideal reference DAC Output Voltage Long-Term Stability Ideal reference Ideal reference Ideal reference Ideal reference Ideal reference Ideal reference DAC Glitch Impulse Rising Edge PVDD = 5.5 V DAC Glitch Impulse Rising Edge PVDD = 5.5 V PVDD = 5.5 V PVDD = 5.5 V PVDD = 5.5 V PVDD = 5.5 V PVDD = 5.5 V DAC Glitch Impulse Falling Edge PVDD = 5.5 V DAC Glitch Impulse Falling Edge PVDD = 5.5 V PVDD = 5.5 V PVDD = 5.5 V PVDD = 5.5 V PVDD = 5.5 V PVDD = 5.5 V DAC Gain Error vs Temperature DAC Gain Error vs Temperature DAC Offset Error vs Temperature DAC Offset Error vs Temperature DAC Full Scale Error vs Temperature DAC Full Scale Error vs Temperature DAC Zero Scale Error vs Temperature DAC Zero Scale Error vs Temperature DAC Output Noise, 0.1 Hz to 10 Hz DAC at midcode PVDD = 5.5 V DAC Output Noise, 0.1 Hz to 10 Hz DAC at midcode PVDD = 5.5 V DAC at midcode PVDD = 5.5 V DAC at midcode PVDD = 5.5 V DAC at midcode PVDD = 5.5 V DAC at midcode PVDD = 5.5 V DAC at midcodePVDD = 5.5 V DAC Output Noise Density vs Frequency DAC at midcode PVDD = 5.5 V DAC Output Noise Density vs Frequency DAC at midcode PVDD = 5.5 V DAC at midcode PVDD = 5.5 V DAC at midcode PVDD = 5.5 V DAC at midcode PVDD = 5.5 V DAC at midcode PVDD = 5.5 V DAC at midcode PVDD = 5.5 V DAC Rising Settling Time   DAC Rising Settling Time             DAC Falling Settling Time   DAC Falling Settling Time             DAC Settling Time With Linear Slew Rate Control   DAC Settling Time With Linear Slew Rate Control             DAC Settling Time With Sinusoidal Slew Rate Control   DAC Settling Time With Sinusoidal Slew Rate Control             DAC RESET Response   DAC RESET ResponseRESET             DAC Supply Power On, PVDD = 2.7 V   DAC Supply Power On, PVDD = 2.7 V             DAC AC PSRR vs Frequency Internal reference DAC AC PSRR vs Frequency Internal reference Internal reference Internal reference Internal reference Internal reference Internal reference Typical Characteristics: ADC at TA = 25°C, PVDD = 3.3 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) ADC DNL vs Digital Input Code   ADC INL vs Digital Input Code   ADC DNL Range vs Temperature   ADC INL Range vs Temperature   ADC Offset Error vs Temperature   ADC Gain Error vs Temperature   Typical Characteristics: ADC at TA = 25°C, PVDD = 3.3 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) ADC DNL vs Digital Input Code   ADC INL vs Digital Input Code   ADC DNL Range vs Temperature   ADC INL Range vs Temperature   ADC Offset Error vs Temperature   ADC Gain Error vs Temperature   at TA = 25°C, PVDD = 3.3 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) ADC DNL vs Digital Input Code   ADC INL vs Digital Input Code   ADC DNL Range vs Temperature   ADC INL Range vs Temperature   ADC Offset Error vs Temperature   ADC Gain Error vs Temperature   at TA = 25°C, PVDD = 3.3 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted)ALOADLOAD ADC DNL vs Digital Input Code   ADC INL vs Digital Input Code   ADC DNL Range vs Temperature   ADC INL Range vs Temperature   ADC Offset Error vs Temperature   ADC Gain Error vs Temperature   ADC DNL vs Digital Input Code   ADC DNL vs Digital Input Code             ADC INL vs Digital Input Code   ADC INL vs Digital Input Code             ADC DNL Range vs Temperature   ADC DNL Range vs Temperature             ADC INL Range vs Temperature   ADC INL Range vs Temperature             ADC Offset Error vs Temperature   ADC Offset Error vs Temperature             ADC Gain Error vs Temperature   ADC Gain Error vs Temperature             Typical Characteristics: Reference at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Reference Voltage Temperature Drift Pre-soldered 30 units Reference Voltage Temperature Drift Post-soldered 30 units Multiple Temperature Cycle Hysteresis   –40°C to +85°C cycles, 60 minutes per cycle, 30 units Multiple Temperature Cycle Hysteresis –40°C to +85°C cycles, 60 minutes per cycle Ambient Temperature Change Settling Two minutes after 25°C to 85°C temperature step, 30 units Reference Voltage Long-Term Stability 30 units  Reference Output Noise, 0.1 Hz to 10 Hz   Reference AC PSRR vs frequency   Reference Source and Sink Current Capability   Initial Accuracy Distribution Typical Characteristics: Reference at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Reference Voltage Temperature Drift Pre-soldered 30 units Reference Voltage Temperature Drift Post-soldered 30 units Multiple Temperature Cycle Hysteresis   –40°C to +85°C cycles, 60 minutes per cycle, 30 units Multiple Temperature Cycle Hysteresis –40°C to +85°C cycles, 60 minutes per cycle Ambient Temperature Change Settling Two minutes after 25°C to 85°C temperature step, 30 units Reference Voltage Long-Term Stability 30 units  Reference Output Noise, 0.1 Hz to 10 Hz   Reference AC PSRR vs frequency   Reference Source and Sink Current Capability   Initial Accuracy Distribution at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Reference Voltage Temperature Drift Pre-soldered 30 units Reference Voltage Temperature Drift Post-soldered 30 units Multiple Temperature Cycle Hysteresis   –40°C to +85°C cycles, 60 minutes per cycle, 30 units Multiple Temperature Cycle Hysteresis –40°C to +85°C cycles, 60 minutes per cycle Ambient Temperature Change Settling Two minutes after 25°C to 85°C temperature step, 30 units Reference Voltage Long-Term Stability 30 units  Reference Output Noise, 0.1 Hz to 10 Hz   Reference AC PSRR vs frequency   Reference Source and Sink Current Capability   Initial Accuracy Distribution at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted)ALOADLOAD Reference Voltage Temperature Drift Pre-soldered 30 units Reference Voltage Temperature Drift Post-soldered 30 units Multiple Temperature Cycle Hysteresis   –40°C to +85°C cycles, 60 minutes per cycle, 30 units Multiple Temperature Cycle Hysteresis –40°C to +85°C cycles, 60 minutes per cycle Ambient Temperature Change Settling Two minutes after 25°C to 85°C temperature step, 30 units Reference Voltage Long-Term Stability 30 units  Reference Output Noise, 0.1 Hz to 10 Hz   Reference AC PSRR vs frequency   Reference Source and Sink Current Capability   Initial Accuracy Distribution Reference Voltage Temperature Drift Pre-soldered 30 units Reference Voltage Temperature Drift Pre-soldered 30 units Pre-soldered 30 units Pre-soldered 30 units Pre-soldered 30 units Pre-soldered 30 units Pre-soldered30 units Reference Voltage Temperature Drift Post-soldered 30 units Reference Voltage Temperature Drift Post-soldered 30 units Post-soldered 30 units Post-soldered 30 units Post-soldered 30 units Post-soldered 30 units Post-soldered30 units Multiple Temperature Cycle Hysteresis   –40°C to +85°C cycles, 60 minutes per cycle, 30 units Multiple Temperature Cycle Hysteresis   –40°C to +85°C cycles, 60 minutes per cycle, 30 units   –40°C to +85°C cycles, 60 minutes per cycle, 30 units   –40°C to +85°C cycles, 60 minutes per cycle, 30 units   –40°C to +85°C cycles, 60 minutes per cycle, 30 units     –40°C to +85°C cycles, 60 minutes per cycle, 30 units –40°C to +85°C cycles, 60 minutes per cycle, 30 units Multiple Temperature Cycle Hysteresis –40°C to +85°C cycles, 60 minutes per cycle Multiple Temperature Cycle Hysteresis –40°C to +85°C cycles, 60 minutes per cycle –40°C to +85°C cycles, 60 minutes per cycle –40°C to +85°C cycles, 60 minutes per cycle –40°C to +85°C cycles, 60 minutes per cycle –40°C to +85°C cycles, 60 minutes per cycle –40°C to +85°C cycles, 60 minutes per cycle Ambient Temperature Change Settling Two minutes after 25°C to 85°C temperature step, 30 units Ambient Temperature Change Settling Two minutes after 25°C to 85°C temperature step, 30 units Two minutes after 25°C to 85°C temperature step, 30 units Two minutes after 25°C to 85°C temperature step, 30 units Two minutes after 25°C to 85°C temperature step, 30 units Two minutes after 25°C to 85°C temperature step, 30 units Two minutes after 25°C to 85°C temperature step, 30 units Reference Voltage Long-Term Stability 30 units  Reference Voltage Long-Term Stability 30 units  30 units  30 units  30 units  30 units  30 units  Reference Output Noise, 0.1 Hz to 10 Hz   Reference Output Noise, 0.1 Hz to 10 Hz             Reference AC PSRR vs frequency   Reference AC PSRR vs frequency             Reference Source and Sink Current Capability   Reference Source and Sink Current Capability             Initial Accuracy Distribution Initial Accuracy Distribution Typical Characteristics: HART Modem at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) HART Internal Mode First Stage Band-Pass Filter Response (From HART_RX Signal to RX_INF Pin)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground HART Internal Mode Complete Band-Pass Filter Response (From HART_RX Signal to Internal Demodulator)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground Typical Characteristics: HART Modem at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) HART Internal Mode First Stage Band-Pass Filter Response (From HART_RX Signal to RX_INF Pin)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground HART Internal Mode Complete Band-Pass Filter Response (From HART_RX Signal to Internal Demodulator)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) HART Internal Mode First Stage Band-Pass Filter Response (From HART_RX Signal to RX_INF Pin)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground HART Internal Mode Complete Band-Pass Filter Response (From HART_RX Signal to Internal Demodulator)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted)ALOADLOAD HART Internal Mode First Stage Band-Pass Filter Response (From HART_RX Signal to RX_INF Pin)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground HART Internal Mode Complete Band-Pass Filter Response (From HART_RX Signal to Internal Demodulator)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground HART Internal Mode First Stage Band-Pass Filter Response (From HART_RX Signal to RX_INF Pin)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground HART Internal Mode First Stage Band-Pass Filter Response (From HART_RX Signal to RX_INF Pin)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground  2.2 nF HART_RX 680 pF RX_INF  2.2 nF HART_RX680 pF RX_INF Input Capacitor Capacitor to Ground Input CapacitorCapacitor to Ground HART Internal Mode Complete Band-Pass Filter Response (From HART_RX Signal to Internal Demodulator)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground HART Internal Mode Complete Band-Pass Filter Response (From HART_RX Signal to Internal Demodulator)  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground  2.2 nF HART_RX 680 pF RX_INF Input Capacitor Capacitor to Ground  2.2 nF HART_RX 680 pF RX_INF  2.2 nF HART_RX680 pF RX_INF Input Capacitor Capacitor to Ground Input CapacitorCapacitor to Ground Typical Characteristics: Power Supply at TA = 25°C, PVDD = IOVDD = 3.3 V, internal VREFIO, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) PVDD Supply Current vs Temperature   IOVDD Supply Current vs Temperature   VDD Voltage vs Load Current   Typical Characteristics: Power Supply at TA = 25°C, PVDD = IOVDD = 3.3 V, internal VREFIO, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) PVDD Supply Current vs Temperature   IOVDD Supply Current vs Temperature   VDD Voltage vs Load Current   at TA = 25°C, PVDD = IOVDD = 3.3 V, internal VREFIO, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) PVDD Supply Current vs Temperature   IOVDD Supply Current vs Temperature   VDD Voltage vs Load Current   at TA = 25°C, PVDD = IOVDD = 3.3 V, internal VREFIO, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted)ALOADLOAD PVDD Supply Current vs Temperature   IOVDD Supply Current vs Temperature   VDD Voltage vs Load Current   PVDD Supply Current vs Temperature   PVDD Supply Current vs Temperature             IOVDD Supply Current vs Temperature   IOVDD Supply Current vs Temperature             VDD Voltage vs Load Current   VDD Voltage vs Load Current             Detailed Description Overview The AFEx82H1 feature a 16-bit (AFE882H1) or 14‑bit (AFE782H1) string DAC with voltage output buffer. Both devices have a buffered voltage output and are designed for use in three‑wire or four-wire sensor transmitters or analog output modules. The DAC has calibration registers for setting gain and offset values for adjusting the DAC outputs. The DAC also has different output slewing modes that allow for a programmable linear slew and a sinusoidal shaped output slew. The AFEx82H1 also feature a 12‑bit SAR ADC that can be multiplexed to measure different inputs, including external nodes and internal nodes for diagnostic measurements on the device. The ADC is capable of making direct-mode measurements with on-demand conversions or auto-mode measurements through continuous conversions using a channel sequencer with a multiplexer. The devices have optional alarm configurations with fault detection and alarm actions. Device communication and programming are done through an SPI, SPI plus a UART interface, or through the UART break mode (UBM). With the SPI, a cyclic redundancy check (CRC) is implemented by default, which can be disabled. Additionally, communications can be monitored with a watchdog timer (WDT) that alerts the user if the device becomes unresponsive to periodic communication. For the field transmitter, a HART interface is created through modulation and demodulation using the SPI or UART. The demodulation of the input signal is done using the combination of the external and internal band-pass filtering. The AFEx82H1 feature a 1.25-V, onboard precision voltage reference, and an integrated precision oscillator. Throughout this data sheet, register and bit names are combined with a period to use the following format: <register_name>.<bit_name>. For example, the CLR bit in the DAC_CFG register is labeled DAC_CFG.CLR. Functional Block Diagram Feature Description Digital-to-Analog Converter (DAC) Overview The AFEx82H1 feature a 16-bit (AFE882H1) or 14‑bit (AFE782H1) string DAC followed by an output voltage buffer. Using an external circuit, the device output voltage can be translated to different output voltages and output currents for use in 3‑wire or 4-wire sensor transmitters or analog output modules. The DAC is configured to support a 0‑V to 2.5‑V range of operation. The alarm function is triggered when PVDD exceeds the valid configuration range of 2.7 V to 5.5 V; see also . DAC Resistor String shows that the resistor string structure consists of a series of resistors, each of value R. The code loaded to the DAC determines the node on the string at which the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. The resistor string architecture has inherent monotonicity, voltage output, and low glitch. DAC Resistor String DAC Buffer Amplifier The VOUT output pin is driven by the DAC output buffer amplifier. The output amplifier default settings are designed to drive capacitive loads as high as 100 pF without oscillation. The output buffer is able to source and sink 1 mA. The device implements short-circuit protection for momentary output shorts to ground and VDD supply. The source and sink short-circuit current thresholds are set to 5 mA. DAC Transfer Function The following equation describes the DAC transfer function, which is the relationship between internal signal DAC_CODE and output voltage VOUT: V O U T = D A C _ C O D E 2 N × F S R where DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N – 1. N = DAC_CODE resolution in bits (16 for the AFE882H1 and 14 for the AFE782H1). FSR = VOUT full-scale range = 2.5 V. DAC Gain and Offset Calibration The AFEx82H1 provide DAC gain and offset calibration capability to correct for end-point errors present in the system. Implement the gain and offset calibration using two registers, DAC_GAIN.GAIN and DAC_OFFSET.OFFSET. Update DAC_DATA register after gain or offset codes are changed for the new values to take effect. The DAC_GAIN can be programmed from 0.5 to 1.499985 using . D A C _ G A I N = 1 2 + G A I N 2 N where N = DAC_GAIN resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. GAIN is the decimal value of the DAC_GAIN register setting. GAIN data are left justified; the last two LSBs in the DAC_GAIN register are ignored for the AFE782H1. The example DAC_GAIN settings for the AFE882H1 are shown in . DAC_GAIN Setting vs GAIN Code DAC_GAIN GAIN (HEX) 0.5 0x0000 1.0 0x8000 1.499985 0xFFFF The DAC_OFFSET is stored in the DAC_OFFSET register using 2's-complement encoding. The DAC_OFFSET value can be programmed from –2(N–1) to 2(N–1) – 1 using . D A C _ O F F S E T = - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i where N = DAC_OFFSET resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. OFFSETMSB = MSB bit of the DAC_OFFSET register. OFFSET i = The rest of the bits of the DAC_OFFSET register. i = Position of the bit in the DAC_OFFSET register. OFFSET data are left justified; the last two LSBs in the DAC_OFFSET register are ignored for the device. The most significant bit determines the sign of the number and is called the sign bit. The sign bit has the weight of –2(N–1) as shown in . The example DAC_OFFSET settings for the AFE882H1 are shown in . DAC_OFFSET Setting vs OFFSET Code DAC_OFFSET OFFSET (HEX) 32767 0x7FFF 1 0x0001 0 0x0000 –1 0xFFFF –2 0xFFFE –32768 0x8000 The following transfer function is applied to the DAC_DATA.DATA based on the DAC_GAIN and DAC_OFFSET values: D A C _ C O D E = ( D A T A × D A C _ G A I N ) + D A C _ O F F S E T where DAC_CODE is the internal signal applied to the DAC. DATA is the decimal value of the DAC_DATA register. DAC_GAIN and DAC_OFFSET are the user calibration settings. DATA data are left justified; the last two LSBs in the DAC_DATA register are ignored for the AFE782H1. Substituting DAC_GAIN and DAC_OFFSET in with and results in: D A C _ C O D E = ( D A T A × 1 2 + G A I N 2 N ) - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i The multiplier is implemented using truncation instead of rounding. This truncation can cause a difference of one LSB if rounding is expected. shows the DAC calibration path. DAC Calibration Path Programmable Slew Rate The slew rate feature controls the rate at which the output voltage or current changes. This feature is disabled by default and is enabled by writing a logic 1 to the DAC_CFG.SR_EN bit. With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load. With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by DAC_CFG.SR_STEP[2:0] and DAC_CFG.SR_CLK[2:0]. SR_CLK defines the rate at which the digital slew updates. SR_STEP defines the amount by which the output value changes at each update. The register descriptions show different settings for SR_STEP and SR_CLK. The time required for the output to slew is expressed as : S l e w   T i m e   =   D e l t a   C o d e   C h a n g e S l e w   S t e p   ×   S l e w   C l o c k   R a t e where Slew Time is expressed in seconds Slew Step is controlled by DAC_CFG.SR_STEP Slew Clock Rate is controlled by DAC_CFG.SR_CLK When the slew-rate control feature is enabled, the output changes at the programmed slew rate. This configuration results in a staircase formation at the output. If the clear code is asserted (see ), the output slews to the DAC_CLR_CODE value at the programmed slew rate. When new DAC data are written, the output starts slewing to the new value at the slew rate determined by the current DAC code and the new DAC data. Two slew-rate control modes are available: linear (default) and sinusoidal. and show the typical rising and falling DAC output waveforms, respectively. Linear Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Linear Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt Sinusoidal mode enables fast DAC settling while improving analog rate of change characteristics. Sinusoidal mode is selected by the DAC_CFG.SR_MODE bit. and show the typical rising and falling DAC output waveforms with sinusoidal slew-rate control, respectively. Sinusoidal Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Sinusoidal Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt If the slew-rate feature is disabled while the DAC is executing the slew-rate command, the slew-rate operation is aborted, and the DAC output goes to the target code. DAC Register Structure and CLEAR State The AFE882H1 DAC has a 16-bit voltage output, and the AFE782H1 DAC has a 14-bit voltage output. The output range is 0 V to 2.5 V. The AFEx82H1 provide the option to quickly set the DAC output to the value set in the DAC_CLR_CODE register without writing to the DAC_DATA register, referred to as the CLEAR state. For register details, see . Transitioning from the DAC_DATA to the DAC_CLR_CODE is synchronous to the clock. If slew mode is enabled, the output slews during the transition. shows the full AFEx82H1 DAC_DATA signal path. The devices synchronize the DAC_DATA code to the internal clock, causing up to 2.5 internal clock cycles of latency (2 μs) with respect to the rising edge of CS or the end of a UBM command. Update DAC_GAIN and DAC_OFFSET values when DAC_CFG.SR_EN = 0 to avoid an IRQ pulse generated by SR_BUSY. Set the DAC to CLEAR state either by: Setting DAC_CFG.CLR. Configuring the DAC to transition to the CLEAR state in response to an alarm condition. Using the SDI pin in UBM as the CLEAR state input pin. Method 1 is a direct command to the AFEx82H1 to set the DAC to CLEAR state. Set the DAC_CFG.CLR bit to 1h to set the DAC to CLEAR state. Method 2 is controlled by settings of ALARM_ACT register. For details of conditions and other masks required to use this method, see and . Method 3 supports setting the DAC to CLEAR state without writing to the AFEx82H1. This pin-based DAC CLEAR state function is available only in UBM on the SDI pin. For details of connection options based on communication modes and pins used in each mode, see . Set the appropriate pin high to drive the DAC to CLEAR state. DAC Data Path Analog-to-Digital Converter (ADC) Overview The AFEx82H1 feature a monitoring system centered on a 12-bit successive approximation register (SAR) ADC and a highly flexible analog multiplexer. The monitoring system is capable of sensing up to two external inputs, as well as several internal device signals. The ADC uses the VREFIO pin voltage as a reference. The ADC timing signals are derived from an on-chip oscillator. The conversion results are accessed through the device serial interface. ADC Operation The device ADC supports direct-mode and auto-mode conversions. Both conversion modes use a custom channel sequencer to determine which of the input channels are converted by the ADC. The sequence order is fixed. The user selects the start channel and stop channel of the conversion sequence. The conversion method and channel sequence are specified in the ADC Configuration registers. The default conversion method is auto-mode. shows the ADC conversion sequence. ADC Conversion Sequence To use the ADC, first enable the ADC buffer by setting ADC_CFG.BUF_PD = 0. Then wait at least 210 μs before setting the trigger using the TRIGGER.ADC bit. An internal delay is forced if the trigger signal is sent before the timer has expired. Make sure the ADC is not converting before setting the ADC_CFG.BUF_PD = 1. If ADC_CFG.BUF_PD is set to 1 while the ADC is still converting, the internal timer delays this command. When the timer expires, the enable signal for the ADC is cleared, and the current conversion finishes before powering down the ADC and the ADC Buffer. A trigger signal must occur for the ADC to exit the idle state. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode conversion, the selected ADC input channels are converted on demand by issuing an ADC trigger signal. After the last enabled channel is converted, the ADC enters the idle state and waits for a new trigger. Read the results of the ADC conversion through the register map. Direct-mode conversion is typically used to gather the ADC data of any of the data channels. In direct-mode, use the ADC_BUSY bit to determine when a direct-mode conversion is complete and the ADC has returned to the idle state. Direct mode is set by writing ADC_CFG.DIRECT_MODE = 1. In auto-mode conversion, the selected ADC input channels are converted continuously. The conversion cycle is initiated by issuing an ADC trigger. Upon completion of the first conversion sequence, another sequence is automatically started. Conversion of the selected channels occurs repeatedly until the auto-mode conversion is stopped by clearing the ADC trigger signal. Auto-mode conversion is not typically used to gather the ADC data. Instead, auto-mode conversions are used in combination with upper and lower ADC data thresholds to detect when the data has exceeded the programmable out-of-range alarm thresholds. Auto mode is set by writing ADC_CFG.DIRECT_MODE = 0. Regardless of the selected conversion method, update the ADC configuration register only while the ADC is in the idle state. Do not change the ADC configuration bits while the ADC is converting channels. Before changing configuration bits, disable the ADC and verify that GEN_STATUS.ADC_BUSY = 0. ADC Custom Channel Sequencer The device uses a custom channel sequencer to control the multiplexer of the ADC. The ADC sequencer allows the user to specify which channels are converted. The sequencer consists of 16 indexed slots with programmable start and stop index fields to configure the start and stop conversion points. In direct-mode conversion, the ADC converts from the start index to the stop index once and then stops. In auto-mode conversion, the ADC converts from the start to stop index repeatedly until the ADC is stopped. shows the indexed custom channel sequence slots available in the device. ADC MUX Control lists the ADC input channel assignments for the sequencer. Indexed Custom Channel Sequence CCS POINTER CHANNEL CONV_RATE RANGE 0 OFFSET 2560 Hz VREF 1 AIN0 Programmable Programmable 2 AIN1 Programmable Programmable 3 TEMP 2560 Hz VREF 4 SD0 (VREF) 2560 Hz VREF 5 SD1 (PVDD) 2560 Hz VREF 6 SD2 (VDD) 2560 Hz VREF 7 SD3 (ZTAT) 2560 Hz VREF 8 SD4 (VOUT) 2560 Hz 2 × VREF 9-15 GND 2560 Hz VREF Use the ADC_INDEX_CFG register to select the channels. The order of the channels is fixed and shown in . Then, use ADC_INDEX_CFG.START and ADC_INDEX_CFG.STOP to select the range of indices to convert. If these two values are the same, then the ADC only converts a single channel. If the START and STOP values are different, then the ADC cycles through the corresponding indices. By default, all channels are configured to be converted; START = 0 and STOP = 8. If the AIN1 channel is not configured as an ADC input, then the result for this channel is 0x000. The minimum time for a conversion is still allotted to AIN1 if the channel is within the START and STOP range. If START is configured to be greater than STOP, then the device interprets the conversion sequence as if START = STOP. In direct mode, each selected channel in the ADC_INDEX_CFG register is converted once per TRIGGER.ADC command. In auto mode, each channel selected in the ADC_INDEX_CFG register is converted once; after the last channel, the loop is repeated as long as the ADC is enabled. In auto mode, writing to TRIGGER.ADC = 1 starts the conversions. Writing TRIGGER.ADC = 0 disables the ADC after the current channel being converted finishes. In direct mode, writing TRIGGER.ADC = 1 starts the sequence. When the sequence ends, then TRIGGER.ADC is self-cleared. A minimum of 20 clock cycles is required to perform one conversion. The ADC clock is derived from the internal oscillator and divided by 16, which gives an ADC clock frequency of 1.2288 MHz / 16 = 76.8 kHz, for a clock period = 13.02 μs. Each of the internal nodes has a fixed conversion rate. Pins AIN0 and AIN1 have programmable conversion rates (see also the ADC_CFG register). Pins AIN0 and AIN1 also have a configurable range. The input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit. If any ADC configuration bits are changed, the following sequence is recommended: Disable the ADC Wait for ADC_BUSY to go low Change the configuration Restart the conversions ADC_BUSY can be monitored in the GEN_STATUS register. If the ADC is configured for direct mode (ADC_CFG.DIRECT_MODE = 1), then after setting the desired channels to convert, write a 1 to TRIGGER.ADC. This bit is self-cleared when the sequence is finished converting. This command converts all the selected channels once. To initiate another conversion of the channels, send another TRIGGER.ADC command. ADC Synchronization The trigger signal must be generated for the ADC to exit the idle state and start conversions. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode, use the GEN_STATUS.ADC_BUSY bit to determine when a direct-mode conversion is complete, and the ADC has returned to the idle state. Similarly, monitor the TRIGGER.ADC bit to see if the ADC has returned to the idle state. ADC Offset Calibration Channel 0 of the CCS pointer is named OFFSET. The OFFSET channel is used to calibrate and improve the ADC offset performance. Convert the OFFSET channel, and use the result as a calibration for the ADC offset in subsequent measurements. This ADC channel samples VREF / 2 and compares this result against 7FFh as a measure of the ADC offset. The data rate for the ADC measuring this channel is 2560 Hz. The ADC conversion for the OFFSET channel is subtracted from 7FFh and the resulting value is stored in ADC_OFFSET (28h). The offset can be positive or negative; therefore, the value is stored in 2’s complement notation. With the subtraction from 7FFh, ADC_OFFSET is the negative of the offset. This value is subtracted from conversions of the ADC by default. For direct measurements of the ADC, set ADC_BYP.OFST_BYP_EN to 1 to enable the offset bypass; see . External Monitoring Inputs The AFEx82H1 have two analog inputs for external voltage sensing. Channels 1 and 2 for the CCS pointer are for external monitoring inputs that can be measured by pins AIN0 and AIN1, respectively. The input range for the analog inputs is configurable to either 0 V to 1.25 V or 0 V to 2.5 V. The analog inputs conversion values are stored in straight binary format in the ADC registers. The ADC resolution can be computed by : 1   L S B = V R A N G E 2 12 where VRANGE = 2.5 V for the 0‑V to 2.5‑V input range or 1.25 V for the 0‑V to 1.25‑V input range. and detail the transfer characteristics. ADC Transfer Characteristics Transfer Characteristics INPUT VOLTAGE CODE DESCRIPTION IDEAL OUTPUT CODE ≤1 LSB NFSC Negative full-scale code 000 1 LSB to 2 LSB NFSC + 1 Negative full-scale code plus 1 001 (VRANGE / 2) to (VRANGE / 2) + 1 LSB MC Midcode 800 (VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSB MC + 1 Midcode plus 1 801 ≥ VRANGE – 1 LSB PFSC Positive full-scale code FFF For these external monitoring inputs, the ADC is configurable for both data rate and voltage range. The data rate is set to either 640 Hz, 1280 Hz, 2560 Hz, or 3840 Hz with the ADC_CFG.CONV_RATE bits. The range of the ADC measurement is set with the ADC_CFG.AIN_RANGE bit. The ADC range is 2 × VREF when the bit = 0; the ADC range is VREF when the bit = 1. When the ADC conversion is completed for AIN0 and AIN1, the resulting ADC data are stored in the ADC_AIN0.DATA and ADC_AIN1.DATA bits at 24h and 25h of the register map. If the external monitoring inputs are not used, connect the AIN0 and AIN1 pins to GND through a 1-kΩ resistor. Temperature Sensor Channel 3 of the CCS is used to measure the die temperature of the device. The ADC measures an internal temperature sensor that measures a voltage complementary to the absolute temperature (CTAT). This CTAT voltage has a negative temperature coefficient. The ADC converts this voltage at a data rate of 2560 Hz. When the ADC conversion is completed, the data are found in the ADC_TEMP.DATA bits (address 26h). The relationship between the ambient temperature and the ADC code is shown in #GUID-A307B900-C147-485E-AF3B-AFFF3E5B4EBD/GUID-09CDF47B-A831-42BA-B93C-B59905D9CECB: ADC Code = 2681   - 11 × T A ( ° C ) Self-Diagnostic Multiplexer In addition to the ADC offset, the two external monitoring inputs, and the temperature sensor, the ADC of the AFEx82H1 has five other internal inputs to monitor the reference voltage, the power supplies, a static voltage, and the DAC output. These five voltages measurements are part of the self-diagnostic multiplexer (SD0 to SD4) measurements of the ADC, and are reported in the ADC_SD_MUX register at 27h; see also . Channel 4 (SD0) measures the reference voltage of the device. The ADC measures the reference voltage through a resistor divider (divide by two). Be aware that all ADC measurements are a function of the reference; using SD0 to measure the reference is not revealing as a diagnostic measurement. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 5 (SD1) measures the PVDD power supply of the device. The ADC measures the PVDD voltage through a resistor divider (divide by six). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 6 (SD2) measures the VDD power supply of the device. When channel 6 is selected, the ADC measures the VDD voltage through a resistor divider (divide by 2). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 7 (SD3) is a ZTAT (zero temperature coefficient) voltage. This internal voltage is nominally 0.6 V with a low temperature drift and does not depend on the reference voltage. An ADC measurement of ZTAT voltage can be useful to determine the state of the reference voltage. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 8 (SD4) measures the VOUT of the DAC. The ADC measures the VOUT voltage through a resistor divider (divide by two). The data rate for this conversion is 2560 Hz and the range of the ADC is set to 2 × VREF. ADC Bypass To test the offset, modify the ADC data path by programming the bypass data register, ADC_BYP.DATA (2Eh). This read/write register is used in two different ways. First, by setting the ADC_BYP.OFST_BYP_EN to 1, this bypass data register is used as a substitute for the ADC_OFFSET. However, if the ADC_BYP.DATA data must be stored in the ADC_OFFSET register, use the second method. Second, the ADC_BYP.DATA is used to set a known value into the ADC readback register of the channel being converted. Write the desired data into ADC_BYP.DATA, set the ADC_BYP.DATA_BYP_EN bit, and convert the selected channel. When ADC_BYP.DATA_BYP_EN bit is set to 1, the ADC conversion is bypassed, and the value of ADC_BYP.DATA is written into the selected ADC channel readback register. This setting is used to test the alarm settings of the ADC. When the ADC bypass is unused, set the ADC_BYP.DATA to 000h. shows the ADC bypass data flow. ADC Bypass Data Flow Programmable Out-of-Range Alarms The AFEx82H1 are capable of continuously analyzing the supplies, external ADC inputs, DAC output voltage, reference, internal temperature, and other internal signals for normal operation. Normal operation for the conversion results is established through the lower- and upper-threshold registers. When any of the monitored inputs are out of the specified range, the corresponding alarm bit in the alarm status registers is set. The alarm bits in the alarm status registers are latched. The alarm bits are referred to as being latched because the alarm bits remain set until read by software. This design makes sure that out-of-limit events cannot be missed if the software is polling the device periodically. All bits are cleared when reading the alarm status registers, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle. When the alarm event is cleared, the DAC is reloaded with the contents of the DAC active registers, which allows the DAC outputs to return to the previous operating point without any additional commands All alarms can be used to generate a hardware interrupt signal on the ALARM pin; see also . In addition, describes how the alarm action can be individually configured for each alarm. Alarm-Based Interrupts One or more of the available alarms can be set to activate the ALARM pin. Connect the ALARM pin as an optional hardware interrupt to the host. The host can query the alarm status registers to determine the alarm source upon assertion of the interrupt. Any alarm event activates the pin, as long as the alarm is not masked in the ALARM_STATUS_MASK register. When an alarm event is masked, the occurrence of the event sets the corresponding status bit in the alarm status registers, but does not activate the ALARM pin. The ALARM pin output depends on ALARM_STATUS and ALARM_STATUS_MASK register settings, independent of ALARM_ACT register settings. Alarm Action Configuration Register The AFEx82H1 provides an alarm action configuration register: ALARM_ACT, . Writing to this register selects the device action that automatically occurs for a specific alarm condition. The ALARM_ACT register determines how the main DAC responds to an alarm event from either an ADC conversion on the self-diagnostics channels (AIN0, AIN1, and TEMP), or from a CRC, WDT, VREF, TEMP_HI, or TEMP_LO fault. Only these faults cause a response by the DAC. Any other alarm status events trigger the ALARM pin. There are four options for alarm action. In case different settings are selected for different alarm conditions, the following low-to-high priority is considered when taking action: 0. → No action 1. → DAC CLEAR state 2. → VOUT alarm voltage 3. → VOUT Hi-Z If option 1 is selected when the alarm event occurs, then the DAC is forced to the clear code. This operation is done by controlling the input code to the DAC. If option 2 is selected when the alarm event occurs, then VOUT is forced to the alarm voltage. The alarm voltage is controlled by either pin or register bit. If SPECIAL_CFG.AIN1_ENB = 0, then the AIN1 pin controls alarm polarity. Also, register bit SPECIAL_CFG.ALMV_POL can be used. If either of these signals = 1, then the alarm voltage is high; otherwise, the alarm voltage is low. The SPECIAL_CFG register is only reset with POR, so the user setting remains intact through hardware or software resets. If option 3 is selected when the alarm event occurs, then the VOUT buffer is put into Hi-Z. If multiple events occur, then the highest setting takes precedence. Option 3 has the highest priority. To disable action response to an alarm, set the corresponding bits in ALARM_ACT to 0h. Alarm action response is cleared either when the triggered condition bit resets (behavior depends on whether the fault bit in ALARM_STATUS is sticky or not), or by changing the action configuration to 0h. An alarm action, as configured, executes when an alarm occurs depending on ALARM_STATUS and ALARM_ACT registers. Action response is independent of ALARM_STATUS_MASK settings. Alarm Voltage Generator shows that the alarm voltage is generated independently from the DAC output voltage. The alarm polarity control logic selects the output level of the alarm voltage generator. The alarm action control logic selects between the DAC output and alarm voltage generator output voltages. The alarm action control logic also controls the output buffer Hi-Z switch. Alarm Voltage Generator Architecture During normal operation, the expected VOUT voltage depends on the DAC_CODE. The ADC thresholds for the SD4 (VOUT) diagnostic channel are set around the programmed DAC_CODE. During the alarm condition, if the alarm action changes the VOUT voltage to the alarm voltage, or switches the VOUT buffer into Hi-Z mode, the VOUT voltage no longer depends on the DAC_CODE. In this case, the SD4 (VOUT) diagnostic channel also reports the alarm. To clear this alarm, as long as all other alarm conditions are cleared, set the alarm action to either no action or to the DAC clear code. Applying either alarm action sets the VOUT voltage within the expected ADC thresholds and clears the alarm after the next ADC measurement of the SD4 (VOUT) channel. Give special consideration to the alarm logic during the transient events. When the new DAC_CODE goes beyond the SD4 (VOUT) alarm thresholds with the ADC monitoring the SD4 (VOUT) input in auto mode, the ADC conversion can occur while VOUT settles to a new value. This conversion can trigger a false alarm. There are two ways to prevent this false alarm: Use direct mode and allow VOUT to settle before triggering the next ADC conversion. Set ADC_CFG.FLT_CNT > 0. With this configuration, a single error in SD4 or any other measurement does not cause an alarm condition to be asserted. Temperature Sensor Alarm Function The AFEx82H1 continuously monitor the internal die temperature. In addition to the ADC measurement, the temperature sensor triggers a comparator to show a thermal warning and a thermal error. A thermal warning alarm is set when the temperature exceeds 85°C. Additionally, a thermal error alarm is set when the die temperature exceeds 130°C. The thermal warning and thermal error alarms can be configured to set the ALARM pin and are indicated in the ALARM_STATUS register. These alarms can be masked with the ALARM_MASK register and also be configured to control the DAC output with the ALARM_ACT register. Internal Reference Alarm Function The devices provide out-of-range detection for the reference voltage. When the reference voltage exceeds ±5% of the nominal value, the reference alarm flag (VREF_FLT bit) is set. Make sure that a reference alarm condition has not been issued by the device before powering up the DAC output. ADC Alarm Function The AFEx82H1 provide independent out-of-range detection for each of the ADC inputs. shows the out-of-range detection block. When the measurement is out of range, the corresponding alarm bit is set to flag the out-of-range condition. ADC Out-of-Range Alarm An alarm event is only registered when the monitored signal is out of range for N number of consecutive conversions, where N is configured in the ADC_CFG.FLT_CNT false alarm register settings. If the monitored signal returns to the normal range before N consecutive conversions, an alarm event is not issued. If an ADC input signal is out of range and the alarm is enabled, then the corresponding alarm bit is set to 1. However, the alarm condition is cleared only when the conversion result returns to a value less than the high-limit register setting and greater than the low-limit register setting by the number of codes specified by the hysteresis setting (see ). The hysteresis is a programmable value between 0 LSB to 127 LSB in the ADC_CFG.HYST register. ADC Alarm Hysteresis Fault Detection There are two fields within the ADC_CFG register: FLT_CNT and HYST. These fields are applied to the assertion and deassertion of alarm conditions for all the ADC channels. ADC_CFG.FLT_CNT determines the maximum number of accepted consecutive failures before an alarm condition is reported. For example, if ADC_CFG.FLT_CNT is set for two counts, then three consecutive conversions must be outside of the thresholds to trigger an alarm. Each failure counts towards the FLT_CNT limit even if the failures alternate between high threshold and low threshold. ADC_CFG.HYST sets the hysteresis used by the alarm-detection circuit. After an alarm is triggered, the hysteresis is applied before the alarm condition is released. In the case of the high threshold, the hysteresis is subtracted from the threshold value. In the case of the low threshold limit, the hysteresis is added to the threshold value. Channels AIN0, AIN1, and TEMP have high and low thresholds associated with them. If a conversion value falls outside of these limits (that is, if TEMP < low threshold or TEMP > high threshold), an alarm condition for that channel is set. The alarms are disabled by setting 0x000 for the low threshold and 0xFFF for the high threshold, respectively. These alarms are disabled by default. Because the configuration fields for the thresholds are only eight bits wide, the four LSBs are hardcoded for each threshold. The high thresholds four LSBs are hardcoded to 0xF, and the low thresholds four LSBs are hardcoded to 0x0. All the self diagnostic (SD) channels have fixed thresholds, except SD4, which measures the VOUT of the main DAC. The threshold for SD4 tracks the VOUT with respect to the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/TABLE_BCL_BCQ_PQB shows the calculations used to determine the high and low ADC thresholds for each SD channel. The limits in the two right-most columns are determined by the threshold columns to the left and given some margin. The four LSBs are assigned as described previously. Self Diagnostic (SD) Alarm ADC Thresholds SD ADC INPUT ACCEPTED LOW VALUE ACCEPTED HIGH VALUE LOW THRESHOLD HIGH THRESHOLD ADC LOW (HEX) ADC HIGH (HEX) SD0 VREF/2 VREF/2 – 9% – 25 mV VREF/2 + 9% + 25 mV 0.54375 V 0.70625 V 0x6D0 0x92F SD1 PVDD/6 1.65/6 – 25 mV 6/6 + 25 mV 0.25 V 1.025 V 0x310 0xD3F SD2 VDD/2 1.6/2 – 25 mV 2/2 + 25 mV 0.775 V 1.025 V 0x9C0 0xD3F SD3 0.6 V 0.6 V – 9% – 25 mV 0.6 V + 9% + 25 mV 0.521 V 0.679 V 0x690 0x8CF SD4 VOUT/2 VOUT/2 – 6 mV VOUT/2 + 6 mV VOUT – 12 mV VOUT + 12 mV Expected – 0x040 Expected + 0x040 The alarm threshold for the SD4 input depends on the expected ADC measurement based on the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/EQUATION-BLOCK_QF3_WXF_QVB shows the expected ADC code for SD4. ADC Expected Code = DAC_CODE[MSB:MSB-11] IRQ The devices include an interrupt request (IRQ) to communicate the occurrence of a variety of events to the host controller. The IRQ block initiates interrupts that are reported internally in a status register, externally on the IRQ pin if the function is enabled, or on the ALARM pin if the condition is from the ALARM_STATUS register. shows the IRQ block diagram. IRQ Block Diagram There are three registers that can generate interrupts: GEN_STATUS, MODEM_STATUS, and ALARM_STATUS. Each of these registers has a corresponding STATUS_MASK register. The mask register controls which of the events trigger an interrupt. Writing a 1 in the mask register masks, or disables, the event from triggering an interrupt. Writing a 0 in the mask register allows the event to trigger an IRQ. All bits are masked by default. Some status bits are sticky. Reading the corresponding register clears a sticky bit, unless the condition still exists. The IRQ is configured through CONFIG.IRQ_LVL to be edge- or level-sensitive. Set this bit to logic 1 to enable level-sensitive functionality (default). In edge-sensitive mode, the IRQ signal is a synchronous pulse, one internal clock period wide (813 ns). In level-sensitive mode, the IRQ is set and remains set as long as the condition exists. After the IRQ condition is removed, the condition is cleared by reading the corresponding status register. Trying to clear the bit while the condition still exists does not allow the bit to be cleared if the bit is sticky. CONFIG.IRQ_POL determines the active level of the IRQ. A logic 1 configures IRQ to be active high. When using edge-sensitive IRQ signals, there is a clock cycle delay for synchronization and edge detection. With a 307.2-kHz clock, this delay is up to 3.26 μs. For level-sensitive mode, the delay is approximately 10 ns to 20 ns. Most status bits have two versions within the design. The first version is an edge event that is created when the status is asserted. This signal is used to generate edge-sensitive IRQs. This edge detection prevents multiple status events from blocking one another. The second version is the sticky version of the status bit. This signal is set upon assertion of the status bit and cleared when the corresponding status register is read, as long as the status condition does not still persist. Signals GEN_IRQ, MODEM_IRQ, and ALARM_IRQ are driven by the logical OR of the of the status bits within the corresponding register. If a status bit is unmasked and the sticky version of that bit has been asserted, and the IRQ is level-sensitive, then an interrupt is triggered as soon as the bit is unmasked. If the IRQ is edge-sensitive then a status event must occur after the bit has been unmasked to assert an interrupt. FIFO flags are not sticky; therefore, an IRQ can be triggered, but the status flag can be deasserted by the time the status information is transmitted at the output. For example, If FIFO_U2H_LEVEL_FLAG is unmasked and the FIFO_U2H level drops below the set threshold, the IRQ triggers. If the device is configured to output UBM IRQ messages and a HART data byte is received on UARTIN after the IRQ, but before the UBM captures the IRQ status, then the IRQ status and data information reads back all zeros. If UBM IRQ mode is used, wait until the IRQ message is fully transmitted on UARTOUT before putting data on UARTIN. HART Interface On the AFEx82H1, a HART frequency-shift keyed (FSK) signal can be modulated onto the MOD_OUT pin. illustrates the output current versus time operation for a typical HART interface. Output Current vs Time DC current = 6 mA To enable the HART interface, set the HART_EN bit in the MODEM_CFG register. An external capacitor, placed in series between the RX_IN pin and HART FSK source, is required to ac-couple the HART FSK signal to the RX_IN pin. The recommended capacitance for this external capacitor is 2.2 nF. If additional filtering is required, the AFEx82H1 also support an external band-pass filter. For this configuration, use the RX_INF pin instead of RX_IN pin. FIFO Buffers First-in, first-out (FIFO) buffers are used to transmit and receive HART data using both the SPI and UART. Both the transmit FIFO (FIFO_U2H) and receive FIFO (FIFO_H2U) buffers are 32 rows and 9-bits wide. The 9-bit width allows the storage of the parity bit with the data byte. Bit[8] is the parity bit as received by either the UART or HART demodulator, depending on the direction of the data flow. The device does not calculate the parity bit in this case, and transmits the data with the wrong parity bit if the wrong parity bit was received. Bits[7:0] are the data. The AFEx82H1 HART implementation is shown in . HART Architecture HART data bytes are enqueued into a transmit FIFO_U2H buffer using the SPI or UART. The input data bits are translated into the mark (1200 Hz) and space (2200 Hz) FSK analog signals (see ) used in HART communication by the internal HART transmit modulator. The receive demodulator enqueues HART data into the receive FIFO_H2U buffer. An arbiter is implemented with signals to CD and from the RTS pins to manage the HART physical connections on MOD_OUT, and either the RX_IN or RX_INF pin. To enable efficient and error-free communication, the arbiter in conjunction with the two FIFO buffers can be used to produce an IRQ for the system controller. An incorrect stop bit in the HART receive character causes a HART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the HART data are not enqueued into FIFO_H2U. If the frame error check is not masked, an IRQ event is also triggered. Similarly, an incorrect stop bit in the UARTIN character causes a UART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the UART data are not enqueued into FIFO_U2H. If the frame error check is not masked, an IRQ event is also triggered. FIFO Buffer Access In SPI only mode, both FIFO buffers are accessed using register addresses. HART bus communication activity is reported to the host controller through the IRQ pin and MODEM_STATUS register. See for recommended IRQ based communication techniques when using the AFEx82H1 to convert between the SPI and HART. Write to the FIFO_U2H_WR register to enqueue the HART transmit data into FIFO_U2H. Calculate the correct parity bit and include the parity bit with the data. Do not attempt to read data from the FIFO_U2H because a read request from the FIFO_U2H_WR register is not supported. The read from the FIFO_U2H_WR register returns the data from the dequeue pointer location of FIFO_U2H, but does not dequeue the data. Read the FIFO_H2U_RD register to dequeue the HART receive data from FIFO_H2U. If CRC is enabled and a CRC error occurs during a read request, no data are dequeued from the FIFO_H2U buffer, and the data in the readback frame are invalid. A write to the FIFO_H2U_RD register is ignored. When communicating with the HART modem through the UART interface in SPI plus UART mode, any character received on the UARTIN pin is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the clear-to-send (CTS) response is asserted. Similarly, any character received on the RX_IN or RX_INF pin is directly enqueued into FIFO_H2U. The character is then automatically dequeued from FIFO_H2U and transmitted on UARTOUT as a normal UART character. The FIFO buffers are accessed directly by the UART; therefore, do not use the FIFO_U2H_WR and FIFO_H2U_RD registers with the SPI. As a result of using FIFO_U2H in the data path, there is a latency from the UARTIN pin to the MOD_OUT pin; see also . Similarly, as a result of using FIFO_H2U, there is a latency from the RX_IN or RX_INF pin to the UARTOUT pin; see also . HART bus communication activity is interfaced to the host controller through the CD and RTS pins. If the CD and RTS pins are not used, poll the MODEM_STATUS register regularly to monitor the status of the modem. In UBM mode, any character received on the UARTIN pin that is not a part of a break command is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the CTS response is asserted. Although the UBM packets can access all registers, do not use the break command to write the HART transmit data into FIFO_U2H_WR register. Use the standard 8O1 UART character format to enqueue data into the FIFO_U2H buffer, and thus to the HART modulator. Similarly, do not use the break command to read the HART receive data from the FIFO_H2U_RD register. HART receive data are automatically dequeued from FIFO_H2U and transmitted on UARTOUT as normal UART characters in UBM mode. FIFO Buffer Flags Status bits exist for both transmit and receive FIFO buffers in the MODEM_STATUS, FIFO_STATUS and FIFO_H2U_RD registers. These include full, empty, and level flags. Buffer level flags are used to trigger IRQs for HART communication; see also . The status fields in the FIFO_H2U_RD register represent the state of FIFO_H2U before the read is performed and the data byte is dequeued. This implementation means that if the EMPTY_ FLAG is set, the data byte received in that frame is invalid. Similarly, the LEVEL field represents the 4 MSBs for the FIFO_H2U level before dequeuing. The LSB is not reported, and there are only five internal bits to represent 32 levels; therefore, the LEVEL = 0 is reported when the actual level is 0, 1, or 32. Use FULL_FLAG and EMPTY_FLAG when LEVEL = 0 to differentiate between these three cases. The FIFO_H2U and FIFO_U2H buffers have 32 levels; however, the level setting for generating IRQ events only uses four bits. For the receive FIFO_H2U buffer, the LSB in the FIFO level threshold comparison is always 1 (FIFO_CFG.H2U_LEVEL_SET[3:0], 1). This configuration is designed to alert the user when FIFO_H2U is getting nearly full so as to enable a timely data dequeue, and prevent the loss of incoming HART data due to FIFO overload. For this reason, the FIFO_H2U_LEVEL_FLAG is also a greater-than (>) comparison to the FIFO_CFG.H2U_LEVEL_SET. For example, if FIFO_CFG.H2U_LEVEL_SET = 4’b1000, then when the level of the FIFO_H2U > 5’b10001, the FIFO_H2U_LEVEL_FLAG is set. Setting FIFO_CFG.H2U_LEVEL_SET = 4’b1111 (default) effectively disables this flag. Use FIFO_H2U_FULL_ FLAG to detect the FIFO_H2U full event. When the FIFO_H2U is full, the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. Similarly, for the transmit FIFO_U2H buffer, the LSB in the FIFO level threshold comparison is always 0 (FIFO_CFG.U2H_LEVEL_SET[3:0], 0). This configuration is designed to alert the user when FIFO_U2H is getting nearly empty so as to enable a timely data enqueue, and prevent FIFO_U2H from becoming empty prematurely and causing a gap error on the HART bus. For this reason, the FIFO_U2H_LEVEL_FLAG is also a less-than (<) comparison with the FIFO_CFG.U2H_LEVEL_SET. For example, if FIFO_CFG.U2H_LEVEL_SET = 4’b1000, then when the level of the FIFO_U2H < 5’b10000, the FIFO_U2H_LEVEL_FLAG is set. Setting FIFO_CFG.U2H_LEVEL_SET = 4’b0000 (default) effectively disables this flag. Use FIFO_U2H_EMPTY_ FLAG to detect the FIFO_U2H empty event. To avoid buffer overflow, monitor the level of FIFO_U2H by watching for a buffer-full or buffer-threshold event. If the FIFO_U2H_LEVEL_FLAG bit in the MODEM_STATUS_MASK register is set to 0, the IRQ pin toggles when the threshold is exceeded. Similarly, an alarm can be triggered based on the FIFO_U2H_FULL_FLAG bit in the MODEM_STATUS register. When the FIFO_U2H is full the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. HART Modulator The HART modulator implements a look-up table (LUT) containing 128, 8-bit, signed values that represent a single-phase, continuous sinusoidal cycle. A counter is implemented that incrementally loads the table values to a DAC at a clock frequency determined by the binary value of the input data. The DAC clock frequency is determined by the logical value of the data bit being transmitted. A logic 1 transmits at the internal clock frequency of 32 (default) steps times 1200 Hz. A logic 0 transmits at the internal clock frequency of 32 (default) steps times 2200 Hz. All frequencies are derived from 1.2288 MHz. This process creates the mark and space analog output signals used to represent HART data. The default mode uses 32 sinusoidal codes per period from the LUT for power savings. To generate a 128-step-per-period sinusoidal signal set MODEM_CFG.TxRES = 1. shows the HART modulator architecture. HART Modulator Architecture HART Demodulator The HART demodulator converts the HART FSK input signals applied at the HART input pins (RX_IN and RX_INF) to binary data that are enqueued into the receive FIFO (FIFO_H2U). Data from the FIFO_H2U can then be dequeued by the host controller using the SPI or output on UARTOUT. shows the HART demodulator architecture. The AFEx82H1 supports two different input bandpass filter modes: internal and external. In internal filter mode, the HART input signal is connected to the RX_IN pin through the high-pass filter capacitor. In this mode, the low-pass filter capacitor is connected to the RX_INF pin. In external filter mode, the band-pass filter is implemented with external components for better flexibility, and the resulting band-pass-filtered signal is connected to the RX_INF pin. In this mode, float the RX_IN pin. Use the MODEM_CFG.RX_EXFILT_EN bit to select between these two modes, depending on the external band-pass filter implementation and HART input signal connection. The input band-pass filter (either fully external or partially internal with external capacitors and internal resistors) is followed by the internal second-order high-pass filter and the internal second-order low-pass filter. To enable the second-order low-pass filter, use the MODEM_CFG.RX_HORD_EN bit. HART Demodulator Architecture The HART demodulator asserts a carrier detect (CD) signal, when a carrier-above-threshold level is detected. Hysteresis is implemented with the carrier-detect feature to prevent erroneous carrier-detection signals. The glitch-free CD signal is available internally to the arbiter and externally to the system controller on the CD pin. HART Modem Modes The HART modulator‑demodulator operates in either half‑duplex or full‑duplex mode. Half-Duplex Mode Half-duplex mode is the main functional mode of operation for the AFEx82H1, in conjunction with the half‑duplex HART protocol. In half-duplex mode, either the modulator or demodulator is active at any given instant, but never simultaneously enabled. By default, the demodulator is active and the modulator is inactive. When using half-duplex mode, the modem arbitrates when modulator and demodulator are active. For more details, see . Full-Duplex Mode In full‑duplex mode, the modulator and demodulator are simultaneously enabled. This configuration allows a self‑test feature to verify functionality of the transmit and receive signal chains to improve system diagnostics. There are internal and external full-duplex modes. In internal full-duplex mode, the MOD_OUT pin is internally shorted to the RX_INF pin. Set MODEM_CFG.DUPLEX = 1 to enable an internal connection between the HART transmitter and receiver to verify communication. In external full-duplex mode, the HART modulator and demodulator are enabled, but the MOD_OUT pin is not internally shorted to the RX_IN or RX_INF pins. To enable the external full‑duplex mode, short MOD_OUT to RX_IN or RX_INF pins externally, and set MODEM_CFG.DUPLEX_EXT = 1. HART Modulation and Demodulation Arbitration In half‑duplex HART-protocol mode, the device arbitrates when the modulator and demodulator are active, based on activity on the HART bus. The system controller has various means of monitoring and interacting with the AFEx82H1. For the methods used in SPI mode, see . For the reporting method used in UART mode, see . In the default idle state, the RTS pin is high (inactive), and the CD pin is low. The demodulator is active and the modulator is inactive. HART Receive Mode When a carrier is detected, the CD pin toggles high, and data bytes received by the modem are automatically enqueued into FIFO_H2U. This mode is the highest priority, and the device continues to remain in this mode as long as a valid carrier is present. The system controller must timely dequeue the data from the FIFO_H2U as long as CD remains high and the demodulator enqueues new data into FIFO_H2U. CD is deasserted when the level of the incoming carrier is reduced to less than the HART specification. For receive operation timing details, see . HART Transmit Mode To transmit the HART data, issue a request to send (RTS) either by toggling the RTS pin low or asserting MODEM_CFG.RTS, depending on the selected communication setup. When the HART bus is available for transmission and no carrier is detected, the device deasserts the CD pin, disables the demodulator, asserts the CTS response by setting MODEM_STATUS.CTS_ASSERT = 1, and begins modulating the carrier. If the CD pin is used, wait for the CD pin to be deasserted. Otherwise, unmask CTS_ASSERT and set up the appropriate IRQs for the FIFO_U2H levels and CTS flags to enable the system controller to receive an IRQ when CTS is asserted. See also . When the CD pin and IRQ are not used, poll the MODEM_STATUS register regularly to detect when the CTS response is asserted. As long as the CD pin is asserted, the demodulator remains active and the RTS request is held pending by the arbiter. Any HART transmit data bytes received by the AFEx82H1 are enqueued into FIFO_U2H, but not transmitted immediately. The system controller must monitor the FIFO_U2H level to avoid buffer overflow in this condition. When the CTS response is asserted, the data enqueued into FIFO_U2H are dequeued and transmitted onto the MOD_OUT pin. If no data are enqueued into FIFO_U2H, the modulator starts transmitting the mark signal. The beginning of the bit stream must meet the minimum bit times requirement to make sure there is enough time for successful detection of the mark-to-space transition on the receiving side; see also . The system controller is then required to maintain adequate an FIFO_U2H buffer level to avoid gap errors and deassert the RTS at the end of bit stream with the correct timing delays; see also . HART Modulator Timing and Preamble Requirements The HART modulator starts modulating the carrier as soon as the CTS response is asserted. If data are enqueued into FIFO_U2H before the CTS is asserted, make sure to enqueue the required preamble bytes at the beginning of the data packet in accordance with . The first byte is used by the HART recipient receiver to recognize the carrier and properly detect the mark-to-space transition of the start bit in the second character. Alternatively, wait for CTS_ASSERT, and give an appropriate delay while the modulator is transmitting the mark signal. Then enqueue the preamble bytes followed by the data bytes into FIFO_U2H. Monitor the level of FIFO_U2H and timely enqueue the new data to avoid transmission gap errors. Carrier Detect and Preamble HART REQUIREMENT FIFO_U2H STATE AFEx82H1 BEHAVIOR RECOMMENDED USE CASE Transmit at least 6 bit times of HART signal of specified amplitude for the carrier to be detected by the receiver. FIFO_U2H is empty. HART modulator starts sending mark FSK signal as soon as CTS is asserted. Wait at least 6 bit times from CTS assert before transmitting first preamble byte. Calculate the time to enqueue the data into FIFO_U2H based on the interface mode used. FIFO_U2H is preloaded with data. HART modulator starts sending FIFO_U2H data as soon as CTS is asserted. Preload FIFO_U2H with one additional preamble byte. Depending on the interface mode, there is a latency from the UARTIN or CS pin to the MOD_OUT pin as a result of using FIFO_U2H in the data path. In the SPI plus UART and UBM modes, a delay of approximately 1.5 bit times (1.5 × tBAUDUART) occurs from the stop bit on the UARTIN pin until the data are enqueued into FIFO_U2H as a result of data decoding and synchronization. shows this timing. HART Transmit Start Timing Diagram (UART Mode) In SPI only mode, the HART transmit data are enqueued into FIFO_U2H using FIFO_U2H_WR register. Therefore, in this mode, take the standard SPI timing into consideration while calculating the latency of the HART transmit data from the CS pin to the MOD_OUT pin. shows the HART transmit start timing for SPI mode. HART Transmit Start Timing Diagram (SPI Mode) The HART character contains 11 bits; therefore, a delay of approximately 11 bit times (11 × tBAUDHART) occurs from the moment the data are dequeued from FIFO_U2H until the data are fully transmitted on the MOD_OUT pin (see ). Additional delay is accumulated when there is a frequency mismatch between the incoming UART_IN data and the HART data transmitted on MOD_OUT. If the UART_IN data frequency is 2% greater compared to the MOD_OUT data frequency, a delay of approximately 1 bit time is accumulated every five HART characters. Add a gap of at least 1 bit time between every five HART characters to account for this latency. Keep the request to send (RTS) asserted until the data are fully transmitted on MOD_OUT. HART Transmit End Timing Diagram (UBM, UART Plus SPI Modes) HART Demodulator Timing and Preamble Requirements The RX_IN and RX_INF pins are continuously monitored by the HART demodulator when not transmitting. AFEx82H1 requires at least 3 mark bits (3 × tBAUDHART) of 1200 Hz for carrier detection. For UART-based communication setup, the HART data are automatically dequeued from FIFO_H2U and transmitted on the UARTOUT pin as UART characters. A delay of approximately 1.5 bit times (1.5 × tBAUDHART) occurs as a result of data decoding and synchronization from the end of the character on RX_IN or RX_INF pin until the data are enqueued into FIFO_H2U. Thus, when CD deasserts, there is typically still one UART character pending transfer to the system controller on UARTOUT (see ). FIFO latency is as low as a few microseconds when using the SPI to dequeue the data from FIFO_H2U by reading FIFO_H2U_RD register. and show the timing diagrams for the start and end of the HART receive character, respectively. HART Receive Start Timing Diagram (SPI and UART Modes) HART Receive End Timing Diagram (UART Mode) IRQ Configuration for HART Communication To enable robust and error-free communicate on the HART bus, the events listed in #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/TABLE_BCL_BCQ_PQB must be detected from the AFEx82H1 by the system controller in a timely manner. If the IRQ signal is not directly connected to the system controller, poll the corresponding status flags. In UART mode, the automatic dequeue of FIFO_H2U simplifies event management significantly, and not all events must be translated to IRQs. When using the HART modem with the IRQ, the IRQ features help control communication in both directions. Enable IRQ functionality by following these steps: Configure the IRQ to be either edge or level sensitive using CONFIG.IRQ_LVL. See also . Configure the IRQ polarity with CONFIG.IRQ_POL, as needed per the respective system. See also . For SPI only mode, set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the UARTOUT pin. Also, set CONFIG.UART_DIS = 1 to disable all UART functionality. For UBM, use one of the two following methods: Set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the SDO pin, or Set CONFIG.UBM_IRQ_EN = 1 to enable interrupts being sent UARTOUT using UBM. After IRQ functionality is enabled, unmask all the required interrupt signals in the MODEM_STATUS_MASK register (set each bit = 0). IRQ Sources and Uses AFEx82H1HART STATE EVENT MODEM_STATUS FLAG ASSERTION METHOD #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWB ACTION Receive RTS deasserted CTS_DEASSERT Toggle RTS pin high or set MODEM_CFG.RTS = 0. Demodulator enabled and ready to receive HART data. Carrier detect asserted CD_ASSERT Demodulator detects the HART carrier signal of valid amplitude. Expect to receive HART data. Set desired FIFO_H2U level trigger threshold. FIFO_H2U level threshold trigger FIFO_H2U_LEVEL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. Dequeue data from FIFO_H2U when level exceeds the set threshold. Prevent FIFO_H2U from being full to avoid the loss of incoming data. FIFO_H2U full FIFO_H2U_FULL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. System controller has not dequeued FIFO_H2U. Critical flag. Dequeue FIFO_H2U immediately to avoid the loss of incoming data. Carrier detect deasserted CD_DEASSERT Demodulator stops detecting the HART carrier signal of valid amplitude. Dequeue remaining data from FIFO_H2U. Monitor the empty flag to make sure that all data have been received. FIFO_H2U empty FIFO_H2U_EMPTY_FLAG Dequeue of FIFO_H2U by system controller. If using UART, wait to make sure the last character is received on UARTOUT. Transmit RTS asserted NA Toggle RTS pin low or write set MODEM_CFG.RTS = 1. Wait for clear-to-send confirmation flag. Clear to send (CTS) CTS_ASSERT RTS asserted and CD deasserted. Modulator enabled. Device starts modulating the carrier on MOD_OUT. Set desired FIFO_U2H level trigger threshold. Enqueue data into FIFO_U2H. Modulator automatically dequeues FIFO_U2H and transmits the HART data. FIFO_U2H level threshold trigger FIFO_U2H_LEVEL_FLAG Automatic dequeue of FIFO_U2H by HART modulator. Enqueue new data into FIFO_U2H when the level drops below the set threshold. Prevent FIFO_U2H from being empty to avoid a gap in transmission. FIFO_U2H full FIFO_U2H_FULL_FLAG System controller enqueue of the new data into FIFO_U2H. Critical flag.Stop enqueue of data into FIFO_U2H immediately to avoid loss of HART data. FIFO_U2H empty FIFO_U2H_EMPTY_FLAG Automatic dequeue of FIFO_U2H by HART modulator. System controller has not enqueued new data into FIFO_U2H. Critical flag in the middle of the data packet.Enqueue new data into FIFO_U2H immediately to avoid a gap in transmission. When the last character is dequeued from FIFO_U2H, wait until the character is fully transmitted on MOD_OUT before deasserting RTS. For CD, RTS, ALARM, and IRQ connection choices, see . HART Communication Using the SPI HART bus communication activity is reported to the host controller through the IRQ signal routed to the UARTOUT pin and MODEM_STATUS register. Read the MODEM_STATUS register to determine the source of the IRQ when an IRQ is received. If the UARTOUT pin is not connected, poll the status registers regularly through the SPI. To transmit data, set up the desired FIFO_U2H level thresholds using FIFO_CFG.U2H_LEVEL_SET. Assert the RTS. After CTS_ASSERT is set, begin to fill FIFO_U2H. Enqueue enough data into FIFO_U2H to fill the FIFO above the set threshold level. The HART modulator automatically dequeues the data from FIFO_U2H and transmits the data on MOD_OUT. When FIFO_U2H level drops below the set threshold, an IRQ triggers, indicating that new data bytes can be enqueued without losing any data. After the last set of data have been enqueued into FIFO_U2H, an IRQ event triggered by the level flag can be ignored. Wait for the IRQ event triggered by FIFO_U2H_EMPTY_FLAG. Deassert the RTS after required delay; see also . When the RTS is deasserted, the CTS_DEASSERT bit is set. CTS_DEASSERT is an informational bit. To receive data, set up an IRQ event based on CD_ASSERT to know when the carrier is detected and the new data bytes are expected. Also, set up the additional IRQ events to trigger each time FIFO_H2U_LEVEL_FLAG is set. Select the desired level of FIFO_H2U. Dequeue the data from FIFO_H2U every time the level exceeds the set threshold. Also, set up IRQ event trigger based on CD_DEASSERT to know when all the data have been received. At this point, monitor FIFO_H2U.EMPTY_FLAG when dequeuing each character to know when FIFO_H2U is empty and all the data bytes have been dequeued and transmitted to the microcontroller. Alternatively, the CD pin can be directly connected to the microcontroller to monitor the status of the HART bus. In this configuration, mask CD_ASSERT flag by setting MODEM_STATUS_MASK.CD_ASSERT bit = 1 to prevent CD_ASSERT from generating an IRQ event. HART Communication Using UART In SPI plus UART mode, the UART data are transmitted and received at 1200 baud, which is matched to the HART FSK input and output signals. Both SDO and UARTOUT pins are used; therefore, the IRQ functionality is not available in SPI plus UART mode. FIFO_H2U level monitoring is not required because any HART data received by the demodulator and enqueued into FIFO_H2U are automatically dequeued and transmitted on UARTOUT. FIFO_U2H level monitoring is also not required if HART bus communication activity is interfaced to the host controller through the CD and RTS pins. The host controller can properly time the RTS pin to transmit the HART data when no carrier is detected on the bus. If the CD and RTS pins are not used in SPI plus UART mode, the host controller can periodically poll the MODEM_STATUS register through the SPI to detect when the carrier is not present on the HART bus, and assert the request to send by setting MODEM_CFG.RTS bit = 1. In UBM, the UART data are transmitted and received at 9600 baud. The HART data characters are interleaved with break commands for register map access or interrupt reporting; see also . Similar to SPI plus UART mode, monitoring of FIFO_H2U and FIFO_U2H levels is not required. The CD and RTS pins are available to interface the HART bus activity with the microcontroller. IRQ functionality is also available on the SDO pin. If the SDO pin is connected to the microcontroller, the IRQ event based on CD_ASSERT can be set to report when the carrier is detected. In this case, CD pin connection to the microcontroller is not required. Similarly, RTS pin connection is not required if MODEM_CFG.RTS is used to issue a request to send. The SDO pin connection to the microcontroller is also not required if the microcontroller can periodically poll the MODEM_STATUS register using break commands, and monitor all the required flags. Memory Built-In Self-Test (MBIST) Memory built-in self-test (MBIST) verifies the validity of the static random-access memory (SRAM) used for the FIFO buffers. When initiated, the MBIST takes control of the SRAM module until completion. Disable HART communication while the MBIST is running. Communication with the FIFO buffers during the MBIST produces unreliable results. Two status bits, GEN_STATUS.MBIST_DONE and GEN_STATUS.MBIST_FAIL, can be monitored for completion or failure, or used to create IRQ events. Do not try to read back the GEN_STATUS register while the MBIST is running. The MBIST control logic generates narrow pulses for the MBIST_DONE and MBIST_FAIL status flags. The status flags can be missed if these pulses occur during the readback of the GEN_STATUS register. To avoid missing the MBIST_DONE flag, mask all the status bits except GEN_STATUS_MASK.MBIST_DONE and then either: monitor for an IRQ event, or periodically send a NOP and check the GEN_IRQ status bit. Wait until MBIST_DONE is reported, verify the status of the MBIST_FAIL flag, and then resume normal operation. Internal Reference The AFEx82H1 family of devices includes a 1.25-V precision band-gap reference. The internal reference is externally available at the VREFIO pin and sources up to 2.5 mA. For noise filtering, use a 100-nF capacitor between the reference output and GND. The internal reference circuit is enabled or disabled by using the REF_EN pin. A logic high on this pin enables the internal reference, and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal reference, and the device expects to have 1.25 V from external VREF at the VREFIO pin. An invalid reference voltage asserts an alarm condition. The DAC response depends on the VREF_FLT setting in the ALARM_ACT register (10h). Integrated Precision Oscillator The internal time base of the device is provided by an internal oscillator that is trimmed to less than 0.5% tolerance at room temperature. The precision oscillator is the timing source for ADC conversions. At power up, the internal oscillator and ADC take roughly 300 µs to reach < 1% error stability. After the clock stabilizes, the ADC data output is accurate to the electrical specifications provided in . Precision Oscillator Diagnostics The AFEx82H1 features two methods to continuously detect the functional status of the internal precision oscillator. The first method requires a connection from the AFEx82H1 to the system controller. To use the first method, program the AFEx82H1 to output a subdivided internal oscillator clock signal on the CLK_OUT pin. Write to the CONFIG.CLKO register field (see ) to enable the output with the chosen divider or to disable the output. The output digital signal is compliant to the . The CLK_OUT pin is also a shared GPIO pin. For details on connecting CLK_OUT and CLK_OUT interoperability as a GPIO pin , see . The second method does not require a connection from the AFEx82H1 and is a polled-communication-based method to determine the functionality of the internal oscillator using SPI communication. See and for SPI communication details and SDO status bits details, respectively. The OSC_DIV_2 bit reports the logical value of a subdivided internal oscillator signal (divided by 2) sampled at the CS falling edge. Use an appropriate SCLK frequency and interval between SPI frames to capture bit changes from frame to frame as a method of verifying the continued proper operation of the clock. Similar status reports of the logical value of a subdivided internal oscillator signal (divided by 1024) are available in UBM as the OSC_DIV_1024 bit. For details on UBM frames and timing, see . One-Time Programmable (OTP) Memory One-time programmable (OTP) memory in the device is used to store the device trim settings and is not accessible to users. The OTP memory data are loaded to the memory (OTP shadow load) at power up. The OTP memory CRC is performed to verify the correct data are loaded. The TRIGGER.SHADOWLOAD bit is available to initiate a reload of the OTP memory data if a CRC error is detected. The SPECIAL_CFG.OTP_LOAD_SW_RST bit controls whether the OTP memory data are reloaded with a software reset. GPIO AFEx82H1 feature multiple GPIO pins, each independently configurable in either input only or output only or input-ouput mode through GPIO_CFG and GPIO registers. Select either push-pull or pseudo open drain sub modes supported when the GPIO is in output mode. No dedicated GPIO pins are present since the same pins are also configurable for communication interfaces. Based on the selection of the interface protocol and how many pins are used for communication purposes, the AFEx82H1 have up to four available GPIOs. Refer to for detailed diagrams of available GPIOs in each communication mode. If a GPIO pin is unused or undriven, the pin must be tied resistively to either IOVDD or GND according to the connection diagrams in . Unconnected floating input pins lead to unknown states for the communication interfaces and varying supply currents for the AFEx82H1. When functioning as an output, each GPIO pin is capable of sourcing and sinking current and when functioning as an input the register address 0x1C reflects the digital state of the GPIO pins (for details of source and sink capabilities and input thresholds, see ). The minimum pulse width for transition detection is tPULSE_GPIO. When a state transition occurs on a GPIO input, the new state must be held for a minimum of tPULSE_GPIO for detection by the AFEx82H1. Timer The AFEx82H1 have an integrated timer for generating accurate time delays, pulse width modulation or oscillation. The devices have the ability to have timing parameters from the microseconds range to hours. The timer is brought out on the CLK_OUT pin by setting CONFIG.CLKO = Fh. The timer is controlled with three registers; TIMER_CFG_0, TIMER_CFG_1, and TIMER_CFG_2. In the first of the three registers, TIMER_CFG_0.ENABLE turns the timer function on and off. If the timer is off, then the output defaults to 0. TIMER_CFG_0.INVERT inverts the output of the timer. If the INVERT bit is set, the output defaults to 1. TIMER_CFG_0.CLK_SEL selects the clock frequency according to #GUID-D4148F6E-8502-48B6-8064-9DF2FCCD8009/TABLE_ADN_CZD_PVB. If 2'b00 is selected, and no clock is applied, then the timer pauses if the timer has previously been enabled and counting. Timer Select Range CLK_SEL Clock Frequency Resolution Range 00 No clock - - 01 1.2288 MHz 814 ns 53.3 ms 10 1.200 kHz 833 μs 54.6 s 11 1.171 Hz 853 ms 55,923 s The second timer register, TIMER_CFG_1.PERIOD sets the period of the timer. The period of the timer is PERIOD + 1 cycles of the clock period. The last timer register, TIMER_CFG_2.SET_TIME determines when the timer output goes to 1 (INVERT = 0). This effectively defines the duty cycle of the timer. The duty cycle can be calculated as (PERIOD – SET_TIME) × clock period. Unique Chip Identifier (ID) AFEx82H1 include two read only registers: CHIP_ID_MSB (1Ah) and CHIP_ID_LSB (19h) where unique chip ID is stored. The 16-bit CHIP_ID_MSB register stores the encoded lot identification number while the CHIP_ID_LSB register stores the unique part number within each lot. Scratch Pad Register AFEx82H1 feature a 16-bit Scratch Pad register to enable interface debug and verification without affecting the part functionality. This register is located at the address 18h. The readback value of the Scratch Pad register is the inverted code of the value stored in the register (for example, writing 0xAAAA results in 0x5555 while reading back ). Device Functional Modes DAC Power-Down Mode Power-down mode facilitates rapid turn-off of the voltage at the DAC output. The DAC can be set to enter and exit power-down mode through hardware, software, or automatically in response to an alarm event. The DAC output is specified for glitch-free performance when going into and out of power-down mode. Power-down mode is also be enabled by setting DAC_CFG.PD to 1. In power-down mode, the DAC output amplifier powers down and the DAC output pin is put into the Hi-Z configuration. The DAC output remains in power-down mode until the DAC output is re-enabled. Alarm control of the power-down mode is enabled by setting the alarm events as DAC power-down sources. The alarm events that trigger the DAC output power-down state must be specified in the ALARM_ACT register. After the alarm bit is cleared, the DAC returns to normal operation, as long as no other power-down controlling alarm event has been triggered. The DAC register does not change when the DAC enters power-down mode, which enables the device to return to the original operating point after return from the power-down mode. Additionally, the DAC register can be updated while the DAC is in power-down mode, thus allowing the DAC to output a new value upon return to normal operation. Register Built-In Self-Test (RBIST) The AFEx82H1 feature a register built-in self-test (RBIST) that runs on all the registers listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB through a CRC calculation in the order the registers are listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB. If a register is reserved, the reset value is used in the calculation of the RBIST. If the final CRC value is zero, then no error is present in the configuration of the registers. If a non-zero value is present at the end of the calculation, then there is a configuration error. The polynomial used has a Hamming distance (HD) of 4 for data packets up to 2048 bits. With HD = 4, the CRC detects any combination of 4-bit errors within the stored data. Independently calculate the expected CRC polynomial and store the output in the RBIST_CRC register at 3Fh. The final value of the CRC is read in the CRC_RD register at address 3Eh. This value is updated while either an RBIST or shadow load is running. Both the RBIST and OTP memory use the same CRC calculation engine and polynomial. The value in the CRC_RD register remains constant until another RBIST or SHADOWLOAD in TRIGGER register (0Ah) is triggered. Set TRIGGER.RBIST to 1 to initiate an RBIST. The TRIGGER.RBIST bit stays high as long as the RBIST is running and clears when the self-test is complete. While the RBIST is running, the registers cannot be written to or read. Send NOP commands and monitor the RBIST SDO status bit to determine if the RBIST has completed.In UBM, the RBIST does not interfere with register communication. UBM communication is slow enough that the RBIST completes before any following read or write command. The GEN_STATUS.BIST_DONE and GEN_STATUS.BIST_FAIL bits have the same functionality for both MBIST and RBIST. GEN_STATUS.BIST_MODE is used to select between two tests (1 = RBIST and 0 = MBIST). This bit is sticky until the GEN_STATUS register is read. The FIFO_CFG.FIFO_H2U_FLUSH and FIFO_CFG.FIFO_U2H_FLUSH bits are write-self-clear (WSC) and considered 0 by the CRC module. The 16-bit CRC used to generate the RBIST is compliant to the openSAFETY (0x755B) standard with the following polynomial: x16 + x14 + x13 + x12 + x10 + x8 + x6 + x4 + x3 + x1 + 1. The list of registers covered by the RBIST is listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB. Not all registers feature the RBIST. List of Registers Covered by RBIST ADDR (HEX) REGISTER RESET (HEX) 01h DAC_DATA 0000h 02h CONFIG 0036h 03h DAC_CFG 0B00h 04h DAC_GAIN 8000h 05h DAC_OFFSET 0000h 06h DAC_CLR_CODE 0000h 08h ADC_CFG 8810h 09h ADC_INDEX_CFG 0080h 0Bh SPECIAL_CFG 0000h 0Dh RESERVED 0100h 0Eh MODEM_CFG 0040h 0Fh FIFO_CFG 00F0h 10h ALARM_ACT 8020h 11h WDT 0018h 12h AIN0_THRESHOLD FF00h 13h AIN1_THRESHOLD FF00h 14h TEMP_THRESHOLD FF00h 1Bh GPIO_CFG 00FFh 1Dh ALARM_STATUS_MASK EFDFh 1Eh GEN_STATUS_MASK FFFFh 1Fh MODEM_STATUS_MASK FFFFh 3Fh RBIST_CRC 0000h Reset There are three reset mechanisms in the device: a power-on reset (POR), a RESET pin, and the SW_RST command that can be sent through the either the SPI or by UBM. When power is first applied to the device, a POR circuit holds the device in reset until all supplies reach the specified operating voltages. The power-on reset returns the device to a known operating state in case a brownout event occurs (when the supplies have dipped below the minimum operating voltages). The POR starts all digital circuits in reset as the supply settles, and releases them to make sure that the device starts in the default condition and loads the OTP memory. After the OTP memory has been loaded, the ALARM pin is released. At this time, communication with the device is safe. This tPOR time is less than 100 µs. The devices also have a RESET pin that is used as a hardware reset to the device. Send the RESET pin low for a minimum of 100 ns (tRESET) to reset the device. A delay time of 10 μs (tRESETWAIT) is required before sending the first serial interface command as the device latches and releases the reset. The release of the internal reset state is synchronized to the internal clock. The RESET pin resets the SPI and the UART interfaces, the HART FIFO buffer, the watchdog timer, the internal oscillator, and the device registers. RESET does not reload the OTP memory. The command to RESET.SW_RST = 0xAD resets the device as a software reset. The command is decoded at the rising edge of CS with an SPI command or during the stop bit of the last character of a UBM frame. Set UBM.REG_MODE again to put the device back into UBM when resetting the device in UBM. After sending the RESET command, no delay time is required before sending the first serial interface command as the device latches and releases the reset. The reset is synchronized to the falling edge of the internal clock and is released well before the next rising edge. The ALARM pin pulses low for the width of the internal reset. This pulse duration is less than 20 ns. This command resets the SPI and the UART interface, the HART FIFO, and the watchdog timer, but does not reset the internal oscillator. The software reset also reloads internal factory trim registers if properly configured in the SPECIAL_CFG register. The SPECIAL_CFG register is only reset with a POR. The POR and hardware reset place the internal oscillator into a reset condition, which holds the clock low. When these two signals are released, there is a delay of a few microseconds before the first rising edge of the clock. The hardware reset, RESET, pulse width must be at least 100 ns to allow the oscillator to properly reset. The SW_RST command is a short pulse. This pulse is not long enough to adequately reset the oscillator. The SW_RST is asserted with a falling edge of the clock. As a result of the long oscillator period, the design architecture provides that all devices are out of reset by the next rising edge. shows the reset tree. Reset Conditions Programming The AFEx82H1 communicate with the system controller through a serial interface that supports either a UART-compatible two-wire bus or an SPI-compatible bus. Based on the hardware configuration, either interface can be enabled. and show the configurations to enable SPI mode and UART break mode (UBM), respectively. The SPI supports an 8-bit frame-by-frame CRC that is enabled by default, but can be disabled by the user. UBM does not support CRC, but does support the UART protocol parity bit. The AFEx82H1 are designed to leverage the existing firmware for communication with DACs or HART modems. A special SPI- and UART-capable dual mode of communication that is available to enable firmware reuse from discrete HART architecture is shown in . See for more details. Communication Setup After any reset or power up, the AFEx82H1 wake up able to use the SPI or UART break mode (UBM). The devices include a robust mechanism that configures the interface between either an SPI-compatible or UART-compatible protocol based system, thus preventing protocol change during normal operation. The selection is based on initial conditions from the respective hardware configurations (see and ) and any subsequent user configuration. In SPI plus UART mode, all communication pins on the system microcontroller are connected to the AFEx82H1, as shown in . SPI Mode By default, the AFEx82H1 can be fully accessed with the SPI (except UBM.REG_MODE). To set up the device in SPI mode: Set CONFIG.UART_DIS = 1 (disables the UART communication). Optionally, set CONFIG.DSDO, CONFIG.FSDO, and CONFIG.IRQ_PIN_EN. For details, see . SPI Mode Connections shows the SPI mode logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the UARTOUT pin functions as the IRQ output. In SPI mode, set CONFIG.SDO_DSDO = 0 to enable the readback function. This function is disabled by default to save power. If the readback function not enabled, SDO remains in Hi-Z mode even during the subsequent frame after a read request. Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tied the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor as indicated to avoid floating IOs. UART Mode At power up, the UART interface is set to 9600 baud with UBM enabled. Any reset clears the UBM register, and the register must be set again to use UBM. To set up the device in UBM: Using UBM, set UBM.REG_MODE = 1 at 9600 baud. This setting blocks the SPI from accessing the device and enables the UART interface access to the entire register map. Optionally, set CONFIG.CLR_PIN_EN and CONFIG.IRQ_PIN_EN (See for details). shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the SDO pin functions as the IRQ output. If CONFIG.CLR_PIN_EN = 1 is set, then the SDI pin controls the clear pin function. Enable each GPIO pin for use through proper register configuration. If a GPIO pin remains unused, tie the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor to avoid floating I/Os. UBM (UART Interface) Connections SPI Plus UART Mode In this mode, communicate with the integrated HART modem using the UART while communicating with the DAC using the SPI. Many discrete DACs use SPI communication, whereas HART modems use UART communication, but this special communication interface enables easy transition from discrete to integrated HART architecture. shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tie the pin to either IOVDD using a pullup or to GND using a pulldown as indicated to avoid floating I/Os. To setup the device in SPI plus UART mode using the SPI, set CONFIG.UART_BAUD = 0 to set the baud rate to 1200 for the UART, and to track the HART baud rate of 1200. The UART also works at a 9600 baud, but the 1200 baud rate of HART must be considered, and the FIFO STATUS must be monitored through the SPI. SPI Plus UART Mode Connections HART Functionality Setup Options #GUID-6C44E4D3-BE4F-4FC5-BC78-8E09FD6B576E/SLVSBY77695 shows the various options to set up HART functionality based on communication options by connected pin. HART Function Setup Options by Communication Pins Used FUNCTION INTERFACE MODE 1 PIN NAME HARDWARE METHOD (PIN CONNECTED) ALTERNATE METHOD (PIN NOT CONNECTED) Request to send (RTS) Any RTS (input) L: RTS asserted. H: RTS deasserted. Write to MODEM_CFG.RTS bit 1: RTS asserted. 0: RTS deasserted. Carrier detect (CD) Any CD (output) L: CD deasserted. H: CD asserted. Connect and setup interrupt request orPoll CD_ASSERT / CD_DEASSERT Clear to send (CTS) Any None Not available Connect and setup interrupt request or Poll CTS_ASSERT Alarm Any ALARM (output) Multiple alarm based interrupt sources for system controller; see also . Connect and setup interrupt request or Poll ALARM_STATUS register Interrupt request (IRQ) 2 UART SDO (output) Level- and polarity-configurable interrupt pin (see ). Multiple interrupt sources for system controller; see also . Set CONFIG.UBM_IRQ_EN = 1 to generate soft IRQ as break command followed by data on UARTOUT. See for details. SPI only UARTOUT (Output) Poll status registers SPI plus UART None Not available Poll status registers For option details, see . For IRQ configuration details, see . GPIO Programming Seven physical pins are interoperable as GPIOs in the AFEx82H1 when not used for communication. The state of these pins is set after the communication interface mode is determined (see for power-up conditions and connection-diagram options for each communication mode supported by the AFEx82H1). Configure any unused communication pins as GPIO, and resistively tie the pins to IOVDD or GND, respectively, as described in . #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/TABLE_A3S_QDJ_MSB shows the pins and pin functions in UBM, SPI Mode, or SPI plus UART mode and lists the register configuration conditions to enable GPIO functionality for each pin. In addition to these register configurations, to use an available pin as GPIO, set the corresponding GPIO_CFG.EN bit. For a GPIO pin to be configured as an input, the following conditions must be met: GPIO_CFG.ODE for the pin must = 1 GPIO.DATA for the pin must = 1 After initialization, the pin state is Hi-Z. Reading the GPIO.DATA register reads the pin value. If the previous conditions are not met, the pin is an output. In this case, the output drive type is determined by the GPIO_CFG.ODE bits to be push-pull or pseudo open drain. The GPIO output is driven by the GPIO.DATA bits. All reads of GPIO.DATA reports the values of the pins, regardless if the pins are configured as GPIO or not. Data written to the GPIO.DATA bits cannot be read directly. If a pin is available for use as GPIO, then the corresponding GPIO_CFG.EN bit must be set to enable GPIO functionality. Pin Configuration in Each Interface Mode PIN UBM SPI SPI PLUS UART REGISTER CONFIGURATION TO ENABLE GPIO #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/LI_PW1_PQF_VVB FUNCTION DIRECTION FUNCTION DIRECTION FUNCTION DIRECTION GPIO6/CS GPIO Input/Output CS Input CS Input (UBM.REG_MODE = 1) GPIO5/SDI CLR/GPIO Input/Output SDI Input SDI Input (UBM.REG_MODE = 1) AND (CONFIG.CLR_PIN_EN = 0) GPIO4/SDO IRQ/GPIO Input/Output SDO Output SDO Output (UBM.REG_MODE = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO3/UARTIN UARTIN Input GPIO Input/Output UARTIN Input (CONFIG.UART_DIS = 1) GPIO2/UARTOUT UARTOUT Output IRQ/GPIO Input/Output UARTOUT Output (CONFIG.UART_DIS = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO1/CD CD Output CD/GPIO Input/Output CD Output (CONFIG.UART_DIS = 1) GPIO0/CLK_OUT CLKO/GPIO Input/Output CLKO/GPIO Input/Output CLKO/GPIO Input/Output (CONFIG.CLKO = 0) AND ((UBM.REGMODE = 1) OR (CONFIG.UART_DIS = 1)) Required by pin in addition to the corresponding GPIO_CFG.EN bit. Serial Peripheral Interface (SPI) The AFEx82H1 are controlled over a versatile four-wire serial interface (SDIN, SDO, SCLK, and CS). The interface operates at clock rates of up to 12.5 MHz and is compatible with SPI, QSPI, Microwire, and digital signal processing (DSP) standards. The SPI communication command consists of a read or write address, a data word, and an optional CRC byte. The SPI can access all register addresses except for the UBM register. Read-only and read-write capability is defined by register (see ). The SPI supports both SPI Mode 1 (CPOL = 0, CPHA = 1) and SPI Mode 2 (CPOL = 1, CPHA = 0). The default SCLK value is low for SPI Mode 1 and high for SPI Mode 2. See for timing diagrams in each mode. The serial clock, SCLK, can be continuous or gated. SPI Frame Definition Subject to the timing requirements listed in the Timing Requirements , the first SCLK falling edge immediately following the falling edge of CS captures the first frame bit. Subject to the same requirements, the last SCLK falling edge before the rising edge of CS captures the last bit of the frame. shows that the SPI shift register frame is 32-bits wide, and consists of an R/W bit, followed by a 7-bit address, and a 16-bit data word. The 8-bit CRC is optional (enabled by default) and is disabled by setting CONFIG.CRC_EN = 0 (see also ). shows that when the CRC is disabled, the frame is 24-bits wide. SPI Frame Details (Default, CRC Enabled) SPI Frame Details (CRC Disabled) For a valid frame, a full frame length of data (24 bits if CRC is disabled or 32 bits if CRC is enabled) must be transmitted before CS is brought high. If CS is brought high before the last falling SCLK edge of a full frame, then the data word is not transferred into the internal registers. If more than a full frame length of falling SCLK edges are applied before CS is brought high, then the last full frame length number of bits are used. In other words, if the number of falling SCLK edges while CS = 0 is 34, then the last 32 SCLK cycles (or 24 if CRC is disabled) are treated as the valid frame. The device internal registers are updated from the SPI shift register on the rising edge of CS. To start another serial transfer, bring CS low again. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is high impedance. SPI Read and Write The SDI input bit is latched on the SCLK falling edge. The SDI pin receives right-justified data. At the rising edge of CS, the right-most (last) bits are evaluated as a frame. Extra clock cycles (exceeding frame length) during the frame begin to output on SDO the SDI data delayed by one frame length. A read operation is started when R/W bit is 1. The data word input for SDI is ignored in the read command frame. Send the subsequent read or write command frame into SDI to clock out the data of the addressed register on SDO. If no other read or write commands are needed, then issue a NOP command to retrieve the requested data. The read register value is output most significant bit first on SDO on successive edges (rising or falling based on CONFIG.FSDO setting) of SCLK. A write operation starts when R/W bit is 0. The SDO output to a write command, delivered in the next frame, contains status bits, data described in , and if the CRC is enabled, an 8-bit CRC for the output frame. Command Functions COMMAND BIT SDI INPUT DATA WORD SDO RESPONSE DATA WORD Write (R/W = 0) Data to be written (16b) 0x0000 Read (R/W = 1) Ignored Register output data (16b) Response data portion in next frame output. The input bits are included in the calculation for CRC, if enabled (see ). Valid SDO output is driven only when CS = 0 and CONFIG.DSDO = 0; otherwise, the SDO pin remains Hi-Z to save power. The SDO data bits are left-justified within the frame, meaning the most significant bit is produced on the line (subject to timing details) when CS is asserted low (bit is driven by falling edge of CS). The subsequent bits in the frame are driven by the rising SCLK edge when CONFIG.FSDO = 0 (default). To drive the SDO data on the falling edge of SCLK, set CONFIG.FSDO = 1. This setting effectively gives the SDO data an additional ½ clock period for setup time, but at the expense of hold time. The frame output on SDO contains the command bit of the input that generated the frame (previous input frame), followed by seven status bits (see ). When an input frame CRC error is detected, the status bit CRC_ERR = 1. If there is no input frame CRC error, then CRC_ERR = 0. See for details. Frame Error Checking If the AFEx82H1 are used in a noisy environment, use the CRC to check the integrity of the SPI data communication between the device and the system controller. This feature is enabled by default and is controlled by the CONFIG.CRC_EN bit. If the CRC is not required in the system, disable frame error checking through the CRC_EN bit, and switch from the default 32-bit frame to the 24-bit frame. Frame error checking is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (9'b100000111). For the output register readback, the AFEx82H1 supply the calculated 8-bit CRC for the 24 bits of data provided, as part of the 32-bit frame. The AFEx82H1 decodes 24-bits of the input frame data and the 8-bit CRC to compute the CRC remainder. If no error exists in the frame, the CRC remainder is zero. When the remainder is nonzero (that is, the input frame has single-bit or multiple-bit errors) the ALARM_STATUS.CRC_ERR_CNT bits are incremented. A bad CRC value prevents execution of commands to the device, which prevents FIFO data from being lost as a result of an invalid read command. When the CRC error counter reaches the limit programmed in CONFIG.CRC_ERR_CNT, the CRC_FLT status bit is set in the ALARM_STATUS register. The fault is reported (as long as the corresponding mask is not set) as an ALARM_IRQ on SDO during the next frame. The ALARM pin asserts low if enabled by the alarm action configuration (see ). The CRC_ERR status bit (see ) in the SDO frame is not sticky and is only reported for the previous frame. The ALARM_STATUS.CRC_FLT bit is sticky and is only cleared after a successful read of the ALARM_STATUS register. Read the GEN_STATUS, MODEM_STATUS or ALARM_STATUS registers to clear any sticky bits that are set. The sticky status bits are cleared at the start of the readback frame and are latched again at the end of the readback frame. Therefore, if the fault condition previously reported in the status register is no longer present at the end of the readback frame, and the data are received by the microcontroller with the CRC error, the fault information is lost. If a robust monitoring of the status bits is required in a noisy environment, use the IRQ pin in combination with the status mask bits to find out the status of each fault before clearing the status bits. Set the CONFIG.IRQ_LVL bit to monitor the signal level on the IRQ pin, and unmask each status bit one at a time to retrieve the information from the status registers. Synchronization The AFEx82H1 register map runs on the internal clock domain. Both the SPI and UBM packets are synchronized to this domain. This synchronization adds a latency of 0.4 µs to 1.22 µs (1.5 internal clocks), with respect to the rising edge of CS or the STOP bit of the last byte of the UBM packet. The effect of clock synchronization on UBM communication is not evident because of the lower speed and asynchronous nature of UBM communication. In SPI mode, if changing register bits CONFIG.DSDO, CONFIG.FSDO, or CONFIG.CRC_EN, keep CS high for at least two clock cycles before issuing the next frame. Frame data corruption can occur if the two extra cycles are not used. The following are examples of frame corruption: Setting CONFIG.DSDO = 0: SDO begins to drive in the middle of the next frame. Changing CONFIG.FSDO: The launching edge of SDO changes in the middle of the next frame. Setting CONFIG.CRC_EN = 1: The next frame has a CRC error because the CRC is enabled in the middle of the frame. Send a NOP command (SDI = 0x00_0000) after setting the DSDO, FSDO, and CRC_EN bits to prevent the corrupted frames from impacting communication. Sending a NOP after CONFIG.CRC_EN is set still generates a CRC error, and is reported in the STATUS portion of SDO. To avoid false errors, wait approximately 2 µs after setting CONFIG.CRC_EN before sending the next frame. UART Interface In UART mode, the device expects 1 start bit, 8 data bits, 1 odd parity bit, and 1 stop bit, or an 8O1 UART character format. When using SPI to communicate with the registers, and only using UART for HART communication, use 1200 baud. The baud must have ±1% accuracy. UART Break Mode (UBM) In UART break mode (UBM), the microcontroller issues a UART break to start communication. The device interprets the UART break as the start to receive commands from the UART. A communication UART character consists of one start bit, eight data bits, one odd parity bit, and at least one stop bit. A UART break character is all 11 bits (including start, data, parity and stop bit) held low by the microcontroller on the UARTIN pin and by the AFEx82H1 on the UARTOUT pin. When a valid break character is detected on UARTIN by the AFEx82H1, no parity (even though parity is odd) or stop bit errors are flagged for this character. The parity and stop bit differences between valid UBM break and communication characters must be managed by the system microcontroller when receiving these characters from the UARTOUT pin of the AFEx82H1. See for UBM break character, communication timing details, and bit order. Two baud rates are supported for UART communication: 9600 and 1200. The 9600 baud rate is default for UBM. The 1200 baud rate is supported to maintain backward compatibility and requires the use of SPI to communicate with the register map; whereas, the UART pins are used only for HART communication. The baud rates are selected by register bit CONFIG.UART_BAUD. When CONFIG.UART_BAUD = 1 (default), the UART operates at 9600 baud. When CONFIG.UART_BAUD = 0, the UART operates at 1200 baud. The break function of the UART protocol is enabled only for 9600 baud. This configuration allows interleaving of HART data with register communication and enables the access to all registers of the device, when configured correctly. Set UBM.REG_MODE = 1 to enable register map access through the UART. By default, this bit is set to 0. The entire register map can only be accessed with SPI, except for the UBM register. The UBM register can only be accessed with UBM. After UBM.REG_MODE is set to 1, the SPI does not have access to the register map, and the full register map is accessible by UBM. A UBM data output packet is initiated by AFEx82H1 on UARTOUT in two cases. See for packet structure details. If the R/IRQn status bit is 0 an IRQ event initiated the break command. If the R/IRQn status bit is 1, the break command is a response to the prior read request. For details on HART data see . To enable IRQ events, set CONFIG.UBM_IRQ_EN = 1. When IRQ is enabled, the AFEx82H1 triggers a break command followed by data on UARTOUT (see ). The contents of the data are listed in order of priority below. If ALARM_IRQ bit is set, then the contents of the ALARM_STATUS register are output. If GEN_IRQ is set, then the contents of the GEN_STATUS register are output. If MODEM_IRQ bit is set, then the contents of the MODEM_STATUS register are output. If none of the previous bits are set, then an IRQ is not generated. A break byte is followed by three bytes. These three bytes have information identical to the SPI frame without the CRC (see ). The CRC cannot be enabled for UBM. All communication characters on the UART bus are transmitted least significant data bit (D0) first. shows the data structure of the UBM write command, and shows the data structure of the UBM read command. UARTIN Break Write Data Format UARTIN Break Read Data Format shows the UARTOUT data frame with details of the status bits produced by the AFEx82H1. See for details. UARTOUT Break Data Format Interface With FIFO Buffers and Register Map In UBM, the HART data characters are interleaved with break commands for register map access or interrupt reporting. The device reports parity and frame errors received on UARTIN. These status bits can be found in the GEN_STATUS register and are maskable to create IRQ events. Avoid the large gaps between the HART bytes. The HART standard has a gap specification of 11 bit times (11 × tBAUDHART ms); therefore, gaps longer than 10.5 HART bit times (10.5 × tBAUDHART ms) can cause a gap error in the HART modem. The following timing diagrams illustrate examples of microcontroller communication with the device registers, as well as HART transmit and receive data transfers. Interleaved HART Transmit With UBM Register Writes Packed HART Transmit With UBM Register Writes Interleaved HART Transmit With UBM Register Read Requests and Responses Packed HART Transmit With UBM Register Write and Read Requests and Responses Interleaved HART Receive With UBM Register Write and Read Requests and Responses Status Bits In SPI mode and UBM, every response from the AFEx82H1 includes a set of status bits. For SPI mode bit order, see . For UBM bit order, . Status Bits STATUS BIT DESCRIPTION NOTES / REFERENCE ALARM_IRQ 1h = ALARM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . CRC_ERR(CRC enabled SPI only) 1h = CRC error detect in input frame 0h = No CRC error detected Generated by the SPI on a frame by frame basis. See . GEN_IRQ 1h = GEN_IRQ asserted 0h = Normal Operation From the ALARM_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . MODEM_IRQ 1h = MODEM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . OSC_DIV_1024 (UBM mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 1024) sampled at the falling edge of the status byte start bit. See also . OSC_DIV_2 (SPI mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 2) sampled at CS falling edge. See also . R/IRQn (UBM only) 1h = Read request 0h = IRQ event Generated by the UART interface on a frame by frame basis. See for details. RBIST 1h = RBIST busy (registers not readable) 0h = RBIST done (registers readable) RBIST running status. See for details. RESET 1h = First readback after RESET0h = All other readbacks From the GEN_STATUS register (). See also . ALARM_STATUS, MODEM_STATUS, and GEN_STATUS registers contain cross-readable IRQ flags for the other registers. The ALARM_STATUS register has the GEN_IRQ and MODEM_IRQ bits. MODEM_STATUS has the GEN_IRQ and ALARM_IRQ bits. GEN_STATUS has the ALARM_IRQ and MODEM_IRQ bits. This functionality enables the system microcontroller to always get full status information by reading only one register, and thus save power. Watchdog Timer The AFEx82H1 include a watchdog timer (WDT) that is used to make sure that communication between the system controller and the device is not lost. The WDT checks that the device received a communication from the system controller within a programmable period of time. To enable this feature, set WDT.WDT_EN to 1. The WDT monitors both SPI and UBM communications. The WDT has two limit fields: WDT.WDT_UP and WDT.WDT_LO. The WDT_UP field sets the upper time limit for the WDT. The WDT_LO field sets the lower time limit. If the WDT_LO is set to a value other than 2’b00, then the WDT acts as a window comparator. If the write occurs too quickly (less than the WDT_LO time), or too slowly (greater than the WDT_UP time), then a WDT error is asserted. When acting as a window comparator, in the event of a WDT error, the WDT resets only when a write to the WDT register occurs. If the WDT_LO is set to 2'b00, then a write to any register resets the WDT time counter. In this mode, the WDT error is asserted when the timer expires. If enabled, the chip must have any SPI or UBM write to the device within the programmed timeout window. Otherwise, the ALARM pin asserts low, and the ALARM_STATUS.WD_FLT bit is set to 1. The WD_FLT bit is sticky. After a WD_FLT has been asserted, WDT.WDT_EN must be set to 0 to clear the WDT condition. Then the WDT can be re-enabled. The WDT condition is also cleared by issuing a software or hardware reset. After the WDT condition is clear, WD_FLT is cleared by reading the ALARM_STATUS register. When using multiple AFEx82H1 devices in a daisy-chain configuration, connect the open-drain ALARM pins of all devices together to form a wired-OR network. The watchdog timer can be enabled in any number of the devices in the chain; although, enabling the watchdog timer in one device in the chain is usually sufficient. The wired-OR ALARM pin can be pulled low in response to the simultaneous presence of different trigger conditions in the devices in the daisy-chain. The host processor must read the ALARM_STATUS register of each device to know all the fault conditions present in the chain. The watchdog timeout period is based on a 1200-Hz clock (1.2288 MHz / 1024). Detailed Description Overview The AFEx82H1 feature a 16-bit (AFE882H1) or 14‑bit (AFE782H1) string DAC with voltage output buffer. Both devices have a buffered voltage output and are designed for use in three‑wire or four-wire sensor transmitters or analog output modules. The DAC has calibration registers for setting gain and offset values for adjusting the DAC outputs. The DAC also has different output slewing modes that allow for a programmable linear slew and a sinusoidal shaped output slew. The AFEx82H1 also feature a 12‑bit SAR ADC that can be multiplexed to measure different inputs, including external nodes and internal nodes for diagnostic measurements on the device. The ADC is capable of making direct-mode measurements with on-demand conversions or auto-mode measurements through continuous conversions using a channel sequencer with a multiplexer. The devices have optional alarm configurations with fault detection and alarm actions. Device communication and programming are done through an SPI, SPI plus a UART interface, or through the UART break mode (UBM). With the SPI, a cyclic redundancy check (CRC) is implemented by default, which can be disabled. Additionally, communications can be monitored with a watchdog timer (WDT) that alerts the user if the device becomes unresponsive to periodic communication. For the field transmitter, a HART interface is created through modulation and demodulation using the SPI or UART. The demodulation of the input signal is done using the combination of the external and internal band-pass filtering. The AFEx82H1 feature a 1.25-V, onboard precision voltage reference, and an integrated precision oscillator. Throughout this data sheet, register and bit names are combined with a period to use the following format: <register_name>.<bit_name>. For example, the CLR bit in the DAC_CFG register is labeled DAC_CFG.CLR. Overview The AFEx82H1 feature a 16-bit (AFE882H1) or 14‑bit (AFE782H1) string DAC with voltage output buffer. Both devices have a buffered voltage output and are designed for use in three‑wire or four-wire sensor transmitters or analog output modules. The DAC has calibration registers for setting gain and offset values for adjusting the DAC outputs. The DAC also has different output slewing modes that allow for a programmable linear slew and a sinusoidal shaped output slew. The AFEx82H1 also feature a 12‑bit SAR ADC that can be multiplexed to measure different inputs, including external nodes and internal nodes for diagnostic measurements on the device. The ADC is capable of making direct-mode measurements with on-demand conversions or auto-mode measurements through continuous conversions using a channel sequencer with a multiplexer. The devices have optional alarm configurations with fault detection and alarm actions. Device communication and programming are done through an SPI, SPI plus a UART interface, or through the UART break mode (UBM). With the SPI, a cyclic redundancy check (CRC) is implemented by default, which can be disabled. Additionally, communications can be monitored with a watchdog timer (WDT) that alerts the user if the device becomes unresponsive to periodic communication. For the field transmitter, a HART interface is created through modulation and demodulation using the SPI or UART. The demodulation of the input signal is done using the combination of the external and internal band-pass filtering. The AFEx82H1 feature a 1.25-V, onboard precision voltage reference, and an integrated precision oscillator. Throughout this data sheet, register and bit names are combined with a period to use the following format: <register_name>.<bit_name>. For example, the CLR bit in the DAC_CFG register is labeled DAC_CFG.CLR. The AFEx82H1 feature a 16-bit (AFE882H1) or 14‑bit (AFE782H1) string DAC with voltage output buffer. Both devices have a buffered voltage output and are designed for use in three‑wire or four-wire sensor transmitters or analog output modules. The DAC has calibration registers for setting gain and offset values for adjusting the DAC outputs. The DAC also has different output slewing modes that allow for a programmable linear slew and a sinusoidal shaped output slew. The AFEx82H1 also feature a 12‑bit SAR ADC that can be multiplexed to measure different inputs, including external nodes and internal nodes for diagnostic measurements on the device. The ADC is capable of making direct-mode measurements with on-demand conversions or auto-mode measurements through continuous conversions using a channel sequencer with a multiplexer. The devices have optional alarm configurations with fault detection and alarm actions. Device communication and programming are done through an SPI, SPI plus a UART interface, or through the UART break mode (UBM). With the SPI, a cyclic redundancy check (CRC) is implemented by default, which can be disabled. Additionally, communications can be monitored with a watchdog timer (WDT) that alerts the user if the device becomes unresponsive to periodic communication. For the field transmitter, a HART interface is created through modulation and demodulation using the SPI or UART. The demodulation of the input signal is done using the combination of the external and internal band-pass filtering. The AFEx82H1 feature a 1.25-V, onboard precision voltage reference, and an integrated precision oscillator. Throughout this data sheet, register and bit names are combined with a period to use the following format: <register_name>.<bit_name>. For example, the CLR bit in the DAC_CFG register is labeled DAC_CFG.CLR. The AFEx82H1 feature a 16-bit (AFE882H1) or 14‑bit (AFE782H1) string DAC with voltage output buffer. Both devices have a buffered voltage output and are designed for use in three‑wire or four-wire sensor transmitters or analog output modules. The DAC has calibration registers for setting gain and offset values for adjusting the DAC outputs. The DAC also has different output slewing modes that allow for a programmable linear slew and a sinusoidal shaped output slew. AFEx82H1AFE882H1AFE782H1Both devices have a buffered voltage output and are designed for use in three‑wire or four-wire sensor transmitters or analog output modules.The AFEx82H1 also feature a 12‑bit SAR ADC that can be multiplexed to measure different inputs, including external nodes and internal nodes for diagnostic measurements on the device. The ADC is capable of making direct-mode measurements with on-demand conversions or auto-mode measurements through continuous conversions using a channel sequencer with a multiplexer. The devices have optional alarm configurations with fault detection and alarm actions.AFEx82H1Device communication and programming are done through an SPI, SPI plus a UART interface, or through the UART break mode (UBM). With the SPI, a cyclic redundancy check (CRC) is implemented by default, which can be disabled. Additionally, communications can be monitored with a watchdog timer (WDT) that alerts the user if the device becomes unresponsive to periodic communication., SPI plus a UART interface,For the field transmitter, a HART interface is created through modulation and demodulation using the SPI or UART. The demodulation of the input signal is done using the combination of the external and internal band-pass filtering.The AFEx82H1 feature a 1.25-V, onboard precision voltage reference, and an integrated precision oscillator.AFEx82H1Throughout this data sheet, register and bit names are combined with a period to use the following format: <register_name>.<bit_name>. For example, the CLR bit in the DAC_CFG register is labeled DAC_CFG.CLR. Functional Block Diagram Functional Block Diagram Feature Description Digital-to-Analog Converter (DAC) Overview The AFEx82H1 feature a 16-bit (AFE882H1) or 14‑bit (AFE782H1) string DAC followed by an output voltage buffer. Using an external circuit, the device output voltage can be translated to different output voltages and output currents for use in 3‑wire or 4-wire sensor transmitters or analog output modules. The DAC is configured to support a 0‑V to 2.5‑V range of operation. The alarm function is triggered when PVDD exceeds the valid configuration range of 2.7 V to 5.5 V; see also . DAC Resistor String shows that the resistor string structure consists of a series of resistors, each of value R. The code loaded to the DAC determines the node on the string at which the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. The resistor string architecture has inherent monotonicity, voltage output, and low glitch. DAC Resistor String DAC Buffer Amplifier The VOUT output pin is driven by the DAC output buffer amplifier. The output amplifier default settings are designed to drive capacitive loads as high as 100 pF without oscillation. The output buffer is able to source and sink 1 mA. The device implements short-circuit protection for momentary output shorts to ground and VDD supply. The source and sink short-circuit current thresholds are set to 5 mA. DAC Transfer Function The following equation describes the DAC transfer function, which is the relationship between internal signal DAC_CODE and output voltage VOUT: V O U T = D A C _ C O D E 2 N × F S R where DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N – 1. N = DAC_CODE resolution in bits (16 for the AFE882H1 and 14 for the AFE782H1). FSR = VOUT full-scale range = 2.5 V. DAC Gain and Offset Calibration The AFEx82H1 provide DAC gain and offset calibration capability to correct for end-point errors present in the system. Implement the gain and offset calibration using two registers, DAC_GAIN.GAIN and DAC_OFFSET.OFFSET. Update DAC_DATA register after gain or offset codes are changed for the new values to take effect. The DAC_GAIN can be programmed from 0.5 to 1.499985 using . D A C _ G A I N = 1 2 + G A I N 2 N where N = DAC_GAIN resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. GAIN is the decimal value of the DAC_GAIN register setting. GAIN data are left justified; the last two LSBs in the DAC_GAIN register are ignored for the AFE782H1. The example DAC_GAIN settings for the AFE882H1 are shown in . DAC_GAIN Setting vs GAIN Code DAC_GAIN GAIN (HEX) 0.5 0x0000 1.0 0x8000 1.499985 0xFFFF The DAC_OFFSET is stored in the DAC_OFFSET register using 2's-complement encoding. The DAC_OFFSET value can be programmed from –2(N–1) to 2(N–1) – 1 using . D A C _ O F F S E T = - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i where N = DAC_OFFSET resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. OFFSETMSB = MSB bit of the DAC_OFFSET register. OFFSET i = The rest of the bits of the DAC_OFFSET register. i = Position of the bit in the DAC_OFFSET register. OFFSET data are left justified; the last two LSBs in the DAC_OFFSET register are ignored for the device. The most significant bit determines the sign of the number and is called the sign bit. The sign bit has the weight of –2(N–1) as shown in . The example DAC_OFFSET settings for the AFE882H1 are shown in . DAC_OFFSET Setting vs OFFSET Code DAC_OFFSET OFFSET (HEX) 32767 0x7FFF 1 0x0001 0 0x0000 –1 0xFFFF –2 0xFFFE –32768 0x8000 The following transfer function is applied to the DAC_DATA.DATA based on the DAC_GAIN and DAC_OFFSET values: D A C _ C O D E = ( D A T A × D A C _ G A I N ) + D A C _ O F F S E T where DAC_CODE is the internal signal applied to the DAC. DATA is the decimal value of the DAC_DATA register. DAC_GAIN and DAC_OFFSET are the user calibration settings. DATA data are left justified; the last two LSBs in the DAC_DATA register are ignored for the AFE782H1. Substituting DAC_GAIN and DAC_OFFSET in with and results in: D A C _ C O D E = ( D A T A × 1 2 + G A I N 2 N ) - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i The multiplier is implemented using truncation instead of rounding. This truncation can cause a difference of one LSB if rounding is expected. shows the DAC calibration path. DAC Calibration Path Programmable Slew Rate The slew rate feature controls the rate at which the output voltage or current changes. This feature is disabled by default and is enabled by writing a logic 1 to the DAC_CFG.SR_EN bit. With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load. With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by DAC_CFG.SR_STEP[2:0] and DAC_CFG.SR_CLK[2:0]. SR_CLK defines the rate at which the digital slew updates. SR_STEP defines the amount by which the output value changes at each update. The register descriptions show different settings for SR_STEP and SR_CLK. The time required for the output to slew is expressed as : S l e w   T i m e   =   D e l t a   C o d e   C h a n g e S l e w   S t e p   ×   S l e w   C l o c k   R a t e where Slew Time is expressed in seconds Slew Step is controlled by DAC_CFG.SR_STEP Slew Clock Rate is controlled by DAC_CFG.SR_CLK When the slew-rate control feature is enabled, the output changes at the programmed slew rate. This configuration results in a staircase formation at the output. If the clear code is asserted (see ), the output slews to the DAC_CLR_CODE value at the programmed slew rate. When new DAC data are written, the output starts slewing to the new value at the slew rate determined by the current DAC code and the new DAC data. Two slew-rate control modes are available: linear (default) and sinusoidal. and show the typical rising and falling DAC output waveforms, respectively. Linear Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Linear Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt Sinusoidal mode enables fast DAC settling while improving analog rate of change characteristics. Sinusoidal mode is selected by the DAC_CFG.SR_MODE bit. and show the typical rising and falling DAC output waveforms with sinusoidal slew-rate control, respectively. Sinusoidal Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Sinusoidal Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt If the slew-rate feature is disabled while the DAC is executing the slew-rate command, the slew-rate operation is aborted, and the DAC output goes to the target code. DAC Register Structure and CLEAR State The AFE882H1 DAC has a 16-bit voltage output, and the AFE782H1 DAC has a 14-bit voltage output. The output range is 0 V to 2.5 V. The AFEx82H1 provide the option to quickly set the DAC output to the value set in the DAC_CLR_CODE register without writing to the DAC_DATA register, referred to as the CLEAR state. For register details, see . Transitioning from the DAC_DATA to the DAC_CLR_CODE is synchronous to the clock. If slew mode is enabled, the output slews during the transition. shows the full AFEx82H1 DAC_DATA signal path. The devices synchronize the DAC_DATA code to the internal clock, causing up to 2.5 internal clock cycles of latency (2 μs) with respect to the rising edge of CS or the end of a UBM command. Update DAC_GAIN and DAC_OFFSET values when DAC_CFG.SR_EN = 0 to avoid an IRQ pulse generated by SR_BUSY. Set the DAC to CLEAR state either by: Setting DAC_CFG.CLR. Configuring the DAC to transition to the CLEAR state in response to an alarm condition. Using the SDI pin in UBM as the CLEAR state input pin. Method 1 is a direct command to the AFEx82H1 to set the DAC to CLEAR state. Set the DAC_CFG.CLR bit to 1h to set the DAC to CLEAR state. Method 2 is controlled by settings of ALARM_ACT register. For details of conditions and other masks required to use this method, see and . Method 3 supports setting the DAC to CLEAR state without writing to the AFEx82H1. This pin-based DAC CLEAR state function is available only in UBM on the SDI pin. For details of connection options based on communication modes and pins used in each mode, see . Set the appropriate pin high to drive the DAC to CLEAR state. DAC Data Path Analog-to-Digital Converter (ADC) Overview The AFEx82H1 feature a monitoring system centered on a 12-bit successive approximation register (SAR) ADC and a highly flexible analog multiplexer. The monitoring system is capable of sensing up to two external inputs, as well as several internal device signals. The ADC uses the VREFIO pin voltage as a reference. The ADC timing signals are derived from an on-chip oscillator. The conversion results are accessed through the device serial interface. ADC Operation The device ADC supports direct-mode and auto-mode conversions. Both conversion modes use a custom channel sequencer to determine which of the input channels are converted by the ADC. The sequence order is fixed. The user selects the start channel and stop channel of the conversion sequence. The conversion method and channel sequence are specified in the ADC Configuration registers. The default conversion method is auto-mode. shows the ADC conversion sequence. ADC Conversion Sequence To use the ADC, first enable the ADC buffer by setting ADC_CFG.BUF_PD = 0. Then wait at least 210 μs before setting the trigger using the TRIGGER.ADC bit. An internal delay is forced if the trigger signal is sent before the timer has expired. Make sure the ADC is not converting before setting the ADC_CFG.BUF_PD = 1. If ADC_CFG.BUF_PD is set to 1 while the ADC is still converting, the internal timer delays this command. When the timer expires, the enable signal for the ADC is cleared, and the current conversion finishes before powering down the ADC and the ADC Buffer. A trigger signal must occur for the ADC to exit the idle state. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode conversion, the selected ADC input channels are converted on demand by issuing an ADC trigger signal. After the last enabled channel is converted, the ADC enters the idle state and waits for a new trigger. Read the results of the ADC conversion through the register map. Direct-mode conversion is typically used to gather the ADC data of any of the data channels. In direct-mode, use the ADC_BUSY bit to determine when a direct-mode conversion is complete and the ADC has returned to the idle state. Direct mode is set by writing ADC_CFG.DIRECT_MODE = 1. In auto-mode conversion, the selected ADC input channels are converted continuously. The conversion cycle is initiated by issuing an ADC trigger. Upon completion of the first conversion sequence, another sequence is automatically started. Conversion of the selected channels occurs repeatedly until the auto-mode conversion is stopped by clearing the ADC trigger signal. Auto-mode conversion is not typically used to gather the ADC data. Instead, auto-mode conversions are used in combination with upper and lower ADC data thresholds to detect when the data has exceeded the programmable out-of-range alarm thresholds. Auto mode is set by writing ADC_CFG.DIRECT_MODE = 0. Regardless of the selected conversion method, update the ADC configuration register only while the ADC is in the idle state. Do not change the ADC configuration bits while the ADC is converting channels. Before changing configuration bits, disable the ADC and verify that GEN_STATUS.ADC_BUSY = 0. ADC Custom Channel Sequencer The device uses a custom channel sequencer to control the multiplexer of the ADC. The ADC sequencer allows the user to specify which channels are converted. The sequencer consists of 16 indexed slots with programmable start and stop index fields to configure the start and stop conversion points. In direct-mode conversion, the ADC converts from the start index to the stop index once and then stops. In auto-mode conversion, the ADC converts from the start to stop index repeatedly until the ADC is stopped. shows the indexed custom channel sequence slots available in the device. ADC MUX Control lists the ADC input channel assignments for the sequencer. Indexed Custom Channel Sequence CCS POINTER CHANNEL CONV_RATE RANGE 0 OFFSET 2560 Hz VREF 1 AIN0 Programmable Programmable 2 AIN1 Programmable Programmable 3 TEMP 2560 Hz VREF 4 SD0 (VREF) 2560 Hz VREF 5 SD1 (PVDD) 2560 Hz VREF 6 SD2 (VDD) 2560 Hz VREF 7 SD3 (ZTAT) 2560 Hz VREF 8 SD4 (VOUT) 2560 Hz 2 × VREF 9-15 GND 2560 Hz VREF Use the ADC_INDEX_CFG register to select the channels. The order of the channels is fixed and shown in . Then, use ADC_INDEX_CFG.START and ADC_INDEX_CFG.STOP to select the range of indices to convert. If these two values are the same, then the ADC only converts a single channel. If the START and STOP values are different, then the ADC cycles through the corresponding indices. By default, all channels are configured to be converted; START = 0 and STOP = 8. If the AIN1 channel is not configured as an ADC input, then the result for this channel is 0x000. The minimum time for a conversion is still allotted to AIN1 if the channel is within the START and STOP range. If START is configured to be greater than STOP, then the device interprets the conversion sequence as if START = STOP. In direct mode, each selected channel in the ADC_INDEX_CFG register is converted once per TRIGGER.ADC command. In auto mode, each channel selected in the ADC_INDEX_CFG register is converted once; after the last channel, the loop is repeated as long as the ADC is enabled. In auto mode, writing to TRIGGER.ADC = 1 starts the conversions. Writing TRIGGER.ADC = 0 disables the ADC after the current channel being converted finishes. In direct mode, writing TRIGGER.ADC = 1 starts the sequence. When the sequence ends, then TRIGGER.ADC is self-cleared. A minimum of 20 clock cycles is required to perform one conversion. The ADC clock is derived from the internal oscillator and divided by 16, which gives an ADC clock frequency of 1.2288 MHz / 16 = 76.8 kHz, for a clock period = 13.02 μs. Each of the internal nodes has a fixed conversion rate. Pins AIN0 and AIN1 have programmable conversion rates (see also the ADC_CFG register). Pins AIN0 and AIN1 also have a configurable range. The input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit. If any ADC configuration bits are changed, the following sequence is recommended: Disable the ADC Wait for ADC_BUSY to go low Change the configuration Restart the conversions ADC_BUSY can be monitored in the GEN_STATUS register. If the ADC is configured for direct mode (ADC_CFG.DIRECT_MODE = 1), then after setting the desired channels to convert, write a 1 to TRIGGER.ADC. This bit is self-cleared when the sequence is finished converting. This command converts all the selected channels once. To initiate another conversion of the channels, send another TRIGGER.ADC command. ADC Synchronization The trigger signal must be generated for the ADC to exit the idle state and start conversions. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode, use the GEN_STATUS.ADC_BUSY bit to determine when a direct-mode conversion is complete, and the ADC has returned to the idle state. Similarly, monitor the TRIGGER.ADC bit to see if the ADC has returned to the idle state. ADC Offset Calibration Channel 0 of the CCS pointer is named OFFSET. The OFFSET channel is used to calibrate and improve the ADC offset performance. Convert the OFFSET channel, and use the result as a calibration for the ADC offset in subsequent measurements. This ADC channel samples VREF / 2 and compares this result against 7FFh as a measure of the ADC offset. The data rate for the ADC measuring this channel is 2560 Hz. The ADC conversion for the OFFSET channel is subtracted from 7FFh and the resulting value is stored in ADC_OFFSET (28h). The offset can be positive or negative; therefore, the value is stored in 2’s complement notation. With the subtraction from 7FFh, ADC_OFFSET is the negative of the offset. This value is subtracted from conversions of the ADC by default. For direct measurements of the ADC, set ADC_BYP.OFST_BYP_EN to 1 to enable the offset bypass; see . External Monitoring Inputs The AFEx82H1 have two analog inputs for external voltage sensing. Channels 1 and 2 for the CCS pointer are for external monitoring inputs that can be measured by pins AIN0 and AIN1, respectively. The input range for the analog inputs is configurable to either 0 V to 1.25 V or 0 V to 2.5 V. The analog inputs conversion values are stored in straight binary format in the ADC registers. The ADC resolution can be computed by : 1   L S B = V R A N G E 2 12 where VRANGE = 2.5 V for the 0‑V to 2.5‑V input range or 1.25 V for the 0‑V to 1.25‑V input range. and detail the transfer characteristics. ADC Transfer Characteristics Transfer Characteristics INPUT VOLTAGE CODE DESCRIPTION IDEAL OUTPUT CODE ≤1 LSB NFSC Negative full-scale code 000 1 LSB to 2 LSB NFSC + 1 Negative full-scale code plus 1 001 (VRANGE / 2) to (VRANGE / 2) + 1 LSB MC Midcode 800 (VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSB MC + 1 Midcode plus 1 801 ≥ VRANGE – 1 LSB PFSC Positive full-scale code FFF For these external monitoring inputs, the ADC is configurable for both data rate and voltage range. The data rate is set to either 640 Hz, 1280 Hz, 2560 Hz, or 3840 Hz with the ADC_CFG.CONV_RATE bits. The range of the ADC measurement is set with the ADC_CFG.AIN_RANGE bit. The ADC range is 2 × VREF when the bit = 0; the ADC range is VREF when the bit = 1. When the ADC conversion is completed for AIN0 and AIN1, the resulting ADC data are stored in the ADC_AIN0.DATA and ADC_AIN1.DATA bits at 24h and 25h of the register map. If the external monitoring inputs are not used, connect the AIN0 and AIN1 pins to GND through a 1-kΩ resistor. Temperature Sensor Channel 3 of the CCS is used to measure the die temperature of the device. The ADC measures an internal temperature sensor that measures a voltage complementary to the absolute temperature (CTAT). This CTAT voltage has a negative temperature coefficient. The ADC converts this voltage at a data rate of 2560 Hz. When the ADC conversion is completed, the data are found in the ADC_TEMP.DATA bits (address 26h). The relationship between the ambient temperature and the ADC code is shown in #GUID-A307B900-C147-485E-AF3B-AFFF3E5B4EBD/GUID-09CDF47B-A831-42BA-B93C-B59905D9CECB: ADC Code = 2681   - 11 × T A ( ° C ) Self-Diagnostic Multiplexer In addition to the ADC offset, the two external monitoring inputs, and the temperature sensor, the ADC of the AFEx82H1 has five other internal inputs to monitor the reference voltage, the power supplies, a static voltage, and the DAC output. These five voltages measurements are part of the self-diagnostic multiplexer (SD0 to SD4) measurements of the ADC, and are reported in the ADC_SD_MUX register at 27h; see also . Channel 4 (SD0) measures the reference voltage of the device. The ADC measures the reference voltage through a resistor divider (divide by two). Be aware that all ADC measurements are a function of the reference; using SD0 to measure the reference is not revealing as a diagnostic measurement. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 5 (SD1) measures the PVDD power supply of the device. The ADC measures the PVDD voltage through a resistor divider (divide by six). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 6 (SD2) measures the VDD power supply of the device. When channel 6 is selected, the ADC measures the VDD voltage through a resistor divider (divide by 2). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 7 (SD3) is a ZTAT (zero temperature coefficient) voltage. This internal voltage is nominally 0.6 V with a low temperature drift and does not depend on the reference voltage. An ADC measurement of ZTAT voltage can be useful to determine the state of the reference voltage. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 8 (SD4) measures the VOUT of the DAC. The ADC measures the VOUT voltage through a resistor divider (divide by two). The data rate for this conversion is 2560 Hz and the range of the ADC is set to 2 × VREF. ADC Bypass To test the offset, modify the ADC data path by programming the bypass data register, ADC_BYP.DATA (2Eh). This read/write register is used in two different ways. First, by setting the ADC_BYP.OFST_BYP_EN to 1, this bypass data register is used as a substitute for the ADC_OFFSET. However, if the ADC_BYP.DATA data must be stored in the ADC_OFFSET register, use the second method. Second, the ADC_BYP.DATA is used to set a known value into the ADC readback register of the channel being converted. Write the desired data into ADC_BYP.DATA, set the ADC_BYP.DATA_BYP_EN bit, and convert the selected channel. When ADC_BYP.DATA_BYP_EN bit is set to 1, the ADC conversion is bypassed, and the value of ADC_BYP.DATA is written into the selected ADC channel readback register. This setting is used to test the alarm settings of the ADC. When the ADC bypass is unused, set the ADC_BYP.DATA to 000h. shows the ADC bypass data flow. ADC Bypass Data Flow Programmable Out-of-Range Alarms The AFEx82H1 are capable of continuously analyzing the supplies, external ADC inputs, DAC output voltage, reference, internal temperature, and other internal signals for normal operation. Normal operation for the conversion results is established through the lower- and upper-threshold registers. When any of the monitored inputs are out of the specified range, the corresponding alarm bit in the alarm status registers is set. The alarm bits in the alarm status registers are latched. The alarm bits are referred to as being latched because the alarm bits remain set until read by software. This design makes sure that out-of-limit events cannot be missed if the software is polling the device periodically. All bits are cleared when reading the alarm status registers, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle. When the alarm event is cleared, the DAC is reloaded with the contents of the DAC active registers, which allows the DAC outputs to return to the previous operating point without any additional commands All alarms can be used to generate a hardware interrupt signal on the ALARM pin; see also . In addition, describes how the alarm action can be individually configured for each alarm. Alarm-Based Interrupts One or more of the available alarms can be set to activate the ALARM pin. Connect the ALARM pin as an optional hardware interrupt to the host. The host can query the alarm status registers to determine the alarm source upon assertion of the interrupt. Any alarm event activates the pin, as long as the alarm is not masked in the ALARM_STATUS_MASK register. When an alarm event is masked, the occurrence of the event sets the corresponding status bit in the alarm status registers, but does not activate the ALARM pin. The ALARM pin output depends on ALARM_STATUS and ALARM_STATUS_MASK register settings, independent of ALARM_ACT register settings. Alarm Action Configuration Register The AFEx82H1 provides an alarm action configuration register: ALARM_ACT, . Writing to this register selects the device action that automatically occurs for a specific alarm condition. The ALARM_ACT register determines how the main DAC responds to an alarm event from either an ADC conversion on the self-diagnostics channels (AIN0, AIN1, and TEMP), or from a CRC, WDT, VREF, TEMP_HI, or TEMP_LO fault. Only these faults cause a response by the DAC. Any other alarm status events trigger the ALARM pin. There are four options for alarm action. In case different settings are selected for different alarm conditions, the following low-to-high priority is considered when taking action: 0. → No action 1. → DAC CLEAR state 2. → VOUT alarm voltage 3. → VOUT Hi-Z If option 1 is selected when the alarm event occurs, then the DAC is forced to the clear code. This operation is done by controlling the input code to the DAC. If option 2 is selected when the alarm event occurs, then VOUT is forced to the alarm voltage. The alarm voltage is controlled by either pin or register bit. If SPECIAL_CFG.AIN1_ENB = 0, then the AIN1 pin controls alarm polarity. Also, register bit SPECIAL_CFG.ALMV_POL can be used. If either of these signals = 1, then the alarm voltage is high; otherwise, the alarm voltage is low. The SPECIAL_CFG register is only reset with POR, so the user setting remains intact through hardware or software resets. If option 3 is selected when the alarm event occurs, then the VOUT buffer is put into Hi-Z. If multiple events occur, then the highest setting takes precedence. Option 3 has the highest priority. To disable action response to an alarm, set the corresponding bits in ALARM_ACT to 0h. Alarm action response is cleared either when the triggered condition bit resets (behavior depends on whether the fault bit in ALARM_STATUS is sticky or not), or by changing the action configuration to 0h. An alarm action, as configured, executes when an alarm occurs depending on ALARM_STATUS and ALARM_ACT registers. Action response is independent of ALARM_STATUS_MASK settings. Alarm Voltage Generator shows that the alarm voltage is generated independently from the DAC output voltage. The alarm polarity control logic selects the output level of the alarm voltage generator. The alarm action control logic selects between the DAC output and alarm voltage generator output voltages. The alarm action control logic also controls the output buffer Hi-Z switch. Alarm Voltage Generator Architecture During normal operation, the expected VOUT voltage depends on the DAC_CODE. The ADC thresholds for the SD4 (VOUT) diagnostic channel are set around the programmed DAC_CODE. During the alarm condition, if the alarm action changes the VOUT voltage to the alarm voltage, or switches the VOUT buffer into Hi-Z mode, the VOUT voltage no longer depends on the DAC_CODE. In this case, the SD4 (VOUT) diagnostic channel also reports the alarm. To clear this alarm, as long as all other alarm conditions are cleared, set the alarm action to either no action or to the DAC clear code. Applying either alarm action sets the VOUT voltage within the expected ADC thresholds and clears the alarm after the next ADC measurement of the SD4 (VOUT) channel. Give special consideration to the alarm logic during the transient events. When the new DAC_CODE goes beyond the SD4 (VOUT) alarm thresholds with the ADC monitoring the SD4 (VOUT) input in auto mode, the ADC conversion can occur while VOUT settles to a new value. This conversion can trigger a false alarm. There are two ways to prevent this false alarm: Use direct mode and allow VOUT to settle before triggering the next ADC conversion. Set ADC_CFG.FLT_CNT > 0. With this configuration, a single error in SD4 or any other measurement does not cause an alarm condition to be asserted. Temperature Sensor Alarm Function The AFEx82H1 continuously monitor the internal die temperature. In addition to the ADC measurement, the temperature sensor triggers a comparator to show a thermal warning and a thermal error. A thermal warning alarm is set when the temperature exceeds 85°C. Additionally, a thermal error alarm is set when the die temperature exceeds 130°C. The thermal warning and thermal error alarms can be configured to set the ALARM pin and are indicated in the ALARM_STATUS register. These alarms can be masked with the ALARM_MASK register and also be configured to control the DAC output with the ALARM_ACT register. Internal Reference Alarm Function The devices provide out-of-range detection for the reference voltage. When the reference voltage exceeds ±5% of the nominal value, the reference alarm flag (VREF_FLT bit) is set. Make sure that a reference alarm condition has not been issued by the device before powering up the DAC output. ADC Alarm Function The AFEx82H1 provide independent out-of-range detection for each of the ADC inputs. shows the out-of-range detection block. When the measurement is out of range, the corresponding alarm bit is set to flag the out-of-range condition. ADC Out-of-Range Alarm An alarm event is only registered when the monitored signal is out of range for N number of consecutive conversions, where N is configured in the ADC_CFG.FLT_CNT false alarm register settings. If the monitored signal returns to the normal range before N consecutive conversions, an alarm event is not issued. If an ADC input signal is out of range and the alarm is enabled, then the corresponding alarm bit is set to 1. However, the alarm condition is cleared only when the conversion result returns to a value less than the high-limit register setting and greater than the low-limit register setting by the number of codes specified by the hysteresis setting (see ). The hysteresis is a programmable value between 0 LSB to 127 LSB in the ADC_CFG.HYST register. ADC Alarm Hysteresis Fault Detection There are two fields within the ADC_CFG register: FLT_CNT and HYST. These fields are applied to the assertion and deassertion of alarm conditions for all the ADC channels. ADC_CFG.FLT_CNT determines the maximum number of accepted consecutive failures before an alarm condition is reported. For example, if ADC_CFG.FLT_CNT is set for two counts, then three consecutive conversions must be outside of the thresholds to trigger an alarm. Each failure counts towards the FLT_CNT limit even if the failures alternate between high threshold and low threshold. ADC_CFG.HYST sets the hysteresis used by the alarm-detection circuit. After an alarm is triggered, the hysteresis is applied before the alarm condition is released. In the case of the high threshold, the hysteresis is subtracted from the threshold value. In the case of the low threshold limit, the hysteresis is added to the threshold value. Channels AIN0, AIN1, and TEMP have high and low thresholds associated with them. If a conversion value falls outside of these limits (that is, if TEMP < low threshold or TEMP > high threshold), an alarm condition for that channel is set. The alarms are disabled by setting 0x000 for the low threshold and 0xFFF for the high threshold, respectively. These alarms are disabled by default. Because the configuration fields for the thresholds are only eight bits wide, the four LSBs are hardcoded for each threshold. The high thresholds four LSBs are hardcoded to 0xF, and the low thresholds four LSBs are hardcoded to 0x0. All the self diagnostic (SD) channels have fixed thresholds, except SD4, which measures the VOUT of the main DAC. The threshold for SD4 tracks the VOUT with respect to the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/TABLE_BCL_BCQ_PQB shows the calculations used to determine the high and low ADC thresholds for each SD channel. The limits in the two right-most columns are determined by the threshold columns to the left and given some margin. The four LSBs are assigned as described previously. Self Diagnostic (SD) Alarm ADC Thresholds SD ADC INPUT ACCEPTED LOW VALUE ACCEPTED HIGH VALUE LOW THRESHOLD HIGH THRESHOLD ADC LOW (HEX) ADC HIGH (HEX) SD0 VREF/2 VREF/2 – 9% – 25 mV VREF/2 + 9% + 25 mV 0.54375 V 0.70625 V 0x6D0 0x92F SD1 PVDD/6 1.65/6 – 25 mV 6/6 + 25 mV 0.25 V 1.025 V 0x310 0xD3F SD2 VDD/2 1.6/2 – 25 mV 2/2 + 25 mV 0.775 V 1.025 V 0x9C0 0xD3F SD3 0.6 V 0.6 V – 9% – 25 mV 0.6 V + 9% + 25 mV 0.521 V 0.679 V 0x690 0x8CF SD4 VOUT/2 VOUT/2 – 6 mV VOUT/2 + 6 mV VOUT – 12 mV VOUT + 12 mV Expected – 0x040 Expected + 0x040 The alarm threshold for the SD4 input depends on the expected ADC measurement based on the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/EQUATION-BLOCK_QF3_WXF_QVB shows the expected ADC code for SD4. ADC Expected Code = DAC_CODE[MSB:MSB-11] IRQ The devices include an interrupt request (IRQ) to communicate the occurrence of a variety of events to the host controller. The IRQ block initiates interrupts that are reported internally in a status register, externally on the IRQ pin if the function is enabled, or on the ALARM pin if the condition is from the ALARM_STATUS register. shows the IRQ block diagram. IRQ Block Diagram There are three registers that can generate interrupts: GEN_STATUS, MODEM_STATUS, and ALARM_STATUS. Each of these registers has a corresponding STATUS_MASK register. The mask register controls which of the events trigger an interrupt. Writing a 1 in the mask register masks, or disables, the event from triggering an interrupt. Writing a 0 in the mask register allows the event to trigger an IRQ. All bits are masked by default. Some status bits are sticky. Reading the corresponding register clears a sticky bit, unless the condition still exists. The IRQ is configured through CONFIG.IRQ_LVL to be edge- or level-sensitive. Set this bit to logic 1 to enable level-sensitive functionality (default). In edge-sensitive mode, the IRQ signal is a synchronous pulse, one internal clock period wide (813 ns). In level-sensitive mode, the IRQ is set and remains set as long as the condition exists. After the IRQ condition is removed, the condition is cleared by reading the corresponding status register. Trying to clear the bit while the condition still exists does not allow the bit to be cleared if the bit is sticky. CONFIG.IRQ_POL determines the active level of the IRQ. A logic 1 configures IRQ to be active high. When using edge-sensitive IRQ signals, there is a clock cycle delay for synchronization and edge detection. With a 307.2-kHz clock, this delay is up to 3.26 μs. For level-sensitive mode, the delay is approximately 10 ns to 20 ns. Most status bits have two versions within the design. The first version is an edge event that is created when the status is asserted. This signal is used to generate edge-sensitive IRQs. This edge detection prevents multiple status events from blocking one another. The second version is the sticky version of the status bit. This signal is set upon assertion of the status bit and cleared when the corresponding status register is read, as long as the status condition does not still persist. Signals GEN_IRQ, MODEM_IRQ, and ALARM_IRQ are driven by the logical OR of the of the status bits within the corresponding register. If a status bit is unmasked and the sticky version of that bit has been asserted, and the IRQ is level-sensitive, then an interrupt is triggered as soon as the bit is unmasked. If the IRQ is edge-sensitive then a status event must occur after the bit has been unmasked to assert an interrupt. FIFO flags are not sticky; therefore, an IRQ can be triggered, but the status flag can be deasserted by the time the status information is transmitted at the output. For example, If FIFO_U2H_LEVEL_FLAG is unmasked and the FIFO_U2H level drops below the set threshold, the IRQ triggers. If the device is configured to output UBM IRQ messages and a HART data byte is received on UARTIN after the IRQ, but before the UBM captures the IRQ status, then the IRQ status and data information reads back all zeros. If UBM IRQ mode is used, wait until the IRQ message is fully transmitted on UARTOUT before putting data on UARTIN. HART Interface On the AFEx82H1, a HART frequency-shift keyed (FSK) signal can be modulated onto the MOD_OUT pin. illustrates the output current versus time operation for a typical HART interface. Output Current vs Time DC current = 6 mA To enable the HART interface, set the HART_EN bit in the MODEM_CFG register. An external capacitor, placed in series between the RX_IN pin and HART FSK source, is required to ac-couple the HART FSK signal to the RX_IN pin. The recommended capacitance for this external capacitor is 2.2 nF. If additional filtering is required, the AFEx82H1 also support an external band-pass filter. For this configuration, use the RX_INF pin instead of RX_IN pin. FIFO Buffers First-in, first-out (FIFO) buffers are used to transmit and receive HART data using both the SPI and UART. Both the transmit FIFO (FIFO_U2H) and receive FIFO (FIFO_H2U) buffers are 32 rows and 9-bits wide. The 9-bit width allows the storage of the parity bit with the data byte. Bit[8] is the parity bit as received by either the UART or HART demodulator, depending on the direction of the data flow. The device does not calculate the parity bit in this case, and transmits the data with the wrong parity bit if the wrong parity bit was received. Bits[7:0] are the data. The AFEx82H1 HART implementation is shown in . HART Architecture HART data bytes are enqueued into a transmit FIFO_U2H buffer using the SPI or UART. The input data bits are translated into the mark (1200 Hz) and space (2200 Hz) FSK analog signals (see ) used in HART communication by the internal HART transmit modulator. The receive demodulator enqueues HART data into the receive FIFO_H2U buffer. An arbiter is implemented with signals to CD and from the RTS pins to manage the HART physical connections on MOD_OUT, and either the RX_IN or RX_INF pin. To enable efficient and error-free communication, the arbiter in conjunction with the two FIFO buffers can be used to produce an IRQ for the system controller. An incorrect stop bit in the HART receive character causes a HART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the HART data are not enqueued into FIFO_H2U. If the frame error check is not masked, an IRQ event is also triggered. Similarly, an incorrect stop bit in the UARTIN character causes a UART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the UART data are not enqueued into FIFO_U2H. If the frame error check is not masked, an IRQ event is also triggered. FIFO Buffer Access In SPI only mode, both FIFO buffers are accessed using register addresses. HART bus communication activity is reported to the host controller through the IRQ pin and MODEM_STATUS register. See for recommended IRQ based communication techniques when using the AFEx82H1 to convert between the SPI and HART. Write to the FIFO_U2H_WR register to enqueue the HART transmit data into FIFO_U2H. Calculate the correct parity bit and include the parity bit with the data. Do not attempt to read data from the FIFO_U2H because a read request from the FIFO_U2H_WR register is not supported. The read from the FIFO_U2H_WR register returns the data from the dequeue pointer location of FIFO_U2H, but does not dequeue the data. Read the FIFO_H2U_RD register to dequeue the HART receive data from FIFO_H2U. If CRC is enabled and a CRC error occurs during a read request, no data are dequeued from the FIFO_H2U buffer, and the data in the readback frame are invalid. A write to the FIFO_H2U_RD register is ignored. When communicating with the HART modem through the UART interface in SPI plus UART mode, any character received on the UARTIN pin is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the clear-to-send (CTS) response is asserted. Similarly, any character received on the RX_IN or RX_INF pin is directly enqueued into FIFO_H2U. The character is then automatically dequeued from FIFO_H2U and transmitted on UARTOUT as a normal UART character. The FIFO buffers are accessed directly by the UART; therefore, do not use the FIFO_U2H_WR and FIFO_H2U_RD registers with the SPI. As a result of using FIFO_U2H in the data path, there is a latency from the UARTIN pin to the MOD_OUT pin; see also . Similarly, as a result of using FIFO_H2U, there is a latency from the RX_IN or RX_INF pin to the UARTOUT pin; see also . HART bus communication activity is interfaced to the host controller through the CD and RTS pins. If the CD and RTS pins are not used, poll the MODEM_STATUS register regularly to monitor the status of the modem. In UBM mode, any character received on the UARTIN pin that is not a part of a break command is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the CTS response is asserted. Although the UBM packets can access all registers, do not use the break command to write the HART transmit data into FIFO_U2H_WR register. Use the standard 8O1 UART character format to enqueue data into the FIFO_U2H buffer, and thus to the HART modulator. Similarly, do not use the break command to read the HART receive data from the FIFO_H2U_RD register. HART receive data are automatically dequeued from FIFO_H2U and transmitted on UARTOUT as normal UART characters in UBM mode. FIFO Buffer Flags Status bits exist for both transmit and receive FIFO buffers in the MODEM_STATUS, FIFO_STATUS and FIFO_H2U_RD registers. These include full, empty, and level flags. Buffer level flags are used to trigger IRQs for HART communication; see also . The status fields in the FIFO_H2U_RD register represent the state of FIFO_H2U before the read is performed and the data byte is dequeued. This implementation means that if the EMPTY_ FLAG is set, the data byte received in that frame is invalid. Similarly, the LEVEL field represents the 4 MSBs for the FIFO_H2U level before dequeuing. The LSB is not reported, and there are only five internal bits to represent 32 levels; therefore, the LEVEL = 0 is reported when the actual level is 0, 1, or 32. Use FULL_FLAG and EMPTY_FLAG when LEVEL = 0 to differentiate between these three cases. The FIFO_H2U and FIFO_U2H buffers have 32 levels; however, the level setting for generating IRQ events only uses four bits. For the receive FIFO_H2U buffer, the LSB in the FIFO level threshold comparison is always 1 (FIFO_CFG.H2U_LEVEL_SET[3:0], 1). This configuration is designed to alert the user when FIFO_H2U is getting nearly full so as to enable a timely data dequeue, and prevent the loss of incoming HART data due to FIFO overload. For this reason, the FIFO_H2U_LEVEL_FLAG is also a greater-than (>) comparison to the FIFO_CFG.H2U_LEVEL_SET. For example, if FIFO_CFG.H2U_LEVEL_SET = 4’b1000, then when the level of the FIFO_H2U > 5’b10001, the FIFO_H2U_LEVEL_FLAG is set. Setting FIFO_CFG.H2U_LEVEL_SET = 4’b1111 (default) effectively disables this flag. Use FIFO_H2U_FULL_ FLAG to detect the FIFO_H2U full event. When the FIFO_H2U is full, the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. Similarly, for the transmit FIFO_U2H buffer, the LSB in the FIFO level threshold comparison is always 0 (FIFO_CFG.U2H_LEVEL_SET[3:0], 0). This configuration is designed to alert the user when FIFO_U2H is getting nearly empty so as to enable a timely data enqueue, and prevent FIFO_U2H from becoming empty prematurely and causing a gap error on the HART bus. For this reason, the FIFO_U2H_LEVEL_FLAG is also a less-than (<) comparison with the FIFO_CFG.U2H_LEVEL_SET. For example, if FIFO_CFG.U2H_LEVEL_SET = 4’b1000, then when the level of the FIFO_U2H < 5’b10000, the FIFO_U2H_LEVEL_FLAG is set. Setting FIFO_CFG.U2H_LEVEL_SET = 4’b0000 (default) effectively disables this flag. Use FIFO_U2H_EMPTY_ FLAG to detect the FIFO_U2H empty event. To avoid buffer overflow, monitor the level of FIFO_U2H by watching for a buffer-full or buffer-threshold event. If the FIFO_U2H_LEVEL_FLAG bit in the MODEM_STATUS_MASK register is set to 0, the IRQ pin toggles when the threshold is exceeded. Similarly, an alarm can be triggered based on the FIFO_U2H_FULL_FLAG bit in the MODEM_STATUS register. When the FIFO_U2H is full the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. HART Modulator The HART modulator implements a look-up table (LUT) containing 128, 8-bit, signed values that represent a single-phase, continuous sinusoidal cycle. A counter is implemented that incrementally loads the table values to a DAC at a clock frequency determined by the binary value of the input data. The DAC clock frequency is determined by the logical value of the data bit being transmitted. A logic 1 transmits at the internal clock frequency of 32 (default) steps times 1200 Hz. A logic 0 transmits at the internal clock frequency of 32 (default) steps times 2200 Hz. All frequencies are derived from 1.2288 MHz. This process creates the mark and space analog output signals used to represent HART data. The default mode uses 32 sinusoidal codes per period from the LUT for power savings. To generate a 128-step-per-period sinusoidal signal set MODEM_CFG.TxRES = 1. shows the HART modulator architecture. HART Modulator Architecture HART Demodulator The HART demodulator converts the HART FSK input signals applied at the HART input pins (RX_IN and RX_INF) to binary data that are enqueued into the receive FIFO (FIFO_H2U). Data from the FIFO_H2U can then be dequeued by the host controller using the SPI or output on UARTOUT. shows the HART demodulator architecture. The AFEx82H1 supports two different input bandpass filter modes: internal and external. In internal filter mode, the HART input signal is connected to the RX_IN pin through the high-pass filter capacitor. In this mode, the low-pass filter capacitor is connected to the RX_INF pin. In external filter mode, the band-pass filter is implemented with external components for better flexibility, and the resulting band-pass-filtered signal is connected to the RX_INF pin. In this mode, float the RX_IN pin. Use the MODEM_CFG.RX_EXFILT_EN bit to select between these two modes, depending on the external band-pass filter implementation and HART input signal connection. The input band-pass filter (either fully external or partially internal with external capacitors and internal resistors) is followed by the internal second-order high-pass filter and the internal second-order low-pass filter. To enable the second-order low-pass filter, use the MODEM_CFG.RX_HORD_EN bit. HART Demodulator Architecture The HART demodulator asserts a carrier detect (CD) signal, when a carrier-above-threshold level is detected. Hysteresis is implemented with the carrier-detect feature to prevent erroneous carrier-detection signals. The glitch-free CD signal is available internally to the arbiter and externally to the system controller on the CD pin. HART Modem Modes The HART modulator‑demodulator operates in either half‑duplex or full‑duplex mode. Half-Duplex Mode Half-duplex mode is the main functional mode of operation for the AFEx82H1, in conjunction with the half‑duplex HART protocol. In half-duplex mode, either the modulator or demodulator is active at any given instant, but never simultaneously enabled. By default, the demodulator is active and the modulator is inactive. When using half-duplex mode, the modem arbitrates when modulator and demodulator are active. For more details, see . Full-Duplex Mode In full‑duplex mode, the modulator and demodulator are simultaneously enabled. This configuration allows a self‑test feature to verify functionality of the transmit and receive signal chains to improve system diagnostics. There are internal and external full-duplex modes. In internal full-duplex mode, the MOD_OUT pin is internally shorted to the RX_INF pin. Set MODEM_CFG.DUPLEX = 1 to enable an internal connection between the HART transmitter and receiver to verify communication. In external full-duplex mode, the HART modulator and demodulator are enabled, but the MOD_OUT pin is not internally shorted to the RX_IN or RX_INF pins. To enable the external full‑duplex mode, short MOD_OUT to RX_IN or RX_INF pins externally, and set MODEM_CFG.DUPLEX_EXT = 1. HART Modulation and Demodulation Arbitration In half‑duplex HART-protocol mode, the device arbitrates when the modulator and demodulator are active, based on activity on the HART bus. The system controller has various means of monitoring and interacting with the AFEx82H1. For the methods used in SPI mode, see . For the reporting method used in UART mode, see . In the default idle state, the RTS pin is high (inactive), and the CD pin is low. The demodulator is active and the modulator is inactive. HART Receive Mode When a carrier is detected, the CD pin toggles high, and data bytes received by the modem are automatically enqueued into FIFO_H2U. This mode is the highest priority, and the device continues to remain in this mode as long as a valid carrier is present. The system controller must timely dequeue the data from the FIFO_H2U as long as CD remains high and the demodulator enqueues new data into FIFO_H2U. CD is deasserted when the level of the incoming carrier is reduced to less than the HART specification. For receive operation timing details, see . HART Transmit Mode To transmit the HART data, issue a request to send (RTS) either by toggling the RTS pin low or asserting MODEM_CFG.RTS, depending on the selected communication setup. When the HART bus is available for transmission and no carrier is detected, the device deasserts the CD pin, disables the demodulator, asserts the CTS response by setting MODEM_STATUS.CTS_ASSERT = 1, and begins modulating the carrier. If the CD pin is used, wait for the CD pin to be deasserted. Otherwise, unmask CTS_ASSERT and set up the appropriate IRQs for the FIFO_U2H levels and CTS flags to enable the system controller to receive an IRQ when CTS is asserted. See also . When the CD pin and IRQ are not used, poll the MODEM_STATUS register regularly to detect when the CTS response is asserted. As long as the CD pin is asserted, the demodulator remains active and the RTS request is held pending by the arbiter. Any HART transmit data bytes received by the AFEx82H1 are enqueued into FIFO_U2H, but not transmitted immediately. The system controller must monitor the FIFO_U2H level to avoid buffer overflow in this condition. When the CTS response is asserted, the data enqueued into FIFO_U2H are dequeued and transmitted onto the MOD_OUT pin. If no data are enqueued into FIFO_U2H, the modulator starts transmitting the mark signal. The beginning of the bit stream must meet the minimum bit times requirement to make sure there is enough time for successful detection of the mark-to-space transition on the receiving side; see also . The system controller is then required to maintain adequate an FIFO_U2H buffer level to avoid gap errors and deassert the RTS at the end of bit stream with the correct timing delays; see also . HART Modulator Timing and Preamble Requirements The HART modulator starts modulating the carrier as soon as the CTS response is asserted. If data are enqueued into FIFO_U2H before the CTS is asserted, make sure to enqueue the required preamble bytes at the beginning of the data packet in accordance with . The first byte is used by the HART recipient receiver to recognize the carrier and properly detect the mark-to-space transition of the start bit in the second character. Alternatively, wait for CTS_ASSERT, and give an appropriate delay while the modulator is transmitting the mark signal. Then enqueue the preamble bytes followed by the data bytes into FIFO_U2H. Monitor the level of FIFO_U2H and timely enqueue the new data to avoid transmission gap errors. Carrier Detect and Preamble HART REQUIREMENT FIFO_U2H STATE AFEx82H1 BEHAVIOR RECOMMENDED USE CASE Transmit at least 6 bit times of HART signal of specified amplitude for the carrier to be detected by the receiver. FIFO_U2H is empty. HART modulator starts sending mark FSK signal as soon as CTS is asserted. Wait at least 6 bit times from CTS assert before transmitting first preamble byte. Calculate the time to enqueue the data into FIFO_U2H based on the interface mode used. FIFO_U2H is preloaded with data. HART modulator starts sending FIFO_U2H data as soon as CTS is asserted. Preload FIFO_U2H with one additional preamble byte. Depending on the interface mode, there is a latency from the UARTIN or CS pin to the MOD_OUT pin as a result of using FIFO_U2H in the data path. In the SPI plus UART and UBM modes, a delay of approximately 1.5 bit times (1.5 × tBAUDUART) occurs from the stop bit on the UARTIN pin until the data are enqueued into FIFO_U2H as a result of data decoding and synchronization. shows this timing. HART Transmit Start Timing Diagram (UART Mode) In SPI only mode, the HART transmit data are enqueued into FIFO_U2H using FIFO_U2H_WR register. Therefore, in this mode, take the standard SPI timing into consideration while calculating the latency of the HART transmit data from the CS pin to the MOD_OUT pin. shows the HART transmit start timing for SPI mode. HART Transmit Start Timing Diagram (SPI Mode) The HART character contains 11 bits; therefore, a delay of approximately 11 bit times (11 × tBAUDHART) occurs from the moment the data are dequeued from FIFO_U2H until the data are fully transmitted on the MOD_OUT pin (see ). Additional delay is accumulated when there is a frequency mismatch between the incoming UART_IN data and the HART data transmitted on MOD_OUT. If the UART_IN data frequency is 2% greater compared to the MOD_OUT data frequency, a delay of approximately 1 bit time is accumulated every five HART characters. Add a gap of at least 1 bit time between every five HART characters to account for this latency. Keep the request to send (RTS) asserted until the data are fully transmitted on MOD_OUT. HART Transmit End Timing Diagram (UBM, UART Plus SPI Modes) HART Demodulator Timing and Preamble Requirements The RX_IN and RX_INF pins are continuously monitored by the HART demodulator when not transmitting. AFEx82H1 requires at least 3 mark bits (3 × tBAUDHART) of 1200 Hz for carrier detection. For UART-based communication setup, the HART data are automatically dequeued from FIFO_H2U and transmitted on the UARTOUT pin as UART characters. A delay of approximately 1.5 bit times (1.5 × tBAUDHART) occurs as a result of data decoding and synchronization from the end of the character on RX_IN or RX_INF pin until the data are enqueued into FIFO_H2U. Thus, when CD deasserts, there is typically still one UART character pending transfer to the system controller on UARTOUT (see ). FIFO latency is as low as a few microseconds when using the SPI to dequeue the data from FIFO_H2U by reading FIFO_H2U_RD register. and show the timing diagrams for the start and end of the HART receive character, respectively. HART Receive Start Timing Diagram (SPI and UART Modes) HART Receive End Timing Diagram (UART Mode) IRQ Configuration for HART Communication To enable robust and error-free communicate on the HART bus, the events listed in #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/TABLE_BCL_BCQ_PQB must be detected from the AFEx82H1 by the system controller in a timely manner. If the IRQ signal is not directly connected to the system controller, poll the corresponding status flags. In UART mode, the automatic dequeue of FIFO_H2U simplifies event management significantly, and not all events must be translated to IRQs. When using the HART modem with the IRQ, the IRQ features help control communication in both directions. Enable IRQ functionality by following these steps: Configure the IRQ to be either edge or level sensitive using CONFIG.IRQ_LVL. See also . Configure the IRQ polarity with CONFIG.IRQ_POL, as needed per the respective system. See also . For SPI only mode, set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the UARTOUT pin. Also, set CONFIG.UART_DIS = 1 to disable all UART functionality. For UBM, use one of the two following methods: Set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the SDO pin, or Set CONFIG.UBM_IRQ_EN = 1 to enable interrupts being sent UARTOUT using UBM. After IRQ functionality is enabled, unmask all the required interrupt signals in the MODEM_STATUS_MASK register (set each bit = 0). IRQ Sources and Uses AFEx82H1HART STATE EVENT MODEM_STATUS FLAG ASSERTION METHOD #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWB ACTION Receive RTS deasserted CTS_DEASSERT Toggle RTS pin high or set MODEM_CFG.RTS = 0. Demodulator enabled and ready to receive HART data. Carrier detect asserted CD_ASSERT Demodulator detects the HART carrier signal of valid amplitude. Expect to receive HART data. Set desired FIFO_H2U level trigger threshold. FIFO_H2U level threshold trigger FIFO_H2U_LEVEL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. Dequeue data from FIFO_H2U when level exceeds the set threshold. Prevent FIFO_H2U from being full to avoid the loss of incoming data. FIFO_H2U full FIFO_H2U_FULL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. System controller has not dequeued FIFO_H2U. Critical flag. Dequeue FIFO_H2U immediately to avoid the loss of incoming data. Carrier detect deasserted CD_DEASSERT Demodulator stops detecting the HART carrier signal of valid amplitude. Dequeue remaining data from FIFO_H2U. Monitor the empty flag to make sure that all data have been received. FIFO_H2U empty FIFO_H2U_EMPTY_FLAG Dequeue of FIFO_H2U by system controller. If using UART, wait to make sure the last character is received on UARTOUT. Transmit RTS asserted NA Toggle RTS pin low or write set MODEM_CFG.RTS = 1. Wait for clear-to-send confirmation flag. Clear to send (CTS) CTS_ASSERT RTS asserted and CD deasserted. Modulator enabled. Device starts modulating the carrier on MOD_OUT. Set desired FIFO_U2H level trigger threshold. Enqueue data into FIFO_U2H. Modulator automatically dequeues FIFO_U2H and transmits the HART data. FIFO_U2H level threshold trigger FIFO_U2H_LEVEL_FLAG Automatic dequeue of FIFO_U2H by HART modulator. Enqueue new data into FIFO_U2H when the level drops below the set threshold. Prevent FIFO_U2H from being empty to avoid a gap in transmission. FIFO_U2H full FIFO_U2H_FULL_FLAG System controller enqueue of the new data into FIFO_U2H. Critical flag.Stop enqueue of data into FIFO_U2H immediately to avoid loss of HART data. FIFO_U2H empty FIFO_U2H_EMPTY_FLAG Automatic dequeue of FIFO_U2H by HART modulator. System controller has not enqueued new data into FIFO_U2H. Critical flag in the middle of the data packet.Enqueue new data into FIFO_U2H immediately to avoid a gap in transmission. When the last character is dequeued from FIFO_U2H, wait until the character is fully transmitted on MOD_OUT before deasserting RTS. For CD, RTS, ALARM, and IRQ connection choices, see . HART Communication Using the SPI HART bus communication activity is reported to the host controller through the IRQ signal routed to the UARTOUT pin and MODEM_STATUS register. Read the MODEM_STATUS register to determine the source of the IRQ when an IRQ is received. If the UARTOUT pin is not connected, poll the status registers regularly through the SPI. To transmit data, set up the desired FIFO_U2H level thresholds using FIFO_CFG.U2H_LEVEL_SET. Assert the RTS. After CTS_ASSERT is set, begin to fill FIFO_U2H. Enqueue enough data into FIFO_U2H to fill the FIFO above the set threshold level. The HART modulator automatically dequeues the data from FIFO_U2H and transmits the data on MOD_OUT. When FIFO_U2H level drops below the set threshold, an IRQ triggers, indicating that new data bytes can be enqueued without losing any data. After the last set of data have been enqueued into FIFO_U2H, an IRQ event triggered by the level flag can be ignored. Wait for the IRQ event triggered by FIFO_U2H_EMPTY_FLAG. Deassert the RTS after required delay; see also . When the RTS is deasserted, the CTS_DEASSERT bit is set. CTS_DEASSERT is an informational bit. To receive data, set up an IRQ event based on CD_ASSERT to know when the carrier is detected and the new data bytes are expected. Also, set up the additional IRQ events to trigger each time FIFO_H2U_LEVEL_FLAG is set. Select the desired level of FIFO_H2U. Dequeue the data from FIFO_H2U every time the level exceeds the set threshold. Also, set up IRQ event trigger based on CD_DEASSERT to know when all the data have been received. At this point, monitor FIFO_H2U.EMPTY_FLAG when dequeuing each character to know when FIFO_H2U is empty and all the data bytes have been dequeued and transmitted to the microcontroller. Alternatively, the CD pin can be directly connected to the microcontroller to monitor the status of the HART bus. In this configuration, mask CD_ASSERT flag by setting MODEM_STATUS_MASK.CD_ASSERT bit = 1 to prevent CD_ASSERT from generating an IRQ event. HART Communication Using UART In SPI plus UART mode, the UART data are transmitted and received at 1200 baud, which is matched to the HART FSK input and output signals. Both SDO and UARTOUT pins are used; therefore, the IRQ functionality is not available in SPI plus UART mode. FIFO_H2U level monitoring is not required because any HART data received by the demodulator and enqueued into FIFO_H2U are automatically dequeued and transmitted on UARTOUT. FIFO_U2H level monitoring is also not required if HART bus communication activity is interfaced to the host controller through the CD and RTS pins. The host controller can properly time the RTS pin to transmit the HART data when no carrier is detected on the bus. If the CD and RTS pins are not used in SPI plus UART mode, the host controller can periodically poll the MODEM_STATUS register through the SPI to detect when the carrier is not present on the HART bus, and assert the request to send by setting MODEM_CFG.RTS bit = 1. In UBM, the UART data are transmitted and received at 9600 baud. The HART data characters are interleaved with break commands for register map access or interrupt reporting; see also . Similar to SPI plus UART mode, monitoring of FIFO_H2U and FIFO_U2H levels is not required. The CD and RTS pins are available to interface the HART bus activity with the microcontroller. IRQ functionality is also available on the SDO pin. If the SDO pin is connected to the microcontroller, the IRQ event based on CD_ASSERT can be set to report when the carrier is detected. In this case, CD pin connection to the microcontroller is not required. Similarly, RTS pin connection is not required if MODEM_CFG.RTS is used to issue a request to send. The SDO pin connection to the microcontroller is also not required if the microcontroller can periodically poll the MODEM_STATUS register using break commands, and monitor all the required flags. Memory Built-In Self-Test (MBIST) Memory built-in self-test (MBIST) verifies the validity of the static random-access memory (SRAM) used for the FIFO buffers. When initiated, the MBIST takes control of the SRAM module until completion. Disable HART communication while the MBIST is running. Communication with the FIFO buffers during the MBIST produces unreliable results. Two status bits, GEN_STATUS.MBIST_DONE and GEN_STATUS.MBIST_FAIL, can be monitored for completion or failure, or used to create IRQ events. Do not try to read back the GEN_STATUS register while the MBIST is running. The MBIST control logic generates narrow pulses for the MBIST_DONE and MBIST_FAIL status flags. The status flags can be missed if these pulses occur during the readback of the GEN_STATUS register. To avoid missing the MBIST_DONE flag, mask all the status bits except GEN_STATUS_MASK.MBIST_DONE and then either: monitor for an IRQ event, or periodically send a NOP and check the GEN_IRQ status bit. Wait until MBIST_DONE is reported, verify the status of the MBIST_FAIL flag, and then resume normal operation. Internal Reference The AFEx82H1 family of devices includes a 1.25-V precision band-gap reference. The internal reference is externally available at the VREFIO pin and sources up to 2.5 mA. For noise filtering, use a 100-nF capacitor between the reference output and GND. The internal reference circuit is enabled or disabled by using the REF_EN pin. A logic high on this pin enables the internal reference, and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal reference, and the device expects to have 1.25 V from external VREF at the VREFIO pin. An invalid reference voltage asserts an alarm condition. The DAC response depends on the VREF_FLT setting in the ALARM_ACT register (10h). Integrated Precision Oscillator The internal time base of the device is provided by an internal oscillator that is trimmed to less than 0.5% tolerance at room temperature. The precision oscillator is the timing source for ADC conversions. At power up, the internal oscillator and ADC take roughly 300 µs to reach < 1% error stability. After the clock stabilizes, the ADC data output is accurate to the electrical specifications provided in . Precision Oscillator Diagnostics The AFEx82H1 features two methods to continuously detect the functional status of the internal precision oscillator. The first method requires a connection from the AFEx82H1 to the system controller. To use the first method, program the AFEx82H1 to output a subdivided internal oscillator clock signal on the CLK_OUT pin. Write to the CONFIG.CLKO register field (see ) to enable the output with the chosen divider or to disable the output. The output digital signal is compliant to the . The CLK_OUT pin is also a shared GPIO pin. For details on connecting CLK_OUT and CLK_OUT interoperability as a GPIO pin , see . The second method does not require a connection from the AFEx82H1 and is a polled-communication-based method to determine the functionality of the internal oscillator using SPI communication. See and for SPI communication details and SDO status bits details, respectively. The OSC_DIV_2 bit reports the logical value of a subdivided internal oscillator signal (divided by 2) sampled at the CS falling edge. Use an appropriate SCLK frequency and interval between SPI frames to capture bit changes from frame to frame as a method of verifying the continued proper operation of the clock. Similar status reports of the logical value of a subdivided internal oscillator signal (divided by 1024) are available in UBM as the OSC_DIV_1024 bit. For details on UBM frames and timing, see . One-Time Programmable (OTP) Memory One-time programmable (OTP) memory in the device is used to store the device trim settings and is not accessible to users. The OTP memory data are loaded to the memory (OTP shadow load) at power up. The OTP memory CRC is performed to verify the correct data are loaded. The TRIGGER.SHADOWLOAD bit is available to initiate a reload of the OTP memory data if a CRC error is detected. The SPECIAL_CFG.OTP_LOAD_SW_RST bit controls whether the OTP memory data are reloaded with a software reset. GPIO AFEx82H1 feature multiple GPIO pins, each independently configurable in either input only or output only or input-ouput mode through GPIO_CFG and GPIO registers. Select either push-pull or pseudo open drain sub modes supported when the GPIO is in output mode. No dedicated GPIO pins are present since the same pins are also configurable for communication interfaces. Based on the selection of the interface protocol and how many pins are used for communication purposes, the AFEx82H1 have up to four available GPIOs. Refer to for detailed diagrams of available GPIOs in each communication mode. If a GPIO pin is unused or undriven, the pin must be tied resistively to either IOVDD or GND according to the connection diagrams in . Unconnected floating input pins lead to unknown states for the communication interfaces and varying supply currents for the AFEx82H1. When functioning as an output, each GPIO pin is capable of sourcing and sinking current and when functioning as an input the register address 0x1C reflects the digital state of the GPIO pins (for details of source and sink capabilities and input thresholds, see ). The minimum pulse width for transition detection is tPULSE_GPIO. When a state transition occurs on a GPIO input, the new state must be held for a minimum of tPULSE_GPIO for detection by the AFEx82H1. Timer The AFEx82H1 have an integrated timer for generating accurate time delays, pulse width modulation or oscillation. The devices have the ability to have timing parameters from the microseconds range to hours. The timer is brought out on the CLK_OUT pin by setting CONFIG.CLKO = Fh. The timer is controlled with three registers; TIMER_CFG_0, TIMER_CFG_1, and TIMER_CFG_2. In the first of the three registers, TIMER_CFG_0.ENABLE turns the timer function on and off. If the timer is off, then the output defaults to 0. TIMER_CFG_0.INVERT inverts the output of the timer. If the INVERT bit is set, the output defaults to 1. TIMER_CFG_0.CLK_SEL selects the clock frequency according to #GUID-D4148F6E-8502-48B6-8064-9DF2FCCD8009/TABLE_ADN_CZD_PVB. If 2'b00 is selected, and no clock is applied, then the timer pauses if the timer has previously been enabled and counting. Timer Select Range CLK_SEL Clock Frequency Resolution Range 00 No clock - - 01 1.2288 MHz 814 ns 53.3 ms 10 1.200 kHz 833 μs 54.6 s 11 1.171 Hz 853 ms 55,923 s The second timer register, TIMER_CFG_1.PERIOD sets the period of the timer. The period of the timer is PERIOD + 1 cycles of the clock period. The last timer register, TIMER_CFG_2.SET_TIME determines when the timer output goes to 1 (INVERT = 0). This effectively defines the duty cycle of the timer. The duty cycle can be calculated as (PERIOD – SET_TIME) × clock period. Unique Chip Identifier (ID) AFEx82H1 include two read only registers: CHIP_ID_MSB (1Ah) and CHIP_ID_LSB (19h) where unique chip ID is stored. The 16-bit CHIP_ID_MSB register stores the encoded lot identification number while the CHIP_ID_LSB register stores the unique part number within each lot. Scratch Pad Register AFEx82H1 feature a 16-bit Scratch Pad register to enable interface debug and verification without affecting the part functionality. This register is located at the address 18h. The readback value of the Scratch Pad register is the inverted code of the value stored in the register (for example, writing 0xAAAA results in 0x5555 while reading back ). Feature Description Digital-to-Analog Converter (DAC) Overview The AFEx82H1 feature a 16-bit (AFE882H1) or 14‑bit (AFE782H1) string DAC followed by an output voltage buffer. Using an external circuit, the device output voltage can be translated to different output voltages and output currents for use in 3‑wire or 4-wire sensor transmitters or analog output modules. The DAC is configured to support a 0‑V to 2.5‑V range of operation. The alarm function is triggered when PVDD exceeds the valid configuration range of 2.7 V to 5.5 V; see also . DAC Resistor String shows that the resistor string structure consists of a series of resistors, each of value R. The code loaded to the DAC determines the node on the string at which the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. The resistor string architecture has inherent monotonicity, voltage output, and low glitch. DAC Resistor String DAC Buffer Amplifier The VOUT output pin is driven by the DAC output buffer amplifier. The output amplifier default settings are designed to drive capacitive loads as high as 100 pF without oscillation. The output buffer is able to source and sink 1 mA. The device implements short-circuit protection for momentary output shorts to ground and VDD supply. The source and sink short-circuit current thresholds are set to 5 mA. DAC Transfer Function The following equation describes the DAC transfer function, which is the relationship between internal signal DAC_CODE and output voltage VOUT: V O U T = D A C _ C O D E 2 N × F S R where DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N – 1. N = DAC_CODE resolution in bits (16 for the AFE882H1 and 14 for the AFE782H1). FSR = VOUT full-scale range = 2.5 V. DAC Gain and Offset Calibration The AFEx82H1 provide DAC gain and offset calibration capability to correct for end-point errors present in the system. Implement the gain and offset calibration using two registers, DAC_GAIN.GAIN and DAC_OFFSET.OFFSET. Update DAC_DATA register after gain or offset codes are changed for the new values to take effect. The DAC_GAIN can be programmed from 0.5 to 1.499985 using . D A C _ G A I N = 1 2 + G A I N 2 N where N = DAC_GAIN resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. GAIN is the decimal value of the DAC_GAIN register setting. GAIN data are left justified; the last two LSBs in the DAC_GAIN register are ignored for the AFE782H1. The example DAC_GAIN settings for the AFE882H1 are shown in . DAC_GAIN Setting vs GAIN Code DAC_GAIN GAIN (HEX) 0.5 0x0000 1.0 0x8000 1.499985 0xFFFF The DAC_OFFSET is stored in the DAC_OFFSET register using 2's-complement encoding. The DAC_OFFSET value can be programmed from –2(N–1) to 2(N–1) – 1 using . D A C _ O F F S E T = - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i where N = DAC_OFFSET resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. OFFSETMSB = MSB bit of the DAC_OFFSET register. OFFSET i = The rest of the bits of the DAC_OFFSET register. i = Position of the bit in the DAC_OFFSET register. OFFSET data are left justified; the last two LSBs in the DAC_OFFSET register are ignored for the device. The most significant bit determines the sign of the number and is called the sign bit. The sign bit has the weight of –2(N–1) as shown in . The example DAC_OFFSET settings for the AFE882H1 are shown in . DAC_OFFSET Setting vs OFFSET Code DAC_OFFSET OFFSET (HEX) 32767 0x7FFF 1 0x0001 0 0x0000 –1 0xFFFF –2 0xFFFE –32768 0x8000 The following transfer function is applied to the DAC_DATA.DATA based on the DAC_GAIN and DAC_OFFSET values: D A C _ C O D E = ( D A T A × D A C _ G A I N ) + D A C _ O F F S E T where DAC_CODE is the internal signal applied to the DAC. DATA is the decimal value of the DAC_DATA register. DAC_GAIN and DAC_OFFSET are the user calibration settings. DATA data are left justified; the last two LSBs in the DAC_DATA register are ignored for the AFE782H1. Substituting DAC_GAIN and DAC_OFFSET in with and results in: D A C _ C O D E = ( D A T A × 1 2 + G A I N 2 N ) - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i The multiplier is implemented using truncation instead of rounding. This truncation can cause a difference of one LSB if rounding is expected. shows the DAC calibration path. DAC Calibration Path Programmable Slew Rate The slew rate feature controls the rate at which the output voltage or current changes. This feature is disabled by default and is enabled by writing a logic 1 to the DAC_CFG.SR_EN bit. With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load. With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by DAC_CFG.SR_STEP[2:0] and DAC_CFG.SR_CLK[2:0]. SR_CLK defines the rate at which the digital slew updates. SR_STEP defines the amount by which the output value changes at each update. The register descriptions show different settings for SR_STEP and SR_CLK. The time required for the output to slew is expressed as : S l e w   T i m e   =   D e l t a   C o d e   C h a n g e S l e w   S t e p   ×   S l e w   C l o c k   R a t e where Slew Time is expressed in seconds Slew Step is controlled by DAC_CFG.SR_STEP Slew Clock Rate is controlled by DAC_CFG.SR_CLK When the slew-rate control feature is enabled, the output changes at the programmed slew rate. This configuration results in a staircase formation at the output. If the clear code is asserted (see ), the output slews to the DAC_CLR_CODE value at the programmed slew rate. When new DAC data are written, the output starts slewing to the new value at the slew rate determined by the current DAC code and the new DAC data. Two slew-rate control modes are available: linear (default) and sinusoidal. and show the typical rising and falling DAC output waveforms, respectively. Linear Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Linear Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt Sinusoidal mode enables fast DAC settling while improving analog rate of change characteristics. Sinusoidal mode is selected by the DAC_CFG.SR_MODE bit. and show the typical rising and falling DAC output waveforms with sinusoidal slew-rate control, respectively. Sinusoidal Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Sinusoidal Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt If the slew-rate feature is disabled while the DAC is executing the slew-rate command, the slew-rate operation is aborted, and the DAC output goes to the target code. DAC Register Structure and CLEAR State The AFE882H1 DAC has a 16-bit voltage output, and the AFE782H1 DAC has a 14-bit voltage output. The output range is 0 V to 2.5 V. The AFEx82H1 provide the option to quickly set the DAC output to the value set in the DAC_CLR_CODE register without writing to the DAC_DATA register, referred to as the CLEAR state. For register details, see . Transitioning from the DAC_DATA to the DAC_CLR_CODE is synchronous to the clock. If slew mode is enabled, the output slews during the transition. shows the full AFEx82H1 DAC_DATA signal path. The devices synchronize the DAC_DATA code to the internal clock, causing up to 2.5 internal clock cycles of latency (2 μs) with respect to the rising edge of CS or the end of a UBM command. Update DAC_GAIN and DAC_OFFSET values when DAC_CFG.SR_EN = 0 to avoid an IRQ pulse generated by SR_BUSY. Set the DAC to CLEAR state either by: Setting DAC_CFG.CLR. Configuring the DAC to transition to the CLEAR state in response to an alarm condition. Using the SDI pin in UBM as the CLEAR state input pin. Method 1 is a direct command to the AFEx82H1 to set the DAC to CLEAR state. Set the DAC_CFG.CLR bit to 1h to set the DAC to CLEAR state. Method 2 is controlled by settings of ALARM_ACT register. For details of conditions and other masks required to use this method, see and . Method 3 supports setting the DAC to CLEAR state without writing to the AFEx82H1. This pin-based DAC CLEAR state function is available only in UBM on the SDI pin. For details of connection options based on communication modes and pins used in each mode, see . Set the appropriate pin high to drive the DAC to CLEAR state. DAC Data Path Digital-to-Analog Converter (DAC) Overview The AFEx82H1 feature a 16-bit (AFE882H1) or 14‑bit (AFE782H1) string DAC followed by an output voltage buffer. Using an external circuit, the device output voltage can be translated to different output voltages and output currents for use in 3‑wire or 4-wire sensor transmitters or analog output modules. The DAC is configured to support a 0‑V to 2.5‑V range of operation. The alarm function is triggered when PVDD exceeds the valid configuration range of 2.7 V to 5.5 V; see also . The AFEx82H1 feature a 16-bit (AFE882H1) or 14‑bit (AFE782H1) string DAC followed by an output voltage buffer. Using an external circuit, the device output voltage can be translated to different output voltages and output currents for use in 3‑wire or 4-wire sensor transmitters or analog output modules. The DAC is configured to support a 0‑V to 2.5‑V range of operation. The alarm function is triggered when PVDD exceeds the valid configuration range of 2.7 V to 5.5 V; see also . The AFEx82H1 feature a 16-bit (AFE882H1) or 14‑bit (AFE782H1) string DAC followed by an output voltage buffer. Using an external circuit, the device output voltage can be translated to different output voltages and output currents for use in 3‑wire or 4-wire sensor transmitters or analog output modules. The DAC is configured to support a 0‑V to 2.5‑V range of operation. The alarm function is triggered when PVDD exceeds the valid configuration range of 2.7 V to 5.5 V; see also . AFEx82H1AFE882H1AFE782H1 DAC Resistor String shows that the resistor string structure consists of a series of resistors, each of value R. The code loaded to the DAC determines the node on the string at which the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. The resistor string architecture has inherent monotonicity, voltage output, and low glitch. DAC Resistor String DAC Resistor String shows that the resistor string structure consists of a series of resistors, each of value R. The code loaded to the DAC determines the node on the string at which the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. The resistor string architecture has inherent monotonicity, voltage output, and low glitch. DAC Resistor String shows that the resistor string structure consists of a series of resistors, each of value R. The code loaded to the DAC determines the node on the string at which the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. The resistor string architecture has inherent monotonicity, voltage output, and low glitch. DAC Resistor String shows that the resistor string structure consists of a series of resistors, each of value R. The code loaded to the DAC determines the node on the string at which the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. The resistor string architecture has inherent monotonicity, voltage output, and low glitch. DAC Resistor String DAC Resistor String DAC Buffer Amplifier The VOUT output pin is driven by the DAC output buffer amplifier. The output amplifier default settings are designed to drive capacitive loads as high as 100 pF without oscillation. The output buffer is able to source and sink 1 mA. The device implements short-circuit protection for momentary output shorts to ground and VDD supply. The source and sink short-circuit current thresholds are set to 5 mA. DAC Buffer Amplifier The VOUT output pin is driven by the DAC output buffer amplifier. The output amplifier default settings are designed to drive capacitive loads as high as 100 pF without oscillation. The output buffer is able to source and sink 1 mA. The device implements short-circuit protection for momentary output shorts to ground and VDD supply. The source and sink short-circuit current thresholds are set to 5 mA. The VOUT output pin is driven by the DAC output buffer amplifier. The output amplifier default settings are designed to drive capacitive loads as high as 100 pF without oscillation. The output buffer is able to source and sink 1 mA. The device implements short-circuit protection for momentary output shorts to ground and VDD supply. The source and sink short-circuit current thresholds are set to 5 mA. The VOUT output pin is driven by the DAC output buffer amplifier. The output amplifier default settings are designed to drive capacitive loads as high as 100 pF without oscillation. The output buffer is able to source and sink 1 mA. The device implements short-circuit protection for momentary output shorts to ground and VDD supply. The source and sink short-circuit current thresholds are set to 5 mA. DAC Transfer Function The following equation describes the DAC transfer function, which is the relationship between internal signal DAC_CODE and output voltage VOUT: V O U T = D A C _ C O D E 2 N × F S R where DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N – 1. N = DAC_CODE resolution in bits (16 for the AFE882H1 and 14 for the AFE782H1). FSR = VOUT full-scale range = 2.5 V. DAC Transfer Function The following equation describes the DAC transfer function, which is the relationship between internal signal DAC_CODE and output voltage VOUT: V O U T = D A C _ C O D E 2 N × F S R where DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N – 1. N = DAC_CODE resolution in bits (16 for the AFE882H1 and 14 for the AFE782H1). FSR = VOUT full-scale range = 2.5 V. The following equation describes the DAC transfer function, which is the relationship between internal signal DAC_CODE and output voltage VOUT: V O U T = D A C _ C O D E 2 N × F S R where DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N – 1. N = DAC_CODE resolution in bits (16 for the AFE882H1 and 14 for the AFE782H1). FSR = VOUT full-scale range = 2.5 V. The following equation describes the DAC transfer function, which is the relationship between internal signal DAC_CODE and output voltage VOUT: V O U T = D A C _ C O D E 2 N × F S R V O U T = D A C _ C O D E 2 N × F S R V O U T = D A C _ C O D E 2 N × F S R VOUT= D A C _ C O D E 2 N D A C _ C O D E DAC_CODE 2 N 2 N 2 2 N N×FSRwhere DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N – 1. N = DAC_CODE resolution in bits (16 for the AFE882H1 and 14 for the AFE782H1). FSR = VOUT full-scale range = 2.5 V. DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N – 1. N = DAC_CODE resolution in bits (16 for the AFE882H1 and 14 for the AFE782H1). FSR = VOUT full-scale range = 2.5 V. DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N – 1.NN = DAC_CODE resolution in bits (16 for the AFE882H1 and 14 for the AFE782H1).AFE882H1AFE782H1FSR = VOUT full-scale range = 2.5 V. DAC Gain and Offset Calibration The AFEx82H1 provide DAC gain and offset calibration capability to correct for end-point errors present in the system. Implement the gain and offset calibration using two registers, DAC_GAIN.GAIN and DAC_OFFSET.OFFSET. Update DAC_DATA register after gain or offset codes are changed for the new values to take effect. The DAC_GAIN can be programmed from 0.5 to 1.499985 using . D A C _ G A I N = 1 2 + G A I N 2 N where N = DAC_GAIN resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. GAIN is the decimal value of the DAC_GAIN register setting. GAIN data are left justified; the last two LSBs in the DAC_GAIN register are ignored for the AFE782H1. The example DAC_GAIN settings for the AFE882H1 are shown in . DAC_GAIN Setting vs GAIN Code DAC_GAIN GAIN (HEX) 0.5 0x0000 1.0 0x8000 1.499985 0xFFFF The DAC_OFFSET is stored in the DAC_OFFSET register using 2's-complement encoding. The DAC_OFFSET value can be programmed from –2(N–1) to 2(N–1) – 1 using . D A C _ O F F S E T = - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i where N = DAC_OFFSET resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. OFFSETMSB = MSB bit of the DAC_OFFSET register. OFFSET i = The rest of the bits of the DAC_OFFSET register. i = Position of the bit in the DAC_OFFSET register. OFFSET data are left justified; the last two LSBs in the DAC_OFFSET register are ignored for the device. The most significant bit determines the sign of the number and is called the sign bit. The sign bit has the weight of –2(N–1) as shown in . The example DAC_OFFSET settings for the AFE882H1 are shown in . DAC_OFFSET Setting vs OFFSET Code DAC_OFFSET OFFSET (HEX) 32767 0x7FFF 1 0x0001 0 0x0000 –1 0xFFFF –2 0xFFFE –32768 0x8000 The following transfer function is applied to the DAC_DATA.DATA based on the DAC_GAIN and DAC_OFFSET values: D A C _ C O D E = ( D A T A × D A C _ G A I N ) + D A C _ O F F S E T where DAC_CODE is the internal signal applied to the DAC. DATA is the decimal value of the DAC_DATA register. DAC_GAIN and DAC_OFFSET are the user calibration settings. DATA data are left justified; the last two LSBs in the DAC_DATA register are ignored for the AFE782H1. Substituting DAC_GAIN and DAC_OFFSET in with and results in: D A C _ C O D E = ( D A T A × 1 2 + G A I N 2 N ) - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i The multiplier is implemented using truncation instead of rounding. This truncation can cause a difference of one LSB if rounding is expected. shows the DAC calibration path. DAC Calibration Path DAC Gain and Offset Calibration The AFEx82H1 provide DAC gain and offset calibration capability to correct for end-point errors present in the system. Implement the gain and offset calibration using two registers, DAC_GAIN.GAIN and DAC_OFFSET.OFFSET. Update DAC_DATA register after gain or offset codes are changed for the new values to take effect. The DAC_GAIN can be programmed from 0.5 to 1.499985 using . D A C _ G A I N = 1 2 + G A I N 2 N where N = DAC_GAIN resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. GAIN is the decimal value of the DAC_GAIN register setting. GAIN data are left justified; the last two LSBs in the DAC_GAIN register are ignored for the AFE782H1. The example DAC_GAIN settings for the AFE882H1 are shown in . DAC_GAIN Setting vs GAIN Code DAC_GAIN GAIN (HEX) 0.5 0x0000 1.0 0x8000 1.499985 0xFFFF The DAC_OFFSET is stored in the DAC_OFFSET register using 2's-complement encoding. The DAC_OFFSET value can be programmed from –2(N–1) to 2(N–1) – 1 using . D A C _ O F F S E T = - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i where N = DAC_OFFSET resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. OFFSETMSB = MSB bit of the DAC_OFFSET register. OFFSET i = The rest of the bits of the DAC_OFFSET register. i = Position of the bit in the DAC_OFFSET register. OFFSET data are left justified; the last two LSBs in the DAC_OFFSET register are ignored for the device. The most significant bit determines the sign of the number and is called the sign bit. The sign bit has the weight of –2(N–1) as shown in . The example DAC_OFFSET settings for the AFE882H1 are shown in . DAC_OFFSET Setting vs OFFSET Code DAC_OFFSET OFFSET (HEX) 32767 0x7FFF 1 0x0001 0 0x0000 –1 0xFFFF –2 0xFFFE –32768 0x8000 The following transfer function is applied to the DAC_DATA.DATA based on the DAC_GAIN and DAC_OFFSET values: D A C _ C O D E = ( D A T A × D A C _ G A I N ) + D A C _ O F F S E T where DAC_CODE is the internal signal applied to the DAC. DATA is the decimal value of the DAC_DATA register. DAC_GAIN and DAC_OFFSET are the user calibration settings. DATA data are left justified; the last two LSBs in the DAC_DATA register are ignored for the AFE782H1. Substituting DAC_GAIN and DAC_OFFSET in with and results in: D A C _ C O D E = ( D A T A × 1 2 + G A I N 2 N ) - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i The multiplier is implemented using truncation instead of rounding. This truncation can cause a difference of one LSB if rounding is expected. shows the DAC calibration path. DAC Calibration Path The AFEx82H1 provide DAC gain and offset calibration capability to correct for end-point errors present in the system. Implement the gain and offset calibration using two registers, DAC_GAIN.GAIN and DAC_OFFSET.OFFSET. Update DAC_DATA register after gain or offset codes are changed for the new values to take effect. The DAC_GAIN can be programmed from 0.5 to 1.499985 using . D A C _ G A I N = 1 2 + G A I N 2 N where N = DAC_GAIN resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. GAIN is the decimal value of the DAC_GAIN register setting. GAIN data are left justified; the last two LSBs in the DAC_GAIN register are ignored for the AFE782H1. The example DAC_GAIN settings for the AFE882H1 are shown in . DAC_GAIN Setting vs GAIN Code DAC_GAIN GAIN (HEX) 0.5 0x0000 1.0 0x8000 1.499985 0xFFFF The DAC_OFFSET is stored in the DAC_OFFSET register using 2's-complement encoding. The DAC_OFFSET value can be programmed from –2(N–1) to 2(N–1) – 1 using . D A C _ O F F S E T = - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i where N = DAC_OFFSET resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. OFFSETMSB = MSB bit of the DAC_OFFSET register. OFFSET i = The rest of the bits of the DAC_OFFSET register. i = Position of the bit in the DAC_OFFSET register. OFFSET data are left justified; the last two LSBs in the DAC_OFFSET register are ignored for the device. The most significant bit determines the sign of the number and is called the sign bit. The sign bit has the weight of –2(N–1) as shown in . The example DAC_OFFSET settings for the AFE882H1 are shown in . DAC_OFFSET Setting vs OFFSET Code DAC_OFFSET OFFSET (HEX) 32767 0x7FFF 1 0x0001 0 0x0000 –1 0xFFFF –2 0xFFFE –32768 0x8000 The following transfer function is applied to the DAC_DATA.DATA based on the DAC_GAIN and DAC_OFFSET values: D A C _ C O D E = ( D A T A × D A C _ G A I N ) + D A C _ O F F S E T where DAC_CODE is the internal signal applied to the DAC. DATA is the decimal value of the DAC_DATA register. DAC_GAIN and DAC_OFFSET are the user calibration settings. DATA data are left justified; the last two LSBs in the DAC_DATA register are ignored for the AFE782H1. Substituting DAC_GAIN and DAC_OFFSET in with and results in: D A C _ C O D E = ( D A T A × 1 2 + G A I N 2 N ) - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i The multiplier is implemented using truncation instead of rounding. This truncation can cause a difference of one LSB if rounding is expected. shows the DAC calibration path. DAC Calibration Path The AFEx82H1 provide DAC gain and offset calibration capability to correct for end-point errors present in the system. Implement the gain and offset calibration using two registers, DAC_GAIN.GAIN and DAC_OFFSET.OFFSET. Update DAC_DATA register after gain or offset codes are changed for the new values to take effect. The DAC_GAIN can be programmed from 0.5 to 1.499985 using .AFEx82H1 D A C _ G A I N = 1 2 + G A I N 2 N D A C _ G A I N = 1 2 + G A I N 2 N D A C _ G A I N = 1 2 + G A I N 2 N DAC_GAIN= 1 2 1 1 2 2+ G A I N 2 N G A I N GAIN 2 N 2 N 2 2 N Nwhere N = DAC_GAIN resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. GAIN is the decimal value of the DAC_GAIN register setting. GAIN data are left justified; the last two LSBs in the DAC_GAIN register are ignored for the AFE782H1. N = DAC_GAIN resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1.AFE882H1AFE782H1GAIN is the decimal value of the DAC_GAIN register setting.GAIN data are left justified; the last two LSBs in the DAC_GAIN register are ignored for the AFE782H1.AFE782H1The example DAC_GAIN settings for the AFE882H1 are shown in .AFE882H1 DAC_GAIN Setting vs GAIN Code DAC_GAIN GAIN (HEX) 0.5 0x0000 1.0 0x8000 1.499985 0xFFFF DAC_GAIN Setting vs GAIN Code DAC_GAIN GAIN (HEX) 0.5 0x0000 1.0 0x8000 1.499985 0xFFFF DAC_GAIN GAIN (HEX) DAC_GAIN GAIN (HEX) DAC_GAINGAIN (HEX) 0.5 0x0000 1.0 0x8000 1.499985 0xFFFF 0.5 0x0000 0.50x0000 1.0 0x8000 1.00x8000 1.499985 0xFFFF 1.4999850xFFFFThe DAC_OFFSET is stored in the DAC_OFFSET register using 2's-complement encoding. The DAC_OFFSET value can be programmed from –2(N–1) to 2(N–1) – 1 using .(N–1)(N–1) D A C _ O F F S E T = - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i D A C _ O F F S E T = - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i D A C _ O F F S E T = - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i DAC_OFFSET=- O F F S E T M S B O F F S E T OFFSET M S B MSB× 2 ( N - 1 ) 2 2 ( N - 1 ) (N-1)+ ∑ i = 0 ( N - 2 ) O F F S E T i ∑ i = 0 ( N - 2 ) ∑ i = 0 i=0 ( N - 2 ) (N-2) O F F S E T i O F F S E T i O F F S E T OFFSET i i × 2 i × 2 ×2 i iwhere N = DAC_OFFSET resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1. OFFSETMSB = MSB bit of the DAC_OFFSET register. OFFSET i = The rest of the bits of the DAC_OFFSET register. i = Position of the bit in the DAC_OFFSET register. OFFSET data are left justified; the last two LSBs in the DAC_OFFSET register are ignored for the device. N = DAC_OFFSET resolution in bits: 16 for the AFE882H1 and 14 for the AFE782H1.AFE882H1AFE782H1OFFSETMSB = MSB bit of the DAC_OFFSET register.MSBOFFSET i = The rest of the bits of the DAC_OFFSET register. i i i = Position of the bit in the DAC_OFFSET register.iOFFSET data are left justified; the last two LSBs in the DAC_OFFSET register are ignored for the device.The most significant bit determines the sign of the number and is called the sign bit. The sign bit has the weight of –2(N–1) as shown in .(N–1)The example DAC_OFFSET settings for the AFE882H1 are shown in .AFE882H1 DAC_OFFSET Setting vs OFFSET Code DAC_OFFSET OFFSET (HEX) 32767 0x7FFF 1 0x0001 0 0x0000 –1 0xFFFF –2 0xFFFE –32768 0x8000 DAC_OFFSET Setting vs OFFSET Code DAC_OFFSET OFFSET (HEX) 32767 0x7FFF 1 0x0001 0 0x0000 –1 0xFFFF –2 0xFFFE –32768 0x8000 DAC_OFFSET OFFSET (HEX) DAC_OFFSET OFFSET (HEX) DAC_OFFSETOFFSET (HEX) 32767 0x7FFF 1 0x0001 0 0x0000 –1 0xFFFF –2 0xFFFE –32768 0x8000 32767 0x7FFF 327670x7FFF 1 0x0001 10x0001 0 0x0000 00x0000 –1 0xFFFF –10xFFFF –2 0xFFFE –20xFFFE –32768 0x8000 –327680x8000The following transfer function is applied to the DAC_DATA.DATA based on the DAC_GAIN and DAC_OFFSET values: D A C _ C O D E = ( D A T A × D A C _ G A I N ) + D A C _ O F F S E T D A C _ C O D E = ( D A T A × D A C _ G A I N ) + D A C _ O F F S E T D A C _ C O D E = ( D A T A × D A C _ G A I N ) + D A C _ O F F S E T DAC_CODE=(DATA×DAC_GAIN)+DAC_OFFSETwhere DAC_CODE is the internal signal applied to the DAC. DATA is the decimal value of the DAC_DATA register. DAC_GAIN and DAC_OFFSET are the user calibration settings. DATA data are left justified; the last two LSBs in the DAC_DATA register are ignored for the AFE782H1. DAC_CODE is the internal signal applied to the DAC.DATA is the decimal value of the DAC_DATA register.DAC_GAIN and DAC_OFFSET are the user calibration settings.DATA data are left justified; the last two LSBs in the DAC_DATA register are ignored for the AFE782H1.AFE782H1Substituting DAC_GAIN and DAC_OFFSET in with and results in: D A C _ C O D E = ( D A T A × 1 2 + G A I N 2 N ) - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i D A C _ C O D E = ( D A T A × 1 2 + G A I N 2 N ) - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i D A C _ C O D E = ( D A T A × 1 2 + G A I N 2 N ) - O F F S E T M S B × 2 ( N - 1 ) + ∑ i = 0 ( N - 2 ) O F F S E T i × 2 i DAC_CODE=(DATA× 1 2 + G A I N 2 N 1 2 + G A I N 2 N 1 2 1 1 2 2+ G A I N 2 N G A I N GAIN 2 N 2 N 2 2 N N)- O F F S E T M S B O F F S E T OFFSET M S B MSB× 2 ( N - 1 ) 2 2 ( N - 1 ) (N-1)+ ∑ i = 0 ( N - 2 ) O F F S E T i ∑ i = 0 ( N - 2 ) ∑ i = 0 i=0 ( N - 2 ) (N-2) O F F S E T i O F F S E T i O F F S E T OFFSET i i × 2 i × 2 ×2 i iThe multiplier is implemented using truncation instead of rounding. This truncation can cause a difference of one LSB if rounding is expected. shows the DAC calibration path. DAC Calibration Path DAC Calibration Path Programmable Slew Rate The slew rate feature controls the rate at which the output voltage or current changes. This feature is disabled by default and is enabled by writing a logic 1 to the DAC_CFG.SR_EN bit. With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load. With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by DAC_CFG.SR_STEP[2:0] and DAC_CFG.SR_CLK[2:0]. SR_CLK defines the rate at which the digital slew updates. SR_STEP defines the amount by which the output value changes at each update. The register descriptions show different settings for SR_STEP and SR_CLK. The time required for the output to slew is expressed as : S l e w   T i m e   =   D e l t a   C o d e   C h a n g e S l e w   S t e p   ×   S l e w   C l o c k   R a t e where Slew Time is expressed in seconds Slew Step is controlled by DAC_CFG.SR_STEP Slew Clock Rate is controlled by DAC_CFG.SR_CLK When the slew-rate control feature is enabled, the output changes at the programmed slew rate. This configuration results in a staircase formation at the output. If the clear code is asserted (see ), the output slews to the DAC_CLR_CODE value at the programmed slew rate. When new DAC data are written, the output starts slewing to the new value at the slew rate determined by the current DAC code and the new DAC data. Two slew-rate control modes are available: linear (default) and sinusoidal. and show the typical rising and falling DAC output waveforms, respectively. Linear Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Linear Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt Sinusoidal mode enables fast DAC settling while improving analog rate of change characteristics. Sinusoidal mode is selected by the DAC_CFG.SR_MODE bit. and show the typical rising and falling DAC output waveforms with sinusoidal slew-rate control, respectively. Sinusoidal Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Sinusoidal Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt If the slew-rate feature is disabled while the DAC is executing the slew-rate command, the slew-rate operation is aborted, and the DAC output goes to the target code. Programmable Slew Rate The slew rate feature controls the rate at which the output voltage or current changes. This feature is disabled by default and is enabled by writing a logic 1 to the DAC_CFG.SR_EN bit. With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load. With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by DAC_CFG.SR_STEP[2:0] and DAC_CFG.SR_CLK[2:0]. SR_CLK defines the rate at which the digital slew updates. SR_STEP defines the amount by which the output value changes at each update. The register descriptions show different settings for SR_STEP and SR_CLK. The time required for the output to slew is expressed as : S l e w   T i m e   =   D e l t a   C o d e   C h a n g e S l e w   S t e p   ×   S l e w   C l o c k   R a t e where Slew Time is expressed in seconds Slew Step is controlled by DAC_CFG.SR_STEP Slew Clock Rate is controlled by DAC_CFG.SR_CLK When the slew-rate control feature is enabled, the output changes at the programmed slew rate. This configuration results in a staircase formation at the output. If the clear code is asserted (see ), the output slews to the DAC_CLR_CODE value at the programmed slew rate. When new DAC data are written, the output starts slewing to the new value at the slew rate determined by the current DAC code and the new DAC data. Two slew-rate control modes are available: linear (default) and sinusoidal. and show the typical rising and falling DAC output waveforms, respectively. Linear Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Linear Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt Sinusoidal mode enables fast DAC settling while improving analog rate of change characteristics. Sinusoidal mode is selected by the DAC_CFG.SR_MODE bit. and show the typical rising and falling DAC output waveforms with sinusoidal slew-rate control, respectively. Sinusoidal Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Sinusoidal Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt If the slew-rate feature is disabled while the DAC is executing the slew-rate command, the slew-rate operation is aborted, and the DAC output goes to the target code. The slew rate feature controls the rate at which the output voltage or current changes. This feature is disabled by default and is enabled by writing a logic 1 to the DAC_CFG.SR_EN bit. With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load. With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by DAC_CFG.SR_STEP[2:0] and DAC_CFG.SR_CLK[2:0]. SR_CLK defines the rate at which the digital slew updates. SR_STEP defines the amount by which the output value changes at each update. The register descriptions show different settings for SR_STEP and SR_CLK. The time required for the output to slew is expressed as : S l e w   T i m e   =   D e l t a   C o d e   C h a n g e S l e w   S t e p   ×   S l e w   C l o c k   R a t e where Slew Time is expressed in seconds Slew Step is controlled by DAC_CFG.SR_STEP Slew Clock Rate is controlled by DAC_CFG.SR_CLK When the slew-rate control feature is enabled, the output changes at the programmed slew rate. This configuration results in a staircase formation at the output. If the clear code is asserted (see ), the output slews to the DAC_CLR_CODE value at the programmed slew rate. When new DAC data are written, the output starts slewing to the new value at the slew rate determined by the current DAC code and the new DAC data. Two slew-rate control modes are available: linear (default) and sinusoidal. and show the typical rising and falling DAC output waveforms, respectively. Linear Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Linear Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt Sinusoidal mode enables fast DAC settling while improving analog rate of change characteristics. Sinusoidal mode is selected by the DAC_CFG.SR_MODE bit. and show the typical rising and falling DAC output waveforms with sinusoidal slew-rate control, respectively. Sinusoidal Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Sinusoidal Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt If the slew-rate feature is disabled while the DAC is executing the slew-rate command, the slew-rate operation is aborted, and the DAC output goes to the target code. The slew rate feature controls the rate at which the output voltage or current changes. This feature is disabled by default and is enabled by writing a logic 1 to the DAC_CFG.SR_EN bit. With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load.With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by DAC_CFG.SR_STEP[2:0] and DAC_CFG.SR_CLK[2:0]. SR_CLK defines the rate at which the digital slew updates. SR_STEP defines the amount by which the output value changes at each update. The register descriptions show different settings for SR_STEP and SR_CLK.The time required for the output to slew is expressed as : S l e w   T i m e   =   D e l t a   C o d e   C h a n g e S l e w   S t e p   ×   S l e w   C l o c k   R a t e S l e w   T i m e   =   D e l t a   C o d e   C h a n g e S l e w   S t e p   ×   S l e w   C l o c k   R a t e S l e w   T i m e   =   D e l t a   C o d e   C h a n g e S l e w   S t e p   ×   S l e w   C l o c k   R a t e Slew Time =   D e l t a   C o d e   C h a n g e S l e w   S t e p   ×   S l e w   C l o c k   R a t e   D e l t a   C o d e   C h a n g e  Delta Code Change S l e w   S t e p   ×   S l e w   C l o c k   R a t e Slew Step × Slew Clock Ratewhere Slew Time is expressed in seconds Slew Step is controlled by DAC_CFG.SR_STEP Slew Clock Rate is controlled by DAC_CFG.SR_CLK Slew Time is expressed in secondsSlew Time Slew Step is controlled by DAC_CFG.SR_STEP Slew Step Slew Clock Rate is controlled by DAC_CFG.SR_CLK Slew Clock RateWhen the slew-rate control feature is enabled, the output changes at the programmed slew rate. This configuration results in a staircase formation at the output. If the clear code is asserted (see ), the output slews to the DAC_CLR_CODE value at the programmed slew rate. When new DAC data are written, the output starts slewing to the new value at the slew rate determined by the current DAC code and the new DAC data.Two slew-rate control modes are available: linear (default) and sinusoidal. and show the typical rising and falling DAC output waveforms, respectively. Linear Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Linear Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt Linear Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Linear Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Linear Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt Linear Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shuntSinusoidal mode enables fast DAC settling while improving analog rate of change characteristics. Sinusoidal mode is selected by the DAC_CFG.SR_MODE bit. and show the typical rising and falling DAC output waveforms with sinusoidal slew-rate control, respectively. Sinusoidal Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Sinusoidal Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt Sinusoidal Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Sinusoidal Slew Rate: Rising 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Sinusoidal Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt Sinusoidal Slew Rate: Falling 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shunt 24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω shuntIf the slew-rate feature is disabled while the DAC is executing the slew-rate command, the slew-rate operation is aborted, and the DAC output goes to the target code. DAC Register Structure and CLEAR State The AFE882H1 DAC has a 16-bit voltage output, and the AFE782H1 DAC has a 14-bit voltage output. The output range is 0 V to 2.5 V. The AFEx82H1 provide the option to quickly set the DAC output to the value set in the DAC_CLR_CODE register without writing to the DAC_DATA register, referred to as the CLEAR state. For register details, see . Transitioning from the DAC_DATA to the DAC_CLR_CODE is synchronous to the clock. If slew mode is enabled, the output slews during the transition. shows the full AFEx82H1 DAC_DATA signal path. The devices synchronize the DAC_DATA code to the internal clock, causing up to 2.5 internal clock cycles of latency (2 μs) with respect to the rising edge of CS or the end of a UBM command. Update DAC_GAIN and DAC_OFFSET values when DAC_CFG.SR_EN = 0 to avoid an IRQ pulse generated by SR_BUSY. Set the DAC to CLEAR state either by: Setting DAC_CFG.CLR. Configuring the DAC to transition to the CLEAR state in response to an alarm condition. Using the SDI pin in UBM as the CLEAR state input pin. Method 1 is a direct command to the AFEx82H1 to set the DAC to CLEAR state. Set the DAC_CFG.CLR bit to 1h to set the DAC to CLEAR state. Method 2 is controlled by settings of ALARM_ACT register. For details of conditions and other masks required to use this method, see and . Method 3 supports setting the DAC to CLEAR state without writing to the AFEx82H1. This pin-based DAC CLEAR state function is available only in UBM on the SDI pin. For details of connection options based on communication modes and pins used in each mode, see . Set the appropriate pin high to drive the DAC to CLEAR state. DAC Data Path DAC Register Structure and CLEAR State The AFE882H1 DAC has a 16-bit voltage output, and the AFE782H1 DAC has a 14-bit voltage output. The output range is 0 V to 2.5 V. The AFEx82H1 provide the option to quickly set the DAC output to the value set in the DAC_CLR_CODE register without writing to the DAC_DATA register, referred to as the CLEAR state. For register details, see . Transitioning from the DAC_DATA to the DAC_CLR_CODE is synchronous to the clock. If slew mode is enabled, the output slews during the transition. shows the full AFEx82H1 DAC_DATA signal path. The devices synchronize the DAC_DATA code to the internal clock, causing up to 2.5 internal clock cycles of latency (2 μs) with respect to the rising edge of CS or the end of a UBM command. Update DAC_GAIN and DAC_OFFSET values when DAC_CFG.SR_EN = 0 to avoid an IRQ pulse generated by SR_BUSY. Set the DAC to CLEAR state either by: Setting DAC_CFG.CLR. Configuring the DAC to transition to the CLEAR state in response to an alarm condition. Using the SDI pin in UBM as the CLEAR state input pin. Method 1 is a direct command to the AFEx82H1 to set the DAC to CLEAR state. Set the DAC_CFG.CLR bit to 1h to set the DAC to CLEAR state. Method 2 is controlled by settings of ALARM_ACT register. For details of conditions and other masks required to use this method, see and . Method 3 supports setting the DAC to CLEAR state without writing to the AFEx82H1. This pin-based DAC CLEAR state function is available only in UBM on the SDI pin. For details of connection options based on communication modes and pins used in each mode, see . Set the appropriate pin high to drive the DAC to CLEAR state. DAC Data Path The AFE882H1 DAC has a 16-bit voltage output, and the AFE782H1 DAC has a 14-bit voltage output. The output range is 0 V to 2.5 V. The AFEx82H1 provide the option to quickly set the DAC output to the value set in the DAC_CLR_CODE register without writing to the DAC_DATA register, referred to as the CLEAR state. For register details, see . Transitioning from the DAC_DATA to the DAC_CLR_CODE is synchronous to the clock. If slew mode is enabled, the output slews during the transition. shows the full AFEx82H1 DAC_DATA signal path. The devices synchronize the DAC_DATA code to the internal clock, causing up to 2.5 internal clock cycles of latency (2 μs) with respect to the rising edge of CS or the end of a UBM command. Update DAC_GAIN and DAC_OFFSET values when DAC_CFG.SR_EN = 0 to avoid an IRQ pulse generated by SR_BUSY. Set the DAC to CLEAR state either by: Setting DAC_CFG.CLR. Configuring the DAC to transition to the CLEAR state in response to an alarm condition. Using the SDI pin in UBM as the CLEAR state input pin. Method 1 is a direct command to the AFEx82H1 to set the DAC to CLEAR state. Set the DAC_CFG.CLR bit to 1h to set the DAC to CLEAR state. Method 2 is controlled by settings of ALARM_ACT register. For details of conditions and other masks required to use this method, see and . Method 3 supports setting the DAC to CLEAR state without writing to the AFEx82H1. This pin-based DAC CLEAR state function is available only in UBM on the SDI pin. For details of connection options based on communication modes and pins used in each mode, see . Set the appropriate pin high to drive the DAC to CLEAR state. DAC Data Path The AFE882H1 DAC has a 16-bit voltage output, and the AFE782H1 DAC has a 14-bit voltage output. The output range is 0 V to 2.5 V. AFE882H1AFE782H1The output range is 0 V to 2.5 V.The AFEx82H1 provide the option to quickly set the DAC output to the value set in the DAC_CLR_CODE register without writing to the DAC_DATA register, referred to as the CLEAR state. For register details, see . AFEx82H1Transitioning from the DAC_DATA to the DAC_CLR_CODE is synchronous to the clock. If slew mode is enabled, the output slews during the transition. shows the full AFEx82H1 DAC_DATA signal path. The devices synchronize the DAC_DATA code to the internal clock, causing up to 2.5 internal clock cycles of latency (2 μs) with respect to the rising edge of CS or the end of a UBM command. Update DAC_GAIN and DAC_OFFSET values when DAC_CFG.SR_EN = 0 to avoid an IRQ pulse generated by SR_BUSY. AFEx82H1CSSet the DAC to CLEAR state either by: Setting DAC_CFG.CLR. Configuring the DAC to transition to the CLEAR state in response to an alarm condition. Using the SDI pin in UBM as the CLEAR state input pin. Setting DAC_CFG.CLR.Configuring the DAC to transition to the CLEAR state in response to an alarm condition.Using the SDI pin in UBM as the CLEAR state input pin.Method 1 is a direct command to the AFEx82H1 to set the DAC to CLEAR state. Set the DAC_CFG.CLR bit to 1h to set the DAC to CLEAR state. AFEx82H1Method 2 is controlled by settings of ALARM_ACT register. For details of conditions and other masks required to use this method, see and .Method 3 supports setting the DAC to CLEAR state without writing to the AFEx82H1. This pin-based DAC CLEAR state function is available only in UBM on the SDI pin. For details of connection options based on communication modes and pins used in each mode, see . Set the appropriate pin high to drive the DAC to CLEAR state.AFEx82H1only in UBM on the SDI pin DAC Data Path DAC Data Path Analog-to-Digital Converter (ADC) Overview The AFEx82H1 feature a monitoring system centered on a 12-bit successive approximation register (SAR) ADC and a highly flexible analog multiplexer. The monitoring system is capable of sensing up to two external inputs, as well as several internal device signals. The ADC uses the VREFIO pin voltage as a reference. The ADC timing signals are derived from an on-chip oscillator. The conversion results are accessed through the device serial interface. ADC Operation The device ADC supports direct-mode and auto-mode conversions. Both conversion modes use a custom channel sequencer to determine which of the input channels are converted by the ADC. The sequence order is fixed. The user selects the start channel and stop channel of the conversion sequence. The conversion method and channel sequence are specified in the ADC Configuration registers. The default conversion method is auto-mode. shows the ADC conversion sequence. ADC Conversion Sequence To use the ADC, first enable the ADC buffer by setting ADC_CFG.BUF_PD = 0. Then wait at least 210 μs before setting the trigger using the TRIGGER.ADC bit. An internal delay is forced if the trigger signal is sent before the timer has expired. Make sure the ADC is not converting before setting the ADC_CFG.BUF_PD = 1. If ADC_CFG.BUF_PD is set to 1 while the ADC is still converting, the internal timer delays this command. When the timer expires, the enable signal for the ADC is cleared, and the current conversion finishes before powering down the ADC and the ADC Buffer. A trigger signal must occur for the ADC to exit the idle state. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode conversion, the selected ADC input channels are converted on demand by issuing an ADC trigger signal. After the last enabled channel is converted, the ADC enters the idle state and waits for a new trigger. Read the results of the ADC conversion through the register map. Direct-mode conversion is typically used to gather the ADC data of any of the data channels. In direct-mode, use the ADC_BUSY bit to determine when a direct-mode conversion is complete and the ADC has returned to the idle state. Direct mode is set by writing ADC_CFG.DIRECT_MODE = 1. In auto-mode conversion, the selected ADC input channels are converted continuously. The conversion cycle is initiated by issuing an ADC trigger. Upon completion of the first conversion sequence, another sequence is automatically started. Conversion of the selected channels occurs repeatedly until the auto-mode conversion is stopped by clearing the ADC trigger signal. Auto-mode conversion is not typically used to gather the ADC data. Instead, auto-mode conversions are used in combination with upper and lower ADC data thresholds to detect when the data has exceeded the programmable out-of-range alarm thresholds. Auto mode is set by writing ADC_CFG.DIRECT_MODE = 0. Regardless of the selected conversion method, update the ADC configuration register only while the ADC is in the idle state. Do not change the ADC configuration bits while the ADC is converting channels. Before changing configuration bits, disable the ADC and verify that GEN_STATUS.ADC_BUSY = 0. ADC Custom Channel Sequencer The device uses a custom channel sequencer to control the multiplexer of the ADC. The ADC sequencer allows the user to specify which channels are converted. The sequencer consists of 16 indexed slots with programmable start and stop index fields to configure the start and stop conversion points. In direct-mode conversion, the ADC converts from the start index to the stop index once and then stops. In auto-mode conversion, the ADC converts from the start to stop index repeatedly until the ADC is stopped. shows the indexed custom channel sequence slots available in the device. ADC MUX Control lists the ADC input channel assignments for the sequencer. Indexed Custom Channel Sequence CCS POINTER CHANNEL CONV_RATE RANGE 0 OFFSET 2560 Hz VREF 1 AIN0 Programmable Programmable 2 AIN1 Programmable Programmable 3 TEMP 2560 Hz VREF 4 SD0 (VREF) 2560 Hz VREF 5 SD1 (PVDD) 2560 Hz VREF 6 SD2 (VDD) 2560 Hz VREF 7 SD3 (ZTAT) 2560 Hz VREF 8 SD4 (VOUT) 2560 Hz 2 × VREF 9-15 GND 2560 Hz VREF Use the ADC_INDEX_CFG register to select the channels. The order of the channels is fixed and shown in . Then, use ADC_INDEX_CFG.START and ADC_INDEX_CFG.STOP to select the range of indices to convert. If these two values are the same, then the ADC only converts a single channel. If the START and STOP values are different, then the ADC cycles through the corresponding indices. By default, all channels are configured to be converted; START = 0 and STOP = 8. If the AIN1 channel is not configured as an ADC input, then the result for this channel is 0x000. The minimum time for a conversion is still allotted to AIN1 if the channel is within the START and STOP range. If START is configured to be greater than STOP, then the device interprets the conversion sequence as if START = STOP. In direct mode, each selected channel in the ADC_INDEX_CFG register is converted once per TRIGGER.ADC command. In auto mode, each channel selected in the ADC_INDEX_CFG register is converted once; after the last channel, the loop is repeated as long as the ADC is enabled. In auto mode, writing to TRIGGER.ADC = 1 starts the conversions. Writing TRIGGER.ADC = 0 disables the ADC after the current channel being converted finishes. In direct mode, writing TRIGGER.ADC = 1 starts the sequence. When the sequence ends, then TRIGGER.ADC is self-cleared. A minimum of 20 clock cycles is required to perform one conversion. The ADC clock is derived from the internal oscillator and divided by 16, which gives an ADC clock frequency of 1.2288 MHz / 16 = 76.8 kHz, for a clock period = 13.02 μs. Each of the internal nodes has a fixed conversion rate. Pins AIN0 and AIN1 have programmable conversion rates (see also the ADC_CFG register). Pins AIN0 and AIN1 also have a configurable range. The input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit. If any ADC configuration bits are changed, the following sequence is recommended: Disable the ADC Wait for ADC_BUSY to go low Change the configuration Restart the conversions ADC_BUSY can be monitored in the GEN_STATUS register. If the ADC is configured for direct mode (ADC_CFG.DIRECT_MODE = 1), then after setting the desired channels to convert, write a 1 to TRIGGER.ADC. This bit is self-cleared when the sequence is finished converting. This command converts all the selected channels once. To initiate another conversion of the channels, send another TRIGGER.ADC command. ADC Synchronization The trigger signal must be generated for the ADC to exit the idle state and start conversions. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode, use the GEN_STATUS.ADC_BUSY bit to determine when a direct-mode conversion is complete, and the ADC has returned to the idle state. Similarly, monitor the TRIGGER.ADC bit to see if the ADC has returned to the idle state. ADC Offset Calibration Channel 0 of the CCS pointer is named OFFSET. The OFFSET channel is used to calibrate and improve the ADC offset performance. Convert the OFFSET channel, and use the result as a calibration for the ADC offset in subsequent measurements. This ADC channel samples VREF / 2 and compares this result against 7FFh as a measure of the ADC offset. The data rate for the ADC measuring this channel is 2560 Hz. The ADC conversion for the OFFSET channel is subtracted from 7FFh and the resulting value is stored in ADC_OFFSET (28h). The offset can be positive or negative; therefore, the value is stored in 2’s complement notation. With the subtraction from 7FFh, ADC_OFFSET is the negative of the offset. This value is subtracted from conversions of the ADC by default. For direct measurements of the ADC, set ADC_BYP.OFST_BYP_EN to 1 to enable the offset bypass; see . External Monitoring Inputs The AFEx82H1 have two analog inputs for external voltage sensing. Channels 1 and 2 for the CCS pointer are for external monitoring inputs that can be measured by pins AIN0 and AIN1, respectively. The input range for the analog inputs is configurable to either 0 V to 1.25 V or 0 V to 2.5 V. The analog inputs conversion values are stored in straight binary format in the ADC registers. The ADC resolution can be computed by : 1   L S B = V R A N G E 2 12 where VRANGE = 2.5 V for the 0‑V to 2.5‑V input range or 1.25 V for the 0‑V to 1.25‑V input range. and detail the transfer characteristics. ADC Transfer Characteristics Transfer Characteristics INPUT VOLTAGE CODE DESCRIPTION IDEAL OUTPUT CODE ≤1 LSB NFSC Negative full-scale code 000 1 LSB to 2 LSB NFSC + 1 Negative full-scale code plus 1 001 (VRANGE / 2) to (VRANGE / 2) + 1 LSB MC Midcode 800 (VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSB MC + 1 Midcode plus 1 801 ≥ VRANGE – 1 LSB PFSC Positive full-scale code FFF For these external monitoring inputs, the ADC is configurable for both data rate and voltage range. The data rate is set to either 640 Hz, 1280 Hz, 2560 Hz, or 3840 Hz with the ADC_CFG.CONV_RATE bits. The range of the ADC measurement is set with the ADC_CFG.AIN_RANGE bit. The ADC range is 2 × VREF when the bit = 0; the ADC range is VREF when the bit = 1. When the ADC conversion is completed for AIN0 and AIN1, the resulting ADC data are stored in the ADC_AIN0.DATA and ADC_AIN1.DATA bits at 24h and 25h of the register map. If the external monitoring inputs are not used, connect the AIN0 and AIN1 pins to GND through a 1-kΩ resistor. Temperature Sensor Channel 3 of the CCS is used to measure the die temperature of the device. The ADC measures an internal temperature sensor that measures a voltage complementary to the absolute temperature (CTAT). This CTAT voltage has a negative temperature coefficient. The ADC converts this voltage at a data rate of 2560 Hz. When the ADC conversion is completed, the data are found in the ADC_TEMP.DATA bits (address 26h). The relationship between the ambient temperature and the ADC code is shown in #GUID-A307B900-C147-485E-AF3B-AFFF3E5B4EBD/GUID-09CDF47B-A831-42BA-B93C-B59905D9CECB: ADC Code = 2681   - 11 × T A ( ° C ) Self-Diagnostic Multiplexer In addition to the ADC offset, the two external monitoring inputs, and the temperature sensor, the ADC of the AFEx82H1 has five other internal inputs to monitor the reference voltage, the power supplies, a static voltage, and the DAC output. These five voltages measurements are part of the self-diagnostic multiplexer (SD0 to SD4) measurements of the ADC, and are reported in the ADC_SD_MUX register at 27h; see also . Channel 4 (SD0) measures the reference voltage of the device. The ADC measures the reference voltage through a resistor divider (divide by two). Be aware that all ADC measurements are a function of the reference; using SD0 to measure the reference is not revealing as a diagnostic measurement. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 5 (SD1) measures the PVDD power supply of the device. The ADC measures the PVDD voltage through a resistor divider (divide by six). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 6 (SD2) measures the VDD power supply of the device. When channel 6 is selected, the ADC measures the VDD voltage through a resistor divider (divide by 2). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 7 (SD3) is a ZTAT (zero temperature coefficient) voltage. This internal voltage is nominally 0.6 V with a low temperature drift and does not depend on the reference voltage. An ADC measurement of ZTAT voltage can be useful to determine the state of the reference voltage. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 8 (SD4) measures the VOUT of the DAC. The ADC measures the VOUT voltage through a resistor divider (divide by two). The data rate for this conversion is 2560 Hz and the range of the ADC is set to 2 × VREF. ADC Bypass To test the offset, modify the ADC data path by programming the bypass data register, ADC_BYP.DATA (2Eh). This read/write register is used in two different ways. First, by setting the ADC_BYP.OFST_BYP_EN to 1, this bypass data register is used as a substitute for the ADC_OFFSET. However, if the ADC_BYP.DATA data must be stored in the ADC_OFFSET register, use the second method. Second, the ADC_BYP.DATA is used to set a known value into the ADC readback register of the channel being converted. Write the desired data into ADC_BYP.DATA, set the ADC_BYP.DATA_BYP_EN bit, and convert the selected channel. When ADC_BYP.DATA_BYP_EN bit is set to 1, the ADC conversion is bypassed, and the value of ADC_BYP.DATA is written into the selected ADC channel readback register. This setting is used to test the alarm settings of the ADC. When the ADC bypass is unused, set the ADC_BYP.DATA to 000h. shows the ADC bypass data flow. ADC Bypass Data Flow Analog-to-Digital Converter (ADC) Overview The AFEx82H1 feature a monitoring system centered on a 12-bit successive approximation register (SAR) ADC and a highly flexible analog multiplexer. The monitoring system is capable of sensing up to two external inputs, as well as several internal device signals. The ADC uses the VREFIO pin voltage as a reference. The ADC timing signals are derived from an on-chip oscillator. The conversion results are accessed through the device serial interface. The AFEx82H1 feature a monitoring system centered on a 12-bit successive approximation register (SAR) ADC and a highly flexible analog multiplexer. The monitoring system is capable of sensing up to two external inputs, as well as several internal device signals. The ADC uses the VREFIO pin voltage as a reference. The ADC timing signals are derived from an on-chip oscillator. The conversion results are accessed through the device serial interface. The AFEx82H1 feature a monitoring system centered on a 12-bit successive approximation register (SAR) ADC and a highly flexible analog multiplexer. The monitoring system is capable of sensing up to two external inputs, as well as several internal device signals.AFEx82H1The ADC uses the VREFIO pin voltage as a reference. The ADC timing signals are derived from an on-chip oscillator. The conversion results are accessed through the device serial interface. ADC Operation The device ADC supports direct-mode and auto-mode conversions. Both conversion modes use a custom channel sequencer to determine which of the input channels are converted by the ADC. The sequence order is fixed. The user selects the start channel and stop channel of the conversion sequence. The conversion method and channel sequence are specified in the ADC Configuration registers. The default conversion method is auto-mode. shows the ADC conversion sequence. ADC Conversion Sequence To use the ADC, first enable the ADC buffer by setting ADC_CFG.BUF_PD = 0. Then wait at least 210 μs before setting the trigger using the TRIGGER.ADC bit. An internal delay is forced if the trigger signal is sent before the timer has expired. Make sure the ADC is not converting before setting the ADC_CFG.BUF_PD = 1. If ADC_CFG.BUF_PD is set to 1 while the ADC is still converting, the internal timer delays this command. When the timer expires, the enable signal for the ADC is cleared, and the current conversion finishes before powering down the ADC and the ADC Buffer. A trigger signal must occur for the ADC to exit the idle state. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode conversion, the selected ADC input channels are converted on demand by issuing an ADC trigger signal. After the last enabled channel is converted, the ADC enters the idle state and waits for a new trigger. Read the results of the ADC conversion through the register map. Direct-mode conversion is typically used to gather the ADC data of any of the data channels. In direct-mode, use the ADC_BUSY bit to determine when a direct-mode conversion is complete and the ADC has returned to the idle state. Direct mode is set by writing ADC_CFG.DIRECT_MODE = 1. In auto-mode conversion, the selected ADC input channels are converted continuously. The conversion cycle is initiated by issuing an ADC trigger. Upon completion of the first conversion sequence, another sequence is automatically started. Conversion of the selected channels occurs repeatedly until the auto-mode conversion is stopped by clearing the ADC trigger signal. Auto-mode conversion is not typically used to gather the ADC data. Instead, auto-mode conversions are used in combination with upper and lower ADC data thresholds to detect when the data has exceeded the programmable out-of-range alarm thresholds. Auto mode is set by writing ADC_CFG.DIRECT_MODE = 0. Regardless of the selected conversion method, update the ADC configuration register only while the ADC is in the idle state. Do not change the ADC configuration bits while the ADC is converting channels. Before changing configuration bits, disable the ADC and verify that GEN_STATUS.ADC_BUSY = 0. ADC Operation The device ADC supports direct-mode and auto-mode conversions. Both conversion modes use a custom channel sequencer to determine which of the input channels are converted by the ADC. The sequence order is fixed. The user selects the start channel and stop channel of the conversion sequence. The conversion method and channel sequence are specified in the ADC Configuration registers. The default conversion method is auto-mode. shows the ADC conversion sequence. ADC Conversion Sequence To use the ADC, first enable the ADC buffer by setting ADC_CFG.BUF_PD = 0. Then wait at least 210 μs before setting the trigger using the TRIGGER.ADC bit. An internal delay is forced if the trigger signal is sent before the timer has expired. Make sure the ADC is not converting before setting the ADC_CFG.BUF_PD = 1. If ADC_CFG.BUF_PD is set to 1 while the ADC is still converting, the internal timer delays this command. When the timer expires, the enable signal for the ADC is cleared, and the current conversion finishes before powering down the ADC and the ADC Buffer. A trigger signal must occur for the ADC to exit the idle state. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode conversion, the selected ADC input channels are converted on demand by issuing an ADC trigger signal. After the last enabled channel is converted, the ADC enters the idle state and waits for a new trigger. Read the results of the ADC conversion through the register map. Direct-mode conversion is typically used to gather the ADC data of any of the data channels. In direct-mode, use the ADC_BUSY bit to determine when a direct-mode conversion is complete and the ADC has returned to the idle state. Direct mode is set by writing ADC_CFG.DIRECT_MODE = 1. In auto-mode conversion, the selected ADC input channels are converted continuously. The conversion cycle is initiated by issuing an ADC trigger. Upon completion of the first conversion sequence, another sequence is automatically started. Conversion of the selected channels occurs repeatedly until the auto-mode conversion is stopped by clearing the ADC trigger signal. Auto-mode conversion is not typically used to gather the ADC data. Instead, auto-mode conversions are used in combination with upper and lower ADC data thresholds to detect when the data has exceeded the programmable out-of-range alarm thresholds. Auto mode is set by writing ADC_CFG.DIRECT_MODE = 0. Regardless of the selected conversion method, update the ADC configuration register only while the ADC is in the idle state. Do not change the ADC configuration bits while the ADC is converting channels. Before changing configuration bits, disable the ADC and verify that GEN_STATUS.ADC_BUSY = 0. The device ADC supports direct-mode and auto-mode conversions. Both conversion modes use a custom channel sequencer to determine which of the input channels are converted by the ADC. The sequence order is fixed. The user selects the start channel and stop channel of the conversion sequence. The conversion method and channel sequence are specified in the ADC Configuration registers. The default conversion method is auto-mode. shows the ADC conversion sequence. ADC Conversion Sequence To use the ADC, first enable the ADC buffer by setting ADC_CFG.BUF_PD = 0. Then wait at least 210 μs before setting the trigger using the TRIGGER.ADC bit. An internal delay is forced if the trigger signal is sent before the timer has expired. Make sure the ADC is not converting before setting the ADC_CFG.BUF_PD = 1. If ADC_CFG.BUF_PD is set to 1 while the ADC is still converting, the internal timer delays this command. When the timer expires, the enable signal for the ADC is cleared, and the current conversion finishes before powering down the ADC and the ADC Buffer. A trigger signal must occur for the ADC to exit the idle state. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode conversion, the selected ADC input channels are converted on demand by issuing an ADC trigger signal. After the last enabled channel is converted, the ADC enters the idle state and waits for a new trigger. Read the results of the ADC conversion through the register map. Direct-mode conversion is typically used to gather the ADC data of any of the data channels. In direct-mode, use the ADC_BUSY bit to determine when a direct-mode conversion is complete and the ADC has returned to the idle state. Direct mode is set by writing ADC_CFG.DIRECT_MODE = 1. In auto-mode conversion, the selected ADC input channels are converted continuously. The conversion cycle is initiated by issuing an ADC trigger. Upon completion of the first conversion sequence, another sequence is automatically started. Conversion of the selected channels occurs repeatedly until the auto-mode conversion is stopped by clearing the ADC trigger signal. Auto-mode conversion is not typically used to gather the ADC data. Instead, auto-mode conversions are used in combination with upper and lower ADC data thresholds to detect when the data has exceeded the programmable out-of-range alarm thresholds. Auto mode is set by writing ADC_CFG.DIRECT_MODE = 0. Regardless of the selected conversion method, update the ADC configuration register only while the ADC is in the idle state. Do not change the ADC configuration bits while the ADC is converting channels. Before changing configuration bits, disable the ADC and verify that GEN_STATUS.ADC_BUSY = 0. The device ADC supports direct-mode and auto-mode conversions. Both conversion modes use a custom channel sequencer to determine which of the input channels are converted by the ADC. The sequence order is fixed. The user selects the start channel and stop channel of the conversion sequence. The conversion method and channel sequence are specified in the ADC Configuration registers. The default conversion method is auto-mode. shows the ADC conversion sequence. ADC Conversion Sequence ADC Conversion SequenceTo use the ADC, first enable the ADC buffer by setting ADC_CFG.BUF_PD = 0. Then wait at least 210 μs before setting the trigger using the TRIGGER.ADC bit. An internal delay is forced if the trigger signal is sent before the timer has expired. Make sure the ADC is not converting before setting the ADC_CFG.BUF_PD = 1. If ADC_CFG.BUF_PD is set to 1 while the ADC is still converting, the internal timer delays this command. When the timer expires, the enable signal for the ADC is cleared, and the current conversion finishes before powering down the ADC and the ADC Buffer.A trigger signal must occur for the ADC to exit the idle state. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation.In direct-mode conversion, the selected ADC input channels are converted on demand by issuing an ADC trigger signal. After the last enabled channel is converted, the ADC enters the idle state and waits for a new trigger. Read the results of the ADC conversion through the register map. Direct-mode conversion is typically used to gather the ADC data of any of the data channels. In direct-mode, use the ADC_BUSY bit to determine when a direct-mode conversion is complete and the ADC has returned to the idle state. Direct mode is set by writing ADC_CFG.DIRECT_MODE = 1.In auto-mode conversion, the selected ADC input channels are converted continuously. The conversion cycle is initiated by issuing an ADC trigger. Upon completion of the first conversion sequence, another sequence is automatically started. Conversion of the selected channels occurs repeatedly until the auto-mode conversion is stopped by clearing the ADC trigger signal. Auto-mode conversion is not typically used to gather the ADC data. Instead, auto-mode conversions are used in combination with upper and lower ADC data thresholds to detect when the data has exceeded the programmable out-of-range alarm thresholds. Auto mode is set by writing ADC_CFG.DIRECT_MODE = 0.Regardless of the selected conversion method, update the ADC configuration register only while the ADC is in the idle state. Do not change the ADC configuration bits while the ADC is converting channels. Before changing configuration bits, disable the ADC and verify that GEN_STATUS.ADC_BUSY = 0. ADC Custom Channel Sequencer The device uses a custom channel sequencer to control the multiplexer of the ADC. The ADC sequencer allows the user to specify which channels are converted. The sequencer consists of 16 indexed slots with programmable start and stop index fields to configure the start and stop conversion points. In direct-mode conversion, the ADC converts from the start index to the stop index once and then stops. In auto-mode conversion, the ADC converts from the start to stop index repeatedly until the ADC is stopped. shows the indexed custom channel sequence slots available in the device. ADC MUX Control lists the ADC input channel assignments for the sequencer. Indexed Custom Channel Sequence CCS POINTER CHANNEL CONV_RATE RANGE 0 OFFSET 2560 Hz VREF 1 AIN0 Programmable Programmable 2 AIN1 Programmable Programmable 3 TEMP 2560 Hz VREF 4 SD0 (VREF) 2560 Hz VREF 5 SD1 (PVDD) 2560 Hz VREF 6 SD2 (VDD) 2560 Hz VREF 7 SD3 (ZTAT) 2560 Hz VREF 8 SD4 (VOUT) 2560 Hz 2 × VREF 9-15 GND 2560 Hz VREF Use the ADC_INDEX_CFG register to select the channels. The order of the channels is fixed and shown in . Then, use ADC_INDEX_CFG.START and ADC_INDEX_CFG.STOP to select the range of indices to convert. If these two values are the same, then the ADC only converts a single channel. If the START and STOP values are different, then the ADC cycles through the corresponding indices. By default, all channels are configured to be converted; START = 0 and STOP = 8. If the AIN1 channel is not configured as an ADC input, then the result for this channel is 0x000. The minimum time for a conversion is still allotted to AIN1 if the channel is within the START and STOP range. If START is configured to be greater than STOP, then the device interprets the conversion sequence as if START = STOP. In direct mode, each selected channel in the ADC_INDEX_CFG register is converted once per TRIGGER.ADC command. In auto mode, each channel selected in the ADC_INDEX_CFG register is converted once; after the last channel, the loop is repeated as long as the ADC is enabled. In auto mode, writing to TRIGGER.ADC = 1 starts the conversions. Writing TRIGGER.ADC = 0 disables the ADC after the current channel being converted finishes. In direct mode, writing TRIGGER.ADC = 1 starts the sequence. When the sequence ends, then TRIGGER.ADC is self-cleared. A minimum of 20 clock cycles is required to perform one conversion. The ADC clock is derived from the internal oscillator and divided by 16, which gives an ADC clock frequency of 1.2288 MHz / 16 = 76.8 kHz, for a clock period = 13.02 μs. Each of the internal nodes has a fixed conversion rate. Pins AIN0 and AIN1 have programmable conversion rates (see also the ADC_CFG register). Pins AIN0 and AIN1 also have a configurable range. The input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit. If any ADC configuration bits are changed, the following sequence is recommended: Disable the ADC Wait for ADC_BUSY to go low Change the configuration Restart the conversions ADC_BUSY can be monitored in the GEN_STATUS register. If the ADC is configured for direct mode (ADC_CFG.DIRECT_MODE = 1), then after setting the desired channels to convert, write a 1 to TRIGGER.ADC. This bit is self-cleared when the sequence is finished converting. This command converts all the selected channels once. To initiate another conversion of the channels, send another TRIGGER.ADC command. ADC Custom Channel Sequencer The device uses a custom channel sequencer to control the multiplexer of the ADC. The ADC sequencer allows the user to specify which channels are converted. The sequencer consists of 16 indexed slots with programmable start and stop index fields to configure the start and stop conversion points. In direct-mode conversion, the ADC converts from the start index to the stop index once and then stops. In auto-mode conversion, the ADC converts from the start to stop index repeatedly until the ADC is stopped. shows the indexed custom channel sequence slots available in the device. ADC MUX Control lists the ADC input channel assignments for the sequencer. Indexed Custom Channel Sequence CCS POINTER CHANNEL CONV_RATE RANGE 0 OFFSET 2560 Hz VREF 1 AIN0 Programmable Programmable 2 AIN1 Programmable Programmable 3 TEMP 2560 Hz VREF 4 SD0 (VREF) 2560 Hz VREF 5 SD1 (PVDD) 2560 Hz VREF 6 SD2 (VDD) 2560 Hz VREF 7 SD3 (ZTAT) 2560 Hz VREF 8 SD4 (VOUT) 2560 Hz 2 × VREF 9-15 GND 2560 Hz VREF Use the ADC_INDEX_CFG register to select the channels. The order of the channels is fixed and shown in . Then, use ADC_INDEX_CFG.START and ADC_INDEX_CFG.STOP to select the range of indices to convert. If these two values are the same, then the ADC only converts a single channel. If the START and STOP values are different, then the ADC cycles through the corresponding indices. By default, all channels are configured to be converted; START = 0 and STOP = 8. If the AIN1 channel is not configured as an ADC input, then the result for this channel is 0x000. The minimum time for a conversion is still allotted to AIN1 if the channel is within the START and STOP range. If START is configured to be greater than STOP, then the device interprets the conversion sequence as if START = STOP. In direct mode, each selected channel in the ADC_INDEX_CFG register is converted once per TRIGGER.ADC command. In auto mode, each channel selected in the ADC_INDEX_CFG register is converted once; after the last channel, the loop is repeated as long as the ADC is enabled. In auto mode, writing to TRIGGER.ADC = 1 starts the conversions. Writing TRIGGER.ADC = 0 disables the ADC after the current channel being converted finishes. In direct mode, writing TRIGGER.ADC = 1 starts the sequence. When the sequence ends, then TRIGGER.ADC is self-cleared. A minimum of 20 clock cycles is required to perform one conversion. The ADC clock is derived from the internal oscillator and divided by 16, which gives an ADC clock frequency of 1.2288 MHz / 16 = 76.8 kHz, for a clock period = 13.02 μs. Each of the internal nodes has a fixed conversion rate. Pins AIN0 and AIN1 have programmable conversion rates (see also the ADC_CFG register). Pins AIN0 and AIN1 also have a configurable range. The input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit. If any ADC configuration bits are changed, the following sequence is recommended: Disable the ADC Wait for ADC_BUSY to go low Change the configuration Restart the conversions ADC_BUSY can be monitored in the GEN_STATUS register. If the ADC is configured for direct mode (ADC_CFG.DIRECT_MODE = 1), then after setting the desired channels to convert, write a 1 to TRIGGER.ADC. This bit is self-cleared when the sequence is finished converting. This command converts all the selected channels once. To initiate another conversion of the channels, send another TRIGGER.ADC command. The device uses a custom channel sequencer to control the multiplexer of the ADC. The ADC sequencer allows the user to specify which channels are converted. The sequencer consists of 16 indexed slots with programmable start and stop index fields to configure the start and stop conversion points. In direct-mode conversion, the ADC converts from the start index to the stop index once and then stops. In auto-mode conversion, the ADC converts from the start to stop index repeatedly until the ADC is stopped. shows the indexed custom channel sequence slots available in the device. ADC MUX Control lists the ADC input channel assignments for the sequencer. Indexed Custom Channel Sequence CCS POINTER CHANNEL CONV_RATE RANGE 0 OFFSET 2560 Hz VREF 1 AIN0 Programmable Programmable 2 AIN1 Programmable Programmable 3 TEMP 2560 Hz VREF 4 SD0 (VREF) 2560 Hz VREF 5 SD1 (PVDD) 2560 Hz VREF 6 SD2 (VDD) 2560 Hz VREF 7 SD3 (ZTAT) 2560 Hz VREF 8 SD4 (VOUT) 2560 Hz 2 × VREF 9-15 GND 2560 Hz VREF Use the ADC_INDEX_CFG register to select the channels. The order of the channels is fixed and shown in . Then, use ADC_INDEX_CFG.START and ADC_INDEX_CFG.STOP to select the range of indices to convert. If these two values are the same, then the ADC only converts a single channel. If the START and STOP values are different, then the ADC cycles through the corresponding indices. By default, all channels are configured to be converted; START = 0 and STOP = 8. If the AIN1 channel is not configured as an ADC input, then the result for this channel is 0x000. The minimum time for a conversion is still allotted to AIN1 if the channel is within the START and STOP range. If START is configured to be greater than STOP, then the device interprets the conversion sequence as if START = STOP. In direct mode, each selected channel in the ADC_INDEX_CFG register is converted once per TRIGGER.ADC command. In auto mode, each channel selected in the ADC_INDEX_CFG register is converted once; after the last channel, the loop is repeated as long as the ADC is enabled. In auto mode, writing to TRIGGER.ADC = 1 starts the conversions. Writing TRIGGER.ADC = 0 disables the ADC after the current channel being converted finishes. In direct mode, writing TRIGGER.ADC = 1 starts the sequence. When the sequence ends, then TRIGGER.ADC is self-cleared. A minimum of 20 clock cycles is required to perform one conversion. The ADC clock is derived from the internal oscillator and divided by 16, which gives an ADC clock frequency of 1.2288 MHz / 16 = 76.8 kHz, for a clock period = 13.02 μs. Each of the internal nodes has a fixed conversion rate. Pins AIN0 and AIN1 have programmable conversion rates (see also the ADC_CFG register). Pins AIN0 and AIN1 also have a configurable range. The input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit. If any ADC configuration bits are changed, the following sequence is recommended: Disable the ADC Wait for ADC_BUSY to go low Change the configuration Restart the conversions ADC_BUSY can be monitored in the GEN_STATUS register. If the ADC is configured for direct mode (ADC_CFG.DIRECT_MODE = 1), then after setting the desired channels to convert, write a 1 to TRIGGER.ADC. This bit is self-cleared when the sequence is finished converting. This command converts all the selected channels once. To initiate another conversion of the channels, send another TRIGGER.ADC command. The device uses a custom channel sequencer to control the multiplexer of the ADC. The ADC sequencer allows the user to specify which channels are converted. The sequencer consists of 16 indexed slots with programmable start and stop index fields to configure the start and stop conversion points.In direct-mode conversion, the ADC converts from the start index to the stop index once and then stops. In auto-mode conversion, the ADC converts from the start to stop index repeatedly until the ADC is stopped. shows the indexed custom channel sequence slots available in the device. ADC MUX Control ADC MUX Control lists the ADC input channel assignments for the sequencer. Indexed Custom Channel Sequence CCS POINTER CHANNEL CONV_RATE RANGE 0 OFFSET 2560 Hz VREF 1 AIN0 Programmable Programmable 2 AIN1 Programmable Programmable 3 TEMP 2560 Hz VREF 4 SD0 (VREF) 2560 Hz VREF 5 SD1 (PVDD) 2560 Hz VREF 6 SD2 (VDD) 2560 Hz VREF 7 SD3 (ZTAT) 2560 Hz VREF 8 SD4 (VOUT) 2560 Hz 2 × VREF 9-15 GND 2560 Hz VREF Indexed Custom Channel Sequence CCS POINTER CHANNEL CONV_RATE RANGE 0 OFFSET 2560 Hz VREF 1 AIN0 Programmable Programmable 2 AIN1 Programmable Programmable 3 TEMP 2560 Hz VREF 4 SD0 (VREF) 2560 Hz VREF 5 SD1 (PVDD) 2560 Hz VREF 6 SD2 (VDD) 2560 Hz VREF 7 SD3 (ZTAT) 2560 Hz VREF 8 SD4 (VOUT) 2560 Hz 2 × VREF 9-15 GND 2560 Hz VREF CCS POINTER CHANNEL CONV_RATE RANGE CCS POINTER CHANNEL CONV_RATE RANGE CCS POINTERCHANNELCONV_RATERANGE 0 OFFSET 2560 Hz VREF 1 AIN0 Programmable Programmable 2 AIN1 Programmable Programmable 3 TEMP 2560 Hz VREF 4 SD0 (VREF) 2560 Hz VREF 5 SD1 (PVDD) 2560 Hz VREF 6 SD2 (VDD) 2560 Hz VREF 7 SD3 (ZTAT) 2560 Hz VREF 8 SD4 (VOUT) 2560 Hz 2 × VREF 9-15 GND 2560 Hz VREF 0 OFFSET 2560 Hz VREF 0OFFSET2560 HzVREF 1 AIN0 Programmable Programmable 1AIN0ProgrammableProgrammable 2 AIN1 Programmable Programmable 2AIN1ProgrammableProgrammable 3 TEMP 2560 Hz VREF 3TEMP2560 HzVREF 4 SD0 (VREF) 2560 Hz VREF 4SD0 (VREF)2560 HzVREF 5 SD1 (PVDD) 2560 Hz VREF 5SD1 (PVDD)2560 HzVREF 6 SD2 (VDD) 2560 Hz VREF 6SD2 (VDD)2560 HzVREF 7 SD3 (ZTAT) 2560 Hz VREF 7SD3 (ZTAT)2560 HzVREF 8 SD4 (VOUT) 2560 Hz 2 × VREF 8SD4 (VOUT)2560 Hz 2 × VREF 2 × VREF 9-15 GND 2560 Hz VREF 9-15GND2560 HzVREFUse the ADC_INDEX_CFG register to select the channels. The order of the channels is fixed and shown in . Then, use ADC_INDEX_CFG.START and ADC_INDEX_CFG.STOP to select the range of indices to convert. If these two values are the same, then the ADC only converts a single channel. If the START and STOP values are different, then the ADC cycles through the corresponding indices. By default, all channels are configured to be converted; START = 0 and STOP = 8. If the AIN1 channel is not configured as an ADC input, then the result for this channel is 0x000. The minimum time for a conversion is still allotted to AIN1 if the channel is within the START and STOP range. If START is configured to be greater than STOP, then the device interprets the conversion sequence as if START = STOP.In direct mode, each selected channel in the ADC_INDEX_CFG register is converted once per TRIGGER.ADC command. In auto mode, each channel selected in the ADC_INDEX_CFG register is converted once; after the last channel, the loop is repeated as long as the ADC is enabled. In auto mode, writing to TRIGGER.ADC = 1 starts the conversions. Writing TRIGGER.ADC = 0 disables the ADC after the current channel being converted finishes. In direct mode, writing TRIGGER.ADC = 1 starts the sequence. When the sequence ends, then TRIGGER.ADC is self-cleared.A minimum of 20 clock cycles is required to perform one conversion. The ADC clock is derived from the internal oscillator and divided by 16, which gives an ADC clock frequency of 1.2288 MHz / 16 = 76.8 kHz, for a clock period = 13.02 μs.Each of the internal nodes has a fixed conversion rate. Pins AIN0 and AIN1 have programmable conversion rates (see also the ADC_CFG register). Pins AIN0 and AIN1 also have a configurable range. The input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit. The input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit.If any ADC configuration bits are changed, the following sequence is recommended: Disable the ADC Wait for ADC_BUSY to go low Change the configuration Restart the conversions Disable the ADCWait for ADC_BUSY to go lowChange the configurationRestart the conversionsADC_BUSY can be monitored in the GEN_STATUS register.If the ADC is configured for direct mode (ADC_CFG.DIRECT_MODE = 1), then after setting the desired channels to convert, write a 1 to TRIGGER.ADC. This bit is self-cleared when the sequence is finished converting. This command converts all the selected channels once. To initiate another conversion of the channels, send another TRIGGER.ADC command. ADC Synchronization The trigger signal must be generated for the ADC to exit the idle state and start conversions. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode, use the GEN_STATUS.ADC_BUSY bit to determine when a direct-mode conversion is complete, and the ADC has returned to the idle state. Similarly, monitor the TRIGGER.ADC bit to see if the ADC has returned to the idle state. ADC Synchronization The trigger signal must be generated for the ADC to exit the idle state and start conversions. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode, use the GEN_STATUS.ADC_BUSY bit to determine when a direct-mode conversion is complete, and the ADC has returned to the idle state. Similarly, monitor the TRIGGER.ADC bit to see if the ADC has returned to the idle state. The trigger signal must be generated for the ADC to exit the idle state and start conversions. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode, use the GEN_STATUS.ADC_BUSY bit to determine when a direct-mode conversion is complete, and the ADC has returned to the idle state. Similarly, monitor the TRIGGER.ADC bit to see if the ADC has returned to the idle state. The trigger signal must be generated for the ADC to exit the idle state and start conversions. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation.In direct-mode, use the GEN_STATUS.ADC_BUSY bit to determine when a direct-mode conversion is complete, and the ADC has returned to the idle state. Similarly, monitor the TRIGGER.ADC bit to see if the ADC has returned to the idle state. ADC Offset Calibration Channel 0 of the CCS pointer is named OFFSET. The OFFSET channel is used to calibrate and improve the ADC offset performance. Convert the OFFSET channel, and use the result as a calibration for the ADC offset in subsequent measurements. This ADC channel samples VREF / 2 and compares this result against 7FFh as a measure of the ADC offset. The data rate for the ADC measuring this channel is 2560 Hz. The ADC conversion for the OFFSET channel is subtracted from 7FFh and the resulting value is stored in ADC_OFFSET (28h). The offset can be positive or negative; therefore, the value is stored in 2’s complement notation. With the subtraction from 7FFh, ADC_OFFSET is the negative of the offset. This value is subtracted from conversions of the ADC by default. For direct measurements of the ADC, set ADC_BYP.OFST_BYP_EN to 1 to enable the offset bypass; see . ADC Offset Calibration Channel 0 of the CCS pointer is named OFFSET. The OFFSET channel is used to calibrate and improve the ADC offset performance. Convert the OFFSET channel, and use the result as a calibration for the ADC offset in subsequent measurements. This ADC channel samples VREF / 2 and compares this result against 7FFh as a measure of the ADC offset. The data rate for the ADC measuring this channel is 2560 Hz. The ADC conversion for the OFFSET channel is subtracted from 7FFh and the resulting value is stored in ADC_OFFSET (28h). The offset can be positive or negative; therefore, the value is stored in 2’s complement notation. With the subtraction from 7FFh, ADC_OFFSET is the negative of the offset. This value is subtracted from conversions of the ADC by default. For direct measurements of the ADC, set ADC_BYP.OFST_BYP_EN to 1 to enable the offset bypass; see . Channel 0 of the CCS pointer is named OFFSET. The OFFSET channel is used to calibrate and improve the ADC offset performance. Convert the OFFSET channel, and use the result as a calibration for the ADC offset in subsequent measurements. This ADC channel samples VREF / 2 and compares this result against 7FFh as a measure of the ADC offset. The data rate for the ADC measuring this channel is 2560 Hz. The ADC conversion for the OFFSET channel is subtracted from 7FFh and the resulting value is stored in ADC_OFFSET (28h). The offset can be positive or negative; therefore, the value is stored in 2’s complement notation. With the subtraction from 7FFh, ADC_OFFSET is the negative of the offset. This value is subtracted from conversions of the ADC by default. For direct measurements of the ADC, set ADC_BYP.OFST_BYP_EN to 1 to enable the offset bypass; see . Channel 0 of the CCS pointer is named OFFSET. The OFFSET channel is used to calibrate and improve the ADC offset performance. Convert the OFFSET channel, and use the result as a calibration for the ADC offset in subsequent measurements.This ADC channel samples VREF / 2 and compares this result against 7FFh as a measure of the ADC offset. The data rate for the ADC measuring this channel is 2560 Hz. The ADC conversion for the OFFSET channel is subtracted from 7FFh and the resulting value is stored in ADC_OFFSET (28h). The offset can be positive or negative; therefore, the value is stored in 2’s complement notation.With the subtraction from 7FFh, ADC_OFFSET is the negative of the offset. This value is subtracted from conversions of the ADC by default. For direct measurements of the ADC, set ADC_BYP.OFST_BYP_EN to 1 to enable the offset bypass; see . External Monitoring Inputs The AFEx82H1 have two analog inputs for external voltage sensing. Channels 1 and 2 for the CCS pointer are for external monitoring inputs that can be measured by pins AIN0 and AIN1, respectively. The input range for the analog inputs is configurable to either 0 V to 1.25 V or 0 V to 2.5 V. The analog inputs conversion values are stored in straight binary format in the ADC registers. The ADC resolution can be computed by : 1   L S B = V R A N G E 2 12 where VRANGE = 2.5 V for the 0‑V to 2.5‑V input range or 1.25 V for the 0‑V to 1.25‑V input range. and detail the transfer characteristics. ADC Transfer Characteristics Transfer Characteristics INPUT VOLTAGE CODE DESCRIPTION IDEAL OUTPUT CODE ≤1 LSB NFSC Negative full-scale code 000 1 LSB to 2 LSB NFSC + 1 Negative full-scale code plus 1 001 (VRANGE / 2) to (VRANGE / 2) + 1 LSB MC Midcode 800 (VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSB MC + 1 Midcode plus 1 801 ≥ VRANGE – 1 LSB PFSC Positive full-scale code FFF For these external monitoring inputs, the ADC is configurable for both data rate and voltage range. The data rate is set to either 640 Hz, 1280 Hz, 2560 Hz, or 3840 Hz with the ADC_CFG.CONV_RATE bits. The range of the ADC measurement is set with the ADC_CFG.AIN_RANGE bit. The ADC range is 2 × VREF when the bit = 0; the ADC range is VREF when the bit = 1. When the ADC conversion is completed for AIN0 and AIN1, the resulting ADC data are stored in the ADC_AIN0.DATA and ADC_AIN1.DATA bits at 24h and 25h of the register map. If the external monitoring inputs are not used, connect the AIN0 and AIN1 pins to GND through a 1-kΩ resistor. External Monitoring Inputs The AFEx82H1 have two analog inputs for external voltage sensing. Channels 1 and 2 for the CCS pointer are for external monitoring inputs that can be measured by pins AIN0 and AIN1, respectively. The input range for the analog inputs is configurable to either 0 V to 1.25 V or 0 V to 2.5 V. The analog inputs conversion values are stored in straight binary format in the ADC registers. The ADC resolution can be computed by : 1   L S B = V R A N G E 2 12 where VRANGE = 2.5 V for the 0‑V to 2.5‑V input range or 1.25 V for the 0‑V to 1.25‑V input range. and detail the transfer characteristics. ADC Transfer Characteristics Transfer Characteristics INPUT VOLTAGE CODE DESCRIPTION IDEAL OUTPUT CODE ≤1 LSB NFSC Negative full-scale code 000 1 LSB to 2 LSB NFSC + 1 Negative full-scale code plus 1 001 (VRANGE / 2) to (VRANGE / 2) + 1 LSB MC Midcode 800 (VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSB MC + 1 Midcode plus 1 801 ≥ VRANGE – 1 LSB PFSC Positive full-scale code FFF For these external monitoring inputs, the ADC is configurable for both data rate and voltage range. The data rate is set to either 640 Hz, 1280 Hz, 2560 Hz, or 3840 Hz with the ADC_CFG.CONV_RATE bits. The range of the ADC measurement is set with the ADC_CFG.AIN_RANGE bit. The ADC range is 2 × VREF when the bit = 0; the ADC range is VREF when the bit = 1. When the ADC conversion is completed for AIN0 and AIN1, the resulting ADC data are stored in the ADC_AIN0.DATA and ADC_AIN1.DATA bits at 24h and 25h of the register map. If the external monitoring inputs are not used, connect the AIN0 and AIN1 pins to GND through a 1-kΩ resistor. The AFEx82H1 have two analog inputs for external voltage sensing. Channels 1 and 2 for the CCS pointer are for external monitoring inputs that can be measured by pins AIN0 and AIN1, respectively. The input range for the analog inputs is configurable to either 0 V to 1.25 V or 0 V to 2.5 V. The analog inputs conversion values are stored in straight binary format in the ADC registers. The ADC resolution can be computed by : 1   L S B = V R A N G E 2 12 where VRANGE = 2.5 V for the 0‑V to 2.5‑V input range or 1.25 V for the 0‑V to 1.25‑V input range. and detail the transfer characteristics. ADC Transfer Characteristics Transfer Characteristics INPUT VOLTAGE CODE DESCRIPTION IDEAL OUTPUT CODE ≤1 LSB NFSC Negative full-scale code 000 1 LSB to 2 LSB NFSC + 1 Negative full-scale code plus 1 001 (VRANGE / 2) to (VRANGE / 2) + 1 LSB MC Midcode 800 (VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSB MC + 1 Midcode plus 1 801 ≥ VRANGE – 1 LSB PFSC Positive full-scale code FFF For these external monitoring inputs, the ADC is configurable for both data rate and voltage range. The data rate is set to either 640 Hz, 1280 Hz, 2560 Hz, or 3840 Hz with the ADC_CFG.CONV_RATE bits. The range of the ADC measurement is set with the ADC_CFG.AIN_RANGE bit. The ADC range is 2 × VREF when the bit = 0; the ADC range is VREF when the bit = 1. When the ADC conversion is completed for AIN0 and AIN1, the resulting ADC data are stored in the ADC_AIN0.DATA and ADC_AIN1.DATA bits at 24h and 25h of the register map. If the external monitoring inputs are not used, connect the AIN0 and AIN1 pins to GND through a 1-kΩ resistor. The AFEx82H1 have two analog inputs for external voltage sensing. Channels 1 and 2 for the CCS pointer are for external monitoring inputs that can be measured by pins AIN0 and AIN1, respectively. The input range for the analog inputs is configurable to either 0 V to 1.25 V or 0 V to 2.5 V. The analog inputs conversion values are stored in straight binary format in the ADC registers. The ADC resolution can be computed by :AFEx82H1 1   L S B = V R A N G E 2 12 1   L S B = V R A N G E 2 12 1   L S B = V R A N G E 2 12 1 LSB= V R A N G E 2 12 V R A N G E V R A N G E V V R A N G E RANGE 2 12 2 12 2 2 12 12where VRANGE = 2.5 V for the 0‑V to 2.5‑V input range or 1.25 V for the 0‑V to 1.25‑V input range. VRANGE = 2.5 V for the 0‑V to 2.5‑V input range or 1.25 V for the 0‑V to 1.25‑V input range.RANGE and detail the transfer characteristics. ADC Transfer Characteristics ADC Transfer Characteristics Transfer Characteristics INPUT VOLTAGE CODE DESCRIPTION IDEAL OUTPUT CODE ≤1 LSB NFSC Negative full-scale code 000 1 LSB to 2 LSB NFSC + 1 Negative full-scale code plus 1 001 (VRANGE / 2) to (VRANGE / 2) + 1 LSB MC Midcode 800 (VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSB MC + 1 Midcode plus 1 801 ≥ VRANGE – 1 LSB PFSC Positive full-scale code FFF Transfer Characteristics INPUT VOLTAGE CODE DESCRIPTION IDEAL OUTPUT CODE ≤1 LSB NFSC Negative full-scale code 000 1 LSB to 2 LSB NFSC + 1 Negative full-scale code plus 1 001 (VRANGE / 2) to (VRANGE / 2) + 1 LSB MC Midcode 800 (VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSB MC + 1 Midcode plus 1 801 ≥ VRANGE – 1 LSB PFSC Positive full-scale code FFF INPUT VOLTAGE CODE DESCRIPTION IDEAL OUTPUT CODE INPUT VOLTAGE CODE DESCRIPTION IDEAL OUTPUT CODE INPUT VOLTAGECODEDESCRIPTIONIDEAL OUTPUT CODE ≤1 LSB NFSC Negative full-scale code 000 1 LSB to 2 LSB NFSC + 1 Negative full-scale code plus 1 001 (VRANGE / 2) to (VRANGE / 2) + 1 LSB MC Midcode 800 (VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSB MC + 1 Midcode plus 1 801 ≥ VRANGE – 1 LSB PFSC Positive full-scale code FFF ≤1 LSB NFSC Negative full-scale code 000 ≤1 LSBNFSCNegative full-scale code000 1 LSB to 2 LSB NFSC + 1 Negative full-scale code plus 1 001 1 LSB to 2 LSBNFSC + 1Negative full-scale code plus 1001 (VRANGE / 2) to (VRANGE / 2) + 1 LSB MC Midcode 800 (VRANGE / 2) to (VRANGE / 2) + 1 LSBRANGERANGEMCMidcode800 (VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSB MC + 1 Midcode plus 1 801 (VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSBRANGERANGEMC + 1Midcode plus 1801 ≥ VRANGE – 1 LSB PFSC Positive full-scale code FFF ≥ VRANGE – 1 LSBRANGEPFSCPositive full-scale codeFFFFor these external monitoring inputs, the ADC is configurable for both data rate and voltage range. The data rate is set to either 640 Hz, 1280 Hz, 2560 Hz, or 3840 Hz with the ADC_CFG.CONV_RATE bits. The range of the ADC measurement is set with the ADC_CFG.AIN_RANGE bit. The ADC range is 2 × VREF when the bit = 0; the ADC range is VREF when the bit = 1.When the ADC conversion is completed for AIN0 and AIN1, the resulting ADC data are stored in the ADC_AIN0.DATA and ADC_AIN1.DATA bits at 24h and 25h of the register map.If the external monitoring inputs are not used, connect the AIN0 and AIN1 pins to GND through a 1-kΩ resistor. Temperature Sensor Channel 3 of the CCS is used to measure the die temperature of the device. The ADC measures an internal temperature sensor that measures a voltage complementary to the absolute temperature (CTAT). This CTAT voltage has a negative temperature coefficient. The ADC converts this voltage at a data rate of 2560 Hz. When the ADC conversion is completed, the data are found in the ADC_TEMP.DATA bits (address 26h). The relationship between the ambient temperature and the ADC code is shown in #GUID-A307B900-C147-485E-AF3B-AFFF3E5B4EBD/GUID-09CDF47B-A831-42BA-B93C-B59905D9CECB: ADC Code = 2681   - 11 × T A ( ° C ) Temperature Sensor Channel 3 of the CCS is used to measure the die temperature of the device. The ADC measures an internal temperature sensor that measures a voltage complementary to the absolute temperature (CTAT). This CTAT voltage has a negative temperature coefficient. The ADC converts this voltage at a data rate of 2560 Hz. When the ADC conversion is completed, the data are found in the ADC_TEMP.DATA bits (address 26h). The relationship between the ambient temperature and the ADC code is shown in #GUID-A307B900-C147-485E-AF3B-AFFF3E5B4EBD/GUID-09CDF47B-A831-42BA-B93C-B59905D9CECB: ADC Code = 2681   - 11 × T A ( ° C ) Channel 3 of the CCS is used to measure the die temperature of the device. The ADC measures an internal temperature sensor that measures a voltage complementary to the absolute temperature (CTAT). This CTAT voltage has a negative temperature coefficient. The ADC converts this voltage at a data rate of 2560 Hz. When the ADC conversion is completed, the data are found in the ADC_TEMP.DATA bits (address 26h). The relationship between the ambient temperature and the ADC code is shown in #GUID-A307B900-C147-485E-AF3B-AFFF3E5B4EBD/GUID-09CDF47B-A831-42BA-B93C-B59905D9CECB: ADC Code = 2681   - 11 × T A ( ° C ) Channel 3 of the CCS is used to measure the die temperature of the device. The ADC measures an internal temperature sensor that measures a voltage complementary to the absolute temperature (CTAT). This CTAT voltage has a negative temperature coefficient. The ADC converts this voltage at a data rate of 2560 Hz. When the ADC conversion is completed, the data are found in the ADC_TEMP.DATA bits (address 26h).The relationship between the ambient temperature and the ADC code is shown in #GUID-A307B900-C147-485E-AF3B-AFFF3E5B4EBD/GUID-09CDF47B-A831-42BA-B93C-B59905D9CECB:#GUID-A307B900-C147-485E-AF3B-AFFF3E5B4EBD/GUID-09CDF47B-A831-42BA-B93C-B59905D9CECB ADC Code = 2681   - 11 × T A ( ° C ) ADC Code = 2681   - 11 × T A ( ° C ) ADC Code = 2681   - 11 × T A ( ° C ) ADC Code=2681 -11× T A T T A A(°C) Self-Diagnostic Multiplexer In addition to the ADC offset, the two external monitoring inputs, and the temperature sensor, the ADC of the AFEx82H1 has five other internal inputs to monitor the reference voltage, the power supplies, a static voltage, and the DAC output. These five voltages measurements are part of the self-diagnostic multiplexer (SD0 to SD4) measurements of the ADC, and are reported in the ADC_SD_MUX register at 27h; see also . Channel 4 (SD0) measures the reference voltage of the device. The ADC measures the reference voltage through a resistor divider (divide by two). Be aware that all ADC measurements are a function of the reference; using SD0 to measure the reference is not revealing as a diagnostic measurement. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 5 (SD1) measures the PVDD power supply of the device. The ADC measures the PVDD voltage through a resistor divider (divide by six). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 6 (SD2) measures the VDD power supply of the device. When channel 6 is selected, the ADC measures the VDD voltage through a resistor divider (divide by 2). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 7 (SD3) is a ZTAT (zero temperature coefficient) voltage. This internal voltage is nominally 0.6 V with a low temperature drift and does not depend on the reference voltage. An ADC measurement of ZTAT voltage can be useful to determine the state of the reference voltage. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 8 (SD4) measures the VOUT of the DAC. The ADC measures the VOUT voltage through a resistor divider (divide by two). The data rate for this conversion is 2560 Hz and the range of the ADC is set to 2 × VREF. Self-Diagnostic Multiplexer In addition to the ADC offset, the two external monitoring inputs, and the temperature sensor, the ADC of the AFEx82H1 has five other internal inputs to monitor the reference voltage, the power supplies, a static voltage, and the DAC output. These five voltages measurements are part of the self-diagnostic multiplexer (SD0 to SD4) measurements of the ADC, and are reported in the ADC_SD_MUX register at 27h; see also . Channel 4 (SD0) measures the reference voltage of the device. The ADC measures the reference voltage through a resistor divider (divide by two). Be aware that all ADC measurements are a function of the reference; using SD0 to measure the reference is not revealing as a diagnostic measurement. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 5 (SD1) measures the PVDD power supply of the device. The ADC measures the PVDD voltage through a resistor divider (divide by six). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 6 (SD2) measures the VDD power supply of the device. When channel 6 is selected, the ADC measures the VDD voltage through a resistor divider (divide by 2). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 7 (SD3) is a ZTAT (zero temperature coefficient) voltage. This internal voltage is nominally 0.6 V with a low temperature drift and does not depend on the reference voltage. An ADC measurement of ZTAT voltage can be useful to determine the state of the reference voltage. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 8 (SD4) measures the VOUT of the DAC. The ADC measures the VOUT voltage through a resistor divider (divide by two). The data rate for this conversion is 2560 Hz and the range of the ADC is set to 2 × VREF. In addition to the ADC offset, the two external monitoring inputs, and the temperature sensor, the ADC of the AFEx82H1 has five other internal inputs to monitor the reference voltage, the power supplies, a static voltage, and the DAC output. These five voltages measurements are part of the self-diagnostic multiplexer (SD0 to SD4) measurements of the ADC, and are reported in the ADC_SD_MUX register at 27h; see also . Channel 4 (SD0) measures the reference voltage of the device. The ADC measures the reference voltage through a resistor divider (divide by two). Be aware that all ADC measurements are a function of the reference; using SD0 to measure the reference is not revealing as a diagnostic measurement. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 5 (SD1) measures the PVDD power supply of the device. The ADC measures the PVDD voltage through a resistor divider (divide by six). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 6 (SD2) measures the VDD power supply of the device. When channel 6 is selected, the ADC measures the VDD voltage through a resistor divider (divide by 2). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 7 (SD3) is a ZTAT (zero temperature coefficient) voltage. This internal voltage is nominally 0.6 V with a low temperature drift and does not depend on the reference voltage. An ADC measurement of ZTAT voltage can be useful to determine the state of the reference voltage. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 8 (SD4) measures the VOUT of the DAC. The ADC measures the VOUT voltage through a resistor divider (divide by two). The data rate for this conversion is 2560 Hz and the range of the ADC is set to 2 × VREF. In addition to the ADC offset, the two external monitoring inputs, and the temperature sensor, the ADC of the AFEx82H1 has five other internal inputs to monitor the reference voltage, the power supplies, a static voltage, and the DAC output. These five voltages measurements are part of the self-diagnostic multiplexer (SD0 to SD4) measurements of the ADC, and are reported in the ADC_SD_MUX register at 27h; see also .AFEx82H1Channel 4 (SD0) measures the reference voltage of the device. The ADC measures the reference voltage through a resistor divider (divide by two). Be aware that all ADC measurements are a function of the reference; using SD0 to measure the reference is not revealing as a diagnostic measurement. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF.Channel 5 (SD1) measures the PVDD power supply of the device. The ADC measures the PVDD voltage through a resistor divider (divide by six). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF.Channel 6 (SD2) measures the VDD power supply of the device. When channel 6 is selected, the ADC measures the VDD voltage through a resistor divider (divide by 2). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF.Channel 7 (SD3) is a ZTAT (zero temperature coefficient) voltage. This internal voltage is nominally 0.6 V with a low temperature drift and does not depend on the reference voltage. An ADC measurement of ZTAT voltage can be useful to determine the state of the reference voltage. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF.Channel 8 (SD4) measures the VOUT of the DAC. The ADC measures the VOUT voltage through a resistor divider (divide by two). The data rate for this conversion is 2560 Hz and the range of the ADC is set to 2 × VREF. and the range of the ADC is set to 2 × VREF ADC Bypass To test the offset, modify the ADC data path by programming the bypass data register, ADC_BYP.DATA (2Eh). This read/write register is used in two different ways. First, by setting the ADC_BYP.OFST_BYP_EN to 1, this bypass data register is used as a substitute for the ADC_OFFSET. However, if the ADC_BYP.DATA data must be stored in the ADC_OFFSET register, use the second method. Second, the ADC_BYP.DATA is used to set a known value into the ADC readback register of the channel being converted. Write the desired data into ADC_BYP.DATA, set the ADC_BYP.DATA_BYP_EN bit, and convert the selected channel. When ADC_BYP.DATA_BYP_EN bit is set to 1, the ADC conversion is bypassed, and the value of ADC_BYP.DATA is written into the selected ADC channel readback register. This setting is used to test the alarm settings of the ADC. When the ADC bypass is unused, set the ADC_BYP.DATA to 000h. shows the ADC bypass data flow. ADC Bypass Data Flow ADC Bypass To test the offset, modify the ADC data path by programming the bypass data register, ADC_BYP.DATA (2Eh). This read/write register is used in two different ways. First, by setting the ADC_BYP.OFST_BYP_EN to 1, this bypass data register is used as a substitute for the ADC_OFFSET. However, if the ADC_BYP.DATA data must be stored in the ADC_OFFSET register, use the second method. Second, the ADC_BYP.DATA is used to set a known value into the ADC readback register of the channel being converted. Write the desired data into ADC_BYP.DATA, set the ADC_BYP.DATA_BYP_EN bit, and convert the selected channel. When ADC_BYP.DATA_BYP_EN bit is set to 1, the ADC conversion is bypassed, and the value of ADC_BYP.DATA is written into the selected ADC channel readback register. This setting is used to test the alarm settings of the ADC. When the ADC bypass is unused, set the ADC_BYP.DATA to 000h. shows the ADC bypass data flow. ADC Bypass Data Flow To test the offset, modify the ADC data path by programming the bypass data register, ADC_BYP.DATA (2Eh). This read/write register is used in two different ways. First, by setting the ADC_BYP.OFST_BYP_EN to 1, this bypass data register is used as a substitute for the ADC_OFFSET. However, if the ADC_BYP.DATA data must be stored in the ADC_OFFSET register, use the second method. Second, the ADC_BYP.DATA is used to set a known value into the ADC readback register of the channel being converted. Write the desired data into ADC_BYP.DATA, set the ADC_BYP.DATA_BYP_EN bit, and convert the selected channel. When ADC_BYP.DATA_BYP_EN bit is set to 1, the ADC conversion is bypassed, and the value of ADC_BYP.DATA is written into the selected ADC channel readback register. This setting is used to test the alarm settings of the ADC. When the ADC bypass is unused, set the ADC_BYP.DATA to 000h. shows the ADC bypass data flow. ADC Bypass Data Flow To test the offset, modify the ADC data path by programming the bypass data register, ADC_BYP.DATA (2Eh). This read/write register is used in two different ways.First, by setting the ADC_BYP.OFST_BYP_EN to 1, this bypass data register is used as a substitute for the ADC_OFFSET. However, if the ADC_BYP.DATA data must be stored in the ADC_OFFSET register, use the second method.Second, the ADC_BYP.DATA is used to set a known value into the ADC readback register of the channel being converted. Write the desired data into ADC_BYP.DATA, set the ADC_BYP.DATA_BYP_EN bit, and convert the selected channel. When ADC_BYP.DATA_BYP_EN bit is set to 1, the ADC conversion is bypassed, and the value of ADC_BYP.DATA is written into the selected ADC channel readback register. This setting is used to test the alarm settings of the ADC.When the ADC bypass is unused, set the ADC_BYP.DATA to 000h. shows the ADC bypass data flow. ADC Bypass Data Flow ADC Bypass Data Flow Programmable Out-of-Range Alarms The AFEx82H1 are capable of continuously analyzing the supplies, external ADC inputs, DAC output voltage, reference, internal temperature, and other internal signals for normal operation. Normal operation for the conversion results is established through the lower- and upper-threshold registers. When any of the monitored inputs are out of the specified range, the corresponding alarm bit in the alarm status registers is set. The alarm bits in the alarm status registers are latched. The alarm bits are referred to as being latched because the alarm bits remain set until read by software. This design makes sure that out-of-limit events cannot be missed if the software is polling the device periodically. All bits are cleared when reading the alarm status registers, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle. When the alarm event is cleared, the DAC is reloaded with the contents of the DAC active registers, which allows the DAC outputs to return to the previous operating point without any additional commands All alarms can be used to generate a hardware interrupt signal on the ALARM pin; see also . In addition, describes how the alarm action can be individually configured for each alarm. Alarm-Based Interrupts One or more of the available alarms can be set to activate the ALARM pin. Connect the ALARM pin as an optional hardware interrupt to the host. The host can query the alarm status registers to determine the alarm source upon assertion of the interrupt. Any alarm event activates the pin, as long as the alarm is not masked in the ALARM_STATUS_MASK register. When an alarm event is masked, the occurrence of the event sets the corresponding status bit in the alarm status registers, but does not activate the ALARM pin. The ALARM pin output depends on ALARM_STATUS and ALARM_STATUS_MASK register settings, independent of ALARM_ACT register settings. Alarm Action Configuration Register The AFEx82H1 provides an alarm action configuration register: ALARM_ACT, . Writing to this register selects the device action that automatically occurs for a specific alarm condition. The ALARM_ACT register determines how the main DAC responds to an alarm event from either an ADC conversion on the self-diagnostics channels (AIN0, AIN1, and TEMP), or from a CRC, WDT, VREF, TEMP_HI, or TEMP_LO fault. Only these faults cause a response by the DAC. Any other alarm status events trigger the ALARM pin. There are four options for alarm action. In case different settings are selected for different alarm conditions, the following low-to-high priority is considered when taking action: 0. → No action 1. → DAC CLEAR state 2. → VOUT alarm voltage 3. → VOUT Hi-Z If option 1 is selected when the alarm event occurs, then the DAC is forced to the clear code. This operation is done by controlling the input code to the DAC. If option 2 is selected when the alarm event occurs, then VOUT is forced to the alarm voltage. The alarm voltage is controlled by either pin or register bit. If SPECIAL_CFG.AIN1_ENB = 0, then the AIN1 pin controls alarm polarity. Also, register bit SPECIAL_CFG.ALMV_POL can be used. If either of these signals = 1, then the alarm voltage is high; otherwise, the alarm voltage is low. The SPECIAL_CFG register is only reset with POR, so the user setting remains intact through hardware or software resets. If option 3 is selected when the alarm event occurs, then the VOUT buffer is put into Hi-Z. If multiple events occur, then the highest setting takes precedence. Option 3 has the highest priority. To disable action response to an alarm, set the corresponding bits in ALARM_ACT to 0h. Alarm action response is cleared either when the triggered condition bit resets (behavior depends on whether the fault bit in ALARM_STATUS is sticky or not), or by changing the action configuration to 0h. An alarm action, as configured, executes when an alarm occurs depending on ALARM_STATUS and ALARM_ACT registers. Action response is independent of ALARM_STATUS_MASK settings. Alarm Voltage Generator shows that the alarm voltage is generated independently from the DAC output voltage. The alarm polarity control logic selects the output level of the alarm voltage generator. The alarm action control logic selects between the DAC output and alarm voltage generator output voltages. The alarm action control logic also controls the output buffer Hi-Z switch. Alarm Voltage Generator Architecture During normal operation, the expected VOUT voltage depends on the DAC_CODE. The ADC thresholds for the SD4 (VOUT) diagnostic channel are set around the programmed DAC_CODE. During the alarm condition, if the alarm action changes the VOUT voltage to the alarm voltage, or switches the VOUT buffer into Hi-Z mode, the VOUT voltage no longer depends on the DAC_CODE. In this case, the SD4 (VOUT) diagnostic channel also reports the alarm. To clear this alarm, as long as all other alarm conditions are cleared, set the alarm action to either no action or to the DAC clear code. Applying either alarm action sets the VOUT voltage within the expected ADC thresholds and clears the alarm after the next ADC measurement of the SD4 (VOUT) channel. Give special consideration to the alarm logic during the transient events. When the new DAC_CODE goes beyond the SD4 (VOUT) alarm thresholds with the ADC monitoring the SD4 (VOUT) input in auto mode, the ADC conversion can occur while VOUT settles to a new value. This conversion can trigger a false alarm. There are two ways to prevent this false alarm: Use direct mode and allow VOUT to settle before triggering the next ADC conversion. Set ADC_CFG.FLT_CNT > 0. With this configuration, a single error in SD4 or any other measurement does not cause an alarm condition to be asserted. Temperature Sensor Alarm Function The AFEx82H1 continuously monitor the internal die temperature. In addition to the ADC measurement, the temperature sensor triggers a comparator to show a thermal warning and a thermal error. A thermal warning alarm is set when the temperature exceeds 85°C. Additionally, a thermal error alarm is set when the die temperature exceeds 130°C. The thermal warning and thermal error alarms can be configured to set the ALARM pin and are indicated in the ALARM_STATUS register. These alarms can be masked with the ALARM_MASK register and also be configured to control the DAC output with the ALARM_ACT register. Internal Reference Alarm Function The devices provide out-of-range detection for the reference voltage. When the reference voltage exceeds ±5% of the nominal value, the reference alarm flag (VREF_FLT bit) is set. Make sure that a reference alarm condition has not been issued by the device before powering up the DAC output. ADC Alarm Function The AFEx82H1 provide independent out-of-range detection for each of the ADC inputs. shows the out-of-range detection block. When the measurement is out of range, the corresponding alarm bit is set to flag the out-of-range condition. ADC Out-of-Range Alarm An alarm event is only registered when the monitored signal is out of range for N number of consecutive conversions, where N is configured in the ADC_CFG.FLT_CNT false alarm register settings. If the monitored signal returns to the normal range before N consecutive conversions, an alarm event is not issued. If an ADC input signal is out of range and the alarm is enabled, then the corresponding alarm bit is set to 1. However, the alarm condition is cleared only when the conversion result returns to a value less than the high-limit register setting and greater than the low-limit register setting by the number of codes specified by the hysteresis setting (see ). The hysteresis is a programmable value between 0 LSB to 127 LSB in the ADC_CFG.HYST register. ADC Alarm Hysteresis Fault Detection There are two fields within the ADC_CFG register: FLT_CNT and HYST. These fields are applied to the assertion and deassertion of alarm conditions for all the ADC channels. ADC_CFG.FLT_CNT determines the maximum number of accepted consecutive failures before an alarm condition is reported. For example, if ADC_CFG.FLT_CNT is set for two counts, then three consecutive conversions must be outside of the thresholds to trigger an alarm. Each failure counts towards the FLT_CNT limit even if the failures alternate between high threshold and low threshold. ADC_CFG.HYST sets the hysteresis used by the alarm-detection circuit. After an alarm is triggered, the hysteresis is applied before the alarm condition is released. In the case of the high threshold, the hysteresis is subtracted from the threshold value. In the case of the low threshold limit, the hysteresis is added to the threshold value. Channels AIN0, AIN1, and TEMP have high and low thresholds associated with them. If a conversion value falls outside of these limits (that is, if TEMP < low threshold or TEMP > high threshold), an alarm condition for that channel is set. The alarms are disabled by setting 0x000 for the low threshold and 0xFFF for the high threshold, respectively. These alarms are disabled by default. Because the configuration fields for the thresholds are only eight bits wide, the four LSBs are hardcoded for each threshold. The high thresholds four LSBs are hardcoded to 0xF, and the low thresholds four LSBs are hardcoded to 0x0. All the self diagnostic (SD) channels have fixed thresholds, except SD4, which measures the VOUT of the main DAC. The threshold for SD4 tracks the VOUT with respect to the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/TABLE_BCL_BCQ_PQB shows the calculations used to determine the high and low ADC thresholds for each SD channel. The limits in the two right-most columns are determined by the threshold columns to the left and given some margin. The four LSBs are assigned as described previously. Self Diagnostic (SD) Alarm ADC Thresholds SD ADC INPUT ACCEPTED LOW VALUE ACCEPTED HIGH VALUE LOW THRESHOLD HIGH THRESHOLD ADC LOW (HEX) ADC HIGH (HEX) SD0 VREF/2 VREF/2 – 9% – 25 mV VREF/2 + 9% + 25 mV 0.54375 V 0.70625 V 0x6D0 0x92F SD1 PVDD/6 1.65/6 – 25 mV 6/6 + 25 mV 0.25 V 1.025 V 0x310 0xD3F SD2 VDD/2 1.6/2 – 25 mV 2/2 + 25 mV 0.775 V 1.025 V 0x9C0 0xD3F SD3 0.6 V 0.6 V – 9% – 25 mV 0.6 V + 9% + 25 mV 0.521 V 0.679 V 0x690 0x8CF SD4 VOUT/2 VOUT/2 – 6 mV VOUT/2 + 6 mV VOUT – 12 mV VOUT + 12 mV Expected – 0x040 Expected + 0x040 The alarm threshold for the SD4 input depends on the expected ADC measurement based on the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/EQUATION-BLOCK_QF3_WXF_QVB shows the expected ADC code for SD4. ADC Expected Code = DAC_CODE[MSB:MSB-11] Programmable Out-of-Range Alarms The AFEx82H1 are capable of continuously analyzing the supplies, external ADC inputs, DAC output voltage, reference, internal temperature, and other internal signals for normal operation. Normal operation for the conversion results is established through the lower- and upper-threshold registers. When any of the monitored inputs are out of the specified range, the corresponding alarm bit in the alarm status registers is set. The alarm bits in the alarm status registers are latched. The alarm bits are referred to as being latched because the alarm bits remain set until read by software. This design makes sure that out-of-limit events cannot be missed if the software is polling the device periodically. All bits are cleared when reading the alarm status registers, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle. When the alarm event is cleared, the DAC is reloaded with the contents of the DAC active registers, which allows the DAC outputs to return to the previous operating point without any additional commands All alarms can be used to generate a hardware interrupt signal on the ALARM pin; see also . In addition, describes how the alarm action can be individually configured for each alarm. The AFEx82H1 are capable of continuously analyzing the supplies, external ADC inputs, DAC output voltage, reference, internal temperature, and other internal signals for normal operation. Normal operation for the conversion results is established through the lower- and upper-threshold registers. When any of the monitored inputs are out of the specified range, the corresponding alarm bit in the alarm status registers is set. The alarm bits in the alarm status registers are latched. The alarm bits are referred to as being latched because the alarm bits remain set until read by software. This design makes sure that out-of-limit events cannot be missed if the software is polling the device periodically. All bits are cleared when reading the alarm status registers, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle. When the alarm event is cleared, the DAC is reloaded with the contents of the DAC active registers, which allows the DAC outputs to return to the previous operating point without any additional commands All alarms can be used to generate a hardware interrupt signal on the ALARM pin; see also . In addition, describes how the alarm action can be individually configured for each alarm. The AFEx82H1 are capable of continuously analyzing the supplies, external ADC inputs, DAC output voltage, reference, internal temperature, and other internal signals for normal operation.AFEx82H1Normal operation for the conversion results is established through the lower- and upper-threshold registers. When any of the monitored inputs are out of the specified range, the corresponding alarm bit in the alarm status registers is set.The alarm bits in the alarm status registers are latched. The alarm bits are referred to as being latched because the alarm bits remain set until read by software. This design makes sure that out-of-limit events cannot be missed if the software is polling the device periodically. All bits are cleared when reading the alarm status registers, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle. When the alarm event is cleared, the DAC is reloaded with the contents of the DAC active registers, which allows the DAC outputs to return to the previous operating point without any additional commandsAll alarms can be used to generate a hardware interrupt signal on the ALARM pin; see also . In addition, describes how the alarm action can be individually configured for each alarm.ALARM Alarm-Based Interrupts One or more of the available alarms can be set to activate the ALARM pin. Connect the ALARM pin as an optional hardware interrupt to the host. The host can query the alarm status registers to determine the alarm source upon assertion of the interrupt. Any alarm event activates the pin, as long as the alarm is not masked in the ALARM_STATUS_MASK register. When an alarm event is masked, the occurrence of the event sets the corresponding status bit in the alarm status registers, but does not activate the ALARM pin. The ALARM pin output depends on ALARM_STATUS and ALARM_STATUS_MASK register settings, independent of ALARM_ACT register settings. Alarm-Based Interrupts One or more of the available alarms can be set to activate the ALARM pin. Connect the ALARM pin as an optional hardware interrupt to the host. The host can query the alarm status registers to determine the alarm source upon assertion of the interrupt. Any alarm event activates the pin, as long as the alarm is not masked in the ALARM_STATUS_MASK register. When an alarm event is masked, the occurrence of the event sets the corresponding status bit in the alarm status registers, but does not activate the ALARM pin. The ALARM pin output depends on ALARM_STATUS and ALARM_STATUS_MASK register settings, independent of ALARM_ACT register settings. One or more of the available alarms can be set to activate the ALARM pin. Connect the ALARM pin as an optional hardware interrupt to the host. The host can query the alarm status registers to determine the alarm source upon assertion of the interrupt. Any alarm event activates the pin, as long as the alarm is not masked in the ALARM_STATUS_MASK register. When an alarm event is masked, the occurrence of the event sets the corresponding status bit in the alarm status registers, but does not activate the ALARM pin. The ALARM pin output depends on ALARM_STATUS and ALARM_STATUS_MASK register settings, independent of ALARM_ACT register settings. One or more of the available alarms can be set to activate the ALARM pin. Connect the ALARM pin as an optional hardware interrupt to the host. The host can query the alarm status registers to determine the alarm source upon assertion of the interrupt. Any alarm event activates the pin, as long as the alarm is not masked in the ALARM_STATUS_MASK register. When an alarm event is masked, the occurrence of the event sets the corresponding status bit in the alarm status registers, but does not activate the ALARM pin.ALARMALARMALARM The ALARM pin output depends on ALARM_STATUS and ALARM_STATUS_MASK register settings, independent of ALARM_ACT register settings. The ALARM pin output depends on ALARM_STATUS and ALARM_STATUS_MASK register settings, independent of ALARM_ACT register settings.ALARM Alarm Action Configuration Register The AFEx82H1 provides an alarm action configuration register: ALARM_ACT, . Writing to this register selects the device action that automatically occurs for a specific alarm condition. The ALARM_ACT register determines how the main DAC responds to an alarm event from either an ADC conversion on the self-diagnostics channels (AIN0, AIN1, and TEMP), or from a CRC, WDT, VREF, TEMP_HI, or TEMP_LO fault. Only these faults cause a response by the DAC. Any other alarm status events trigger the ALARM pin. There are four options for alarm action. In case different settings are selected for different alarm conditions, the following low-to-high priority is considered when taking action: 0. → No action 1. → DAC CLEAR state 2. → VOUT alarm voltage 3. → VOUT Hi-Z If option 1 is selected when the alarm event occurs, then the DAC is forced to the clear code. This operation is done by controlling the input code to the DAC. If option 2 is selected when the alarm event occurs, then VOUT is forced to the alarm voltage. The alarm voltage is controlled by either pin or register bit. If SPECIAL_CFG.AIN1_ENB = 0, then the AIN1 pin controls alarm polarity. Also, register bit SPECIAL_CFG.ALMV_POL can be used. If either of these signals = 1, then the alarm voltage is high; otherwise, the alarm voltage is low. The SPECIAL_CFG register is only reset with POR, so the user setting remains intact through hardware or software resets. If option 3 is selected when the alarm event occurs, then the VOUT buffer is put into Hi-Z. If multiple events occur, then the highest setting takes precedence. Option 3 has the highest priority. To disable action response to an alarm, set the corresponding bits in ALARM_ACT to 0h. Alarm action response is cleared either when the triggered condition bit resets (behavior depends on whether the fault bit in ALARM_STATUS is sticky or not), or by changing the action configuration to 0h. An alarm action, as configured, executes when an alarm occurs depending on ALARM_STATUS and ALARM_ACT registers. Action response is independent of ALARM_STATUS_MASK settings. Alarm Action Configuration Register The AFEx82H1 provides an alarm action configuration register: ALARM_ACT, . Writing to this register selects the device action that automatically occurs for a specific alarm condition. The ALARM_ACT register determines how the main DAC responds to an alarm event from either an ADC conversion on the self-diagnostics channels (AIN0, AIN1, and TEMP), or from a CRC, WDT, VREF, TEMP_HI, or TEMP_LO fault. Only these faults cause a response by the DAC. Any other alarm status events trigger the ALARM pin. There are four options for alarm action. In case different settings are selected for different alarm conditions, the following low-to-high priority is considered when taking action: 0. → No action 1. → DAC CLEAR state 2. → VOUT alarm voltage 3. → VOUT Hi-Z If option 1 is selected when the alarm event occurs, then the DAC is forced to the clear code. This operation is done by controlling the input code to the DAC. If option 2 is selected when the alarm event occurs, then VOUT is forced to the alarm voltage. The alarm voltage is controlled by either pin or register bit. If SPECIAL_CFG.AIN1_ENB = 0, then the AIN1 pin controls alarm polarity. Also, register bit SPECIAL_CFG.ALMV_POL can be used. If either of these signals = 1, then the alarm voltage is high; otherwise, the alarm voltage is low. The SPECIAL_CFG register is only reset with POR, so the user setting remains intact through hardware or software resets. If option 3 is selected when the alarm event occurs, then the VOUT buffer is put into Hi-Z. If multiple events occur, then the highest setting takes precedence. Option 3 has the highest priority. To disable action response to an alarm, set the corresponding bits in ALARM_ACT to 0h. Alarm action response is cleared either when the triggered condition bit resets (behavior depends on whether the fault bit in ALARM_STATUS is sticky or not), or by changing the action configuration to 0h. An alarm action, as configured, executes when an alarm occurs depending on ALARM_STATUS and ALARM_ACT registers. Action response is independent of ALARM_STATUS_MASK settings. The AFEx82H1 provides an alarm action configuration register: ALARM_ACT, . Writing to this register selects the device action that automatically occurs for a specific alarm condition. The ALARM_ACT register determines how the main DAC responds to an alarm event from either an ADC conversion on the self-diagnostics channels (AIN0, AIN1, and TEMP), or from a CRC, WDT, VREF, TEMP_HI, or TEMP_LO fault. Only these faults cause a response by the DAC. Any other alarm status events trigger the ALARM pin. There are four options for alarm action. In case different settings are selected for different alarm conditions, the following low-to-high priority is considered when taking action: 0. → No action 1. → DAC CLEAR state 2. → VOUT alarm voltage 3. → VOUT Hi-Z If option 1 is selected when the alarm event occurs, then the DAC is forced to the clear code. This operation is done by controlling the input code to the DAC. If option 2 is selected when the alarm event occurs, then VOUT is forced to the alarm voltage. The alarm voltage is controlled by either pin or register bit. If SPECIAL_CFG.AIN1_ENB = 0, then the AIN1 pin controls alarm polarity. Also, register bit SPECIAL_CFG.ALMV_POL can be used. If either of these signals = 1, then the alarm voltage is high; otherwise, the alarm voltage is low. The SPECIAL_CFG register is only reset with POR, so the user setting remains intact through hardware or software resets. If option 3 is selected when the alarm event occurs, then the VOUT buffer is put into Hi-Z. If multiple events occur, then the highest setting takes precedence. Option 3 has the highest priority. To disable action response to an alarm, set the corresponding bits in ALARM_ACT to 0h. Alarm action response is cleared either when the triggered condition bit resets (behavior depends on whether the fault bit in ALARM_STATUS is sticky or not), or by changing the action configuration to 0h. An alarm action, as configured, executes when an alarm occurs depending on ALARM_STATUS and ALARM_ACT registers. Action response is independent of ALARM_STATUS_MASK settings. The AFEx82H1 provides an alarm action configuration register: ALARM_ACT, . Writing to this register selects the device action that automatically occurs for a specific alarm condition. The ALARM_ACT register determines how the main DAC responds to an alarm event from either an ADC conversion on the self-diagnostics channels (AIN0, AIN1, and TEMP), or from a CRC, WDT, VREF, TEMP_HI, or TEMP_LO fault. Only these faults cause a response by the DAC. Any other alarm status events trigger the ALARM pin. There are four options for alarm action. In case different settings are selected for different alarm conditions, the following low-to-high priority is considered when taking action:AFEx82H1ALARM 0. → No action 1. → DAC CLEAR state 2. → VOUT alarm voltage 3. → VOUT Hi-Z 0. → No action1. → DAC CLEAR state2. → VOUT alarm voltage3. → VOUT Hi-ZIf option 1 is selected when the alarm event occurs, then the DAC is forced to the clear code. This operation is done by controlling the input code to the DAC.If option 2 is selected when the alarm event occurs, then VOUT is forced to the alarm voltage. The alarm voltage is controlled by either pin or register bit. If SPECIAL_CFG.AIN1_ENB = 0, then the AIN1 pin controls alarm polarity. Also, register bit SPECIAL_CFG.ALMV_POL can be used. If either of these signals = 1, then the alarm voltage is high; otherwise, the alarm voltage is low. The SPECIAL_CFG register is only reset with POR, so the user setting remains intact through hardware or software resets.If option 3 is selected when the alarm event occurs, then the VOUT buffer is put into Hi-Z. If multiple events occur, then the highest setting takes precedence. Option 3 has the highest priority.To disable action response to an alarm, set the corresponding bits in ALARM_ACT to 0h. Alarm action response is cleared either when the triggered condition bit resets (behavior depends on whether the fault bit in ALARM_STATUS is sticky or not), or by changing the action configuration to 0h. An alarm action, as configured, executes when an alarm occurs depending on ALARM_STATUS and ALARM_ACT registers. Action response is independent of ALARM_STATUS_MASK settings. An alarm action, as configured, executes when an alarm occurs depending on ALARM_STATUS and ALARM_ACT registers. Action response is independent of ALARM_STATUS_MASK settings. Alarm Voltage Generator shows that the alarm voltage is generated independently from the DAC output voltage. The alarm polarity control logic selects the output level of the alarm voltage generator. The alarm action control logic selects between the DAC output and alarm voltage generator output voltages. The alarm action control logic also controls the output buffer Hi-Z switch. Alarm Voltage Generator Architecture During normal operation, the expected VOUT voltage depends on the DAC_CODE. The ADC thresholds for the SD4 (VOUT) diagnostic channel are set around the programmed DAC_CODE. During the alarm condition, if the alarm action changes the VOUT voltage to the alarm voltage, or switches the VOUT buffer into Hi-Z mode, the VOUT voltage no longer depends on the DAC_CODE. In this case, the SD4 (VOUT) diagnostic channel also reports the alarm. To clear this alarm, as long as all other alarm conditions are cleared, set the alarm action to either no action or to the DAC clear code. Applying either alarm action sets the VOUT voltage within the expected ADC thresholds and clears the alarm after the next ADC measurement of the SD4 (VOUT) channel. Give special consideration to the alarm logic during the transient events. When the new DAC_CODE goes beyond the SD4 (VOUT) alarm thresholds with the ADC monitoring the SD4 (VOUT) input in auto mode, the ADC conversion can occur while VOUT settles to a new value. This conversion can trigger a false alarm. There are two ways to prevent this false alarm: Use direct mode and allow VOUT to settle before triggering the next ADC conversion. Set ADC_CFG.FLT_CNT > 0. With this configuration, a single error in SD4 or any other measurement does not cause an alarm condition to be asserted. Alarm Voltage Generator shows that the alarm voltage is generated independently from the DAC output voltage. The alarm polarity control logic selects the output level of the alarm voltage generator. The alarm action control logic selects between the DAC output and alarm voltage generator output voltages. The alarm action control logic also controls the output buffer Hi-Z switch. Alarm Voltage Generator Architecture During normal operation, the expected VOUT voltage depends on the DAC_CODE. The ADC thresholds for the SD4 (VOUT) diagnostic channel are set around the programmed DAC_CODE. During the alarm condition, if the alarm action changes the VOUT voltage to the alarm voltage, or switches the VOUT buffer into Hi-Z mode, the VOUT voltage no longer depends on the DAC_CODE. In this case, the SD4 (VOUT) diagnostic channel also reports the alarm. To clear this alarm, as long as all other alarm conditions are cleared, set the alarm action to either no action or to the DAC clear code. Applying either alarm action sets the VOUT voltage within the expected ADC thresholds and clears the alarm after the next ADC measurement of the SD4 (VOUT) channel. Give special consideration to the alarm logic during the transient events. When the new DAC_CODE goes beyond the SD4 (VOUT) alarm thresholds with the ADC monitoring the SD4 (VOUT) input in auto mode, the ADC conversion can occur while VOUT settles to a new value. This conversion can trigger a false alarm. There are two ways to prevent this false alarm: Use direct mode and allow VOUT to settle before triggering the next ADC conversion. Set ADC_CFG.FLT_CNT > 0. With this configuration, a single error in SD4 or any other measurement does not cause an alarm condition to be asserted. shows that the alarm voltage is generated independently from the DAC output voltage. The alarm polarity control logic selects the output level of the alarm voltage generator. The alarm action control logic selects between the DAC output and alarm voltage generator output voltages. The alarm action control logic also controls the output buffer Hi-Z switch. Alarm Voltage Generator Architecture During normal operation, the expected VOUT voltage depends on the DAC_CODE. The ADC thresholds for the SD4 (VOUT) diagnostic channel are set around the programmed DAC_CODE. During the alarm condition, if the alarm action changes the VOUT voltage to the alarm voltage, or switches the VOUT buffer into Hi-Z mode, the VOUT voltage no longer depends on the DAC_CODE. In this case, the SD4 (VOUT) diagnostic channel also reports the alarm. To clear this alarm, as long as all other alarm conditions are cleared, set the alarm action to either no action or to the DAC clear code. Applying either alarm action sets the VOUT voltage within the expected ADC thresholds and clears the alarm after the next ADC measurement of the SD4 (VOUT) channel. Give special consideration to the alarm logic during the transient events. When the new DAC_CODE goes beyond the SD4 (VOUT) alarm thresholds with the ADC monitoring the SD4 (VOUT) input in auto mode, the ADC conversion can occur while VOUT settles to a new value. This conversion can trigger a false alarm. There are two ways to prevent this false alarm: Use direct mode and allow VOUT to settle before triggering the next ADC conversion. Set ADC_CFG.FLT_CNT > 0. With this configuration, a single error in SD4 or any other measurement does not cause an alarm condition to be asserted. shows that the alarm voltage is generated independently from the DAC output voltage. The alarm polarity control logic selects the output level of the alarm voltage generator. The alarm action control logic selects between the DAC output and alarm voltage generator output voltages. The alarm action control logic also controls the output buffer Hi-Z switch. Alarm Voltage Generator Architecture Alarm Voltage Generator ArchitectureDuring normal operation, the expected VOUT voltage depends on the DAC_CODE. The ADC thresholds for the SD4 (VOUT) diagnostic channel are set around the programmed DAC_CODE. During the alarm condition, if the alarm action changes the VOUT voltage to the alarm voltage, or switches the VOUT buffer into Hi-Z mode, the VOUT voltage no longer depends on the DAC_CODE. In this case, the SD4 (VOUT) diagnostic channel also reports the alarm. To clear this alarm, as long as all other alarm conditions are cleared, set the alarm action to either no action or to the DAC clear code. Applying either alarm action sets the VOUT voltage within the expected ADC thresholds and clears the alarm after the next ADC measurement of the SD4 (VOUT) channel.Give special consideration to the alarm logic during the transient events. When the new DAC_CODE goes beyond the SD4 (VOUT) alarm thresholds with the ADC monitoring the SD4 (VOUT) input in auto mode, the ADC conversion can occur while VOUT settles to a new value. This conversion can trigger a false alarm. There are two ways to prevent this false alarm: Use direct mode and allow VOUT to settle before triggering the next ADC conversion. Set ADC_CFG.FLT_CNT > 0. With this configuration, a single error in SD4 or any other measurement does not cause an alarm condition to be asserted. Use direct mode and allow VOUT to settle before triggering the next ADC conversion.Set ADC_CFG.FLT_CNT > 0. With this configuration, a single error in SD4 or any other measurement does not cause an alarm condition to be asserted. Temperature Sensor Alarm Function The AFEx82H1 continuously monitor the internal die temperature. In addition to the ADC measurement, the temperature sensor triggers a comparator to show a thermal warning and a thermal error. A thermal warning alarm is set when the temperature exceeds 85°C. Additionally, a thermal error alarm is set when the die temperature exceeds 130°C. The thermal warning and thermal error alarms can be configured to set the ALARM pin and are indicated in the ALARM_STATUS register. These alarms can be masked with the ALARM_MASK register and also be configured to control the DAC output with the ALARM_ACT register. Temperature Sensor Alarm Function The AFEx82H1 continuously monitor the internal die temperature. In addition to the ADC measurement, the temperature sensor triggers a comparator to show a thermal warning and a thermal error. A thermal warning alarm is set when the temperature exceeds 85°C. Additionally, a thermal error alarm is set when the die temperature exceeds 130°C. The thermal warning and thermal error alarms can be configured to set the ALARM pin and are indicated in the ALARM_STATUS register. These alarms can be masked with the ALARM_MASK register and also be configured to control the DAC output with the ALARM_ACT register. The AFEx82H1 continuously monitor the internal die temperature. In addition to the ADC measurement, the temperature sensor triggers a comparator to show a thermal warning and a thermal error. A thermal warning alarm is set when the temperature exceeds 85°C. Additionally, a thermal error alarm is set when the die temperature exceeds 130°C. The thermal warning and thermal error alarms can be configured to set the ALARM pin and are indicated in the ALARM_STATUS register. These alarms can be masked with the ALARM_MASK register and also be configured to control the DAC output with the ALARM_ACT register. The AFEx82H1 continuously monitor the internal die temperature. In addition to the ADC measurement, the temperature sensor triggers a comparator to show a thermal warning and a thermal error. A thermal warning alarm is set when the temperature exceeds 85°C. Additionally, a thermal error alarm is set when the die temperature exceeds 130°C. AFEx82H1 The thermal warning and thermal error alarms can be configured to set the ALARM pin and are indicated in the ALARM_STATUS register. These alarms can be masked with the ALARM_MASK register and also be configured to control the DAC output with the ALARM_ACT register.ALARM Internal Reference Alarm Function The devices provide out-of-range detection for the reference voltage. When the reference voltage exceeds ±5% of the nominal value, the reference alarm flag (VREF_FLT bit) is set. Make sure that a reference alarm condition has not been issued by the device before powering up the DAC output. Internal Reference Alarm Function The devices provide out-of-range detection for the reference voltage. When the reference voltage exceeds ±5% of the nominal value, the reference alarm flag (VREF_FLT bit) is set. Make sure that a reference alarm condition has not been issued by the device before powering up the DAC output. The devices provide out-of-range detection for the reference voltage. When the reference voltage exceeds ±5% of the nominal value, the reference alarm flag (VREF_FLT bit) is set. Make sure that a reference alarm condition has not been issued by the device before powering up the DAC output. The devices provide out-of-range detection for the reference voltage. When the reference voltage exceeds ±5% of the nominal value, the reference alarm flag (VREF_FLT bit) is set. Make sure that a reference alarm condition has not been issued by the device before powering up the DAC output. ADC Alarm Function The AFEx82H1 provide independent out-of-range detection for each of the ADC inputs. shows the out-of-range detection block. When the measurement is out of range, the corresponding alarm bit is set to flag the out-of-range condition. ADC Out-of-Range Alarm An alarm event is only registered when the monitored signal is out of range for N number of consecutive conversions, where N is configured in the ADC_CFG.FLT_CNT false alarm register settings. If the monitored signal returns to the normal range before N consecutive conversions, an alarm event is not issued. If an ADC input signal is out of range and the alarm is enabled, then the corresponding alarm bit is set to 1. However, the alarm condition is cleared only when the conversion result returns to a value less than the high-limit register setting and greater than the low-limit register setting by the number of codes specified by the hysteresis setting (see ). The hysteresis is a programmable value between 0 LSB to 127 LSB in the ADC_CFG.HYST register. ADC Alarm Hysteresis ADC Alarm Function The AFEx82H1 provide independent out-of-range detection for each of the ADC inputs. shows the out-of-range detection block. When the measurement is out of range, the corresponding alarm bit is set to flag the out-of-range condition. ADC Out-of-Range Alarm An alarm event is only registered when the monitored signal is out of range for N number of consecutive conversions, where N is configured in the ADC_CFG.FLT_CNT false alarm register settings. If the monitored signal returns to the normal range before N consecutive conversions, an alarm event is not issued. If an ADC input signal is out of range and the alarm is enabled, then the corresponding alarm bit is set to 1. However, the alarm condition is cleared only when the conversion result returns to a value less than the high-limit register setting and greater than the low-limit register setting by the number of codes specified by the hysteresis setting (see ). The hysteresis is a programmable value between 0 LSB to 127 LSB in the ADC_CFG.HYST register. ADC Alarm Hysteresis The AFEx82H1 provide independent out-of-range detection for each of the ADC inputs. shows the out-of-range detection block. When the measurement is out of range, the corresponding alarm bit is set to flag the out-of-range condition. ADC Out-of-Range Alarm An alarm event is only registered when the monitored signal is out of range for N number of consecutive conversions, where N is configured in the ADC_CFG.FLT_CNT false alarm register settings. If the monitored signal returns to the normal range before N consecutive conversions, an alarm event is not issued. If an ADC input signal is out of range and the alarm is enabled, then the corresponding alarm bit is set to 1. However, the alarm condition is cleared only when the conversion result returns to a value less than the high-limit register setting and greater than the low-limit register setting by the number of codes specified by the hysteresis setting (see ). The hysteresis is a programmable value between 0 LSB to 127 LSB in the ADC_CFG.HYST register. ADC Alarm Hysteresis The AFEx82H1 provide independent out-of-range detection for each of the ADC inputs. shows the out-of-range detection block. When the measurement is out of range, the corresponding alarm bit is set to flag the out-of-range condition.AFEx82H1 ADC Out-of-Range Alarm ADC Out-of-Range AlarmAn alarm event is only registered when the monitored signal is out of range for N number of consecutive conversions, where N is configured in the ADC_CFG.FLT_CNT false alarm register settings. If the monitored signal returns to the normal range before N consecutive conversions, an alarm event is not issued. NNNIf an ADC input signal is out of range and the alarm is enabled, then the corresponding alarm bit is set to 1. However, the alarm condition is cleared only when the conversion result returns to a value less than the high-limit register setting and greater than the low-limit register setting by the number of codes specified by the hysteresis setting (see ). The hysteresis is a programmable value between 0 LSB to 127 LSB in the ADC_CFG.HYST register. ADC Alarm Hysteresis ADC Alarm Hysteresis Fault Detection There are two fields within the ADC_CFG register: FLT_CNT and HYST. These fields are applied to the assertion and deassertion of alarm conditions for all the ADC channels. ADC_CFG.FLT_CNT determines the maximum number of accepted consecutive failures before an alarm condition is reported. For example, if ADC_CFG.FLT_CNT is set for two counts, then three consecutive conversions must be outside of the thresholds to trigger an alarm. Each failure counts towards the FLT_CNT limit even if the failures alternate between high threshold and low threshold. ADC_CFG.HYST sets the hysteresis used by the alarm-detection circuit. After an alarm is triggered, the hysteresis is applied before the alarm condition is released. In the case of the high threshold, the hysteresis is subtracted from the threshold value. In the case of the low threshold limit, the hysteresis is added to the threshold value. Channels AIN0, AIN1, and TEMP have high and low thresholds associated with them. If a conversion value falls outside of these limits (that is, if TEMP < low threshold or TEMP > high threshold), an alarm condition for that channel is set. The alarms are disabled by setting 0x000 for the low threshold and 0xFFF for the high threshold, respectively. These alarms are disabled by default. Because the configuration fields for the thresholds are only eight bits wide, the four LSBs are hardcoded for each threshold. The high thresholds four LSBs are hardcoded to 0xF, and the low thresholds four LSBs are hardcoded to 0x0. All the self diagnostic (SD) channels have fixed thresholds, except SD4, which measures the VOUT of the main DAC. The threshold for SD4 tracks the VOUT with respect to the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/TABLE_BCL_BCQ_PQB shows the calculations used to determine the high and low ADC thresholds for each SD channel. The limits in the two right-most columns are determined by the threshold columns to the left and given some margin. The four LSBs are assigned as described previously. Self Diagnostic (SD) Alarm ADC Thresholds SD ADC INPUT ACCEPTED LOW VALUE ACCEPTED HIGH VALUE LOW THRESHOLD HIGH THRESHOLD ADC LOW (HEX) ADC HIGH (HEX) SD0 VREF/2 VREF/2 – 9% – 25 mV VREF/2 + 9% + 25 mV 0.54375 V 0.70625 V 0x6D0 0x92F SD1 PVDD/6 1.65/6 – 25 mV 6/6 + 25 mV 0.25 V 1.025 V 0x310 0xD3F SD2 VDD/2 1.6/2 – 25 mV 2/2 + 25 mV 0.775 V 1.025 V 0x9C0 0xD3F SD3 0.6 V 0.6 V – 9% – 25 mV 0.6 V + 9% + 25 mV 0.521 V 0.679 V 0x690 0x8CF SD4 VOUT/2 VOUT/2 – 6 mV VOUT/2 + 6 mV VOUT – 12 mV VOUT + 12 mV Expected – 0x040 Expected + 0x040 The alarm threshold for the SD4 input depends on the expected ADC measurement based on the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/EQUATION-BLOCK_QF3_WXF_QVB shows the expected ADC code for SD4. ADC Expected Code = DAC_CODE[MSB:MSB-11] Fault Detection There are two fields within the ADC_CFG register: FLT_CNT and HYST. These fields are applied to the assertion and deassertion of alarm conditions for all the ADC channels. ADC_CFG.FLT_CNT determines the maximum number of accepted consecutive failures before an alarm condition is reported. For example, if ADC_CFG.FLT_CNT is set for two counts, then three consecutive conversions must be outside of the thresholds to trigger an alarm. Each failure counts towards the FLT_CNT limit even if the failures alternate between high threshold and low threshold. ADC_CFG.HYST sets the hysteresis used by the alarm-detection circuit. After an alarm is triggered, the hysteresis is applied before the alarm condition is released. In the case of the high threshold, the hysteresis is subtracted from the threshold value. In the case of the low threshold limit, the hysteresis is added to the threshold value. Channels AIN0, AIN1, and TEMP have high and low thresholds associated with them. If a conversion value falls outside of these limits (that is, if TEMP < low threshold or TEMP > high threshold), an alarm condition for that channel is set. The alarms are disabled by setting 0x000 for the low threshold and 0xFFF for the high threshold, respectively. These alarms are disabled by default. Because the configuration fields for the thresholds are only eight bits wide, the four LSBs are hardcoded for each threshold. The high thresholds four LSBs are hardcoded to 0xF, and the low thresholds four LSBs are hardcoded to 0x0. All the self diagnostic (SD) channels have fixed thresholds, except SD4, which measures the VOUT of the main DAC. The threshold for SD4 tracks the VOUT with respect to the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/TABLE_BCL_BCQ_PQB shows the calculations used to determine the high and low ADC thresholds for each SD channel. The limits in the two right-most columns are determined by the threshold columns to the left and given some margin. The four LSBs are assigned as described previously. Self Diagnostic (SD) Alarm ADC Thresholds SD ADC INPUT ACCEPTED LOW VALUE ACCEPTED HIGH VALUE LOW THRESHOLD HIGH THRESHOLD ADC LOW (HEX) ADC HIGH (HEX) SD0 VREF/2 VREF/2 – 9% – 25 mV VREF/2 + 9% + 25 mV 0.54375 V 0.70625 V 0x6D0 0x92F SD1 PVDD/6 1.65/6 – 25 mV 6/6 + 25 mV 0.25 V 1.025 V 0x310 0xD3F SD2 VDD/2 1.6/2 – 25 mV 2/2 + 25 mV 0.775 V 1.025 V 0x9C0 0xD3F SD3 0.6 V 0.6 V – 9% – 25 mV 0.6 V + 9% + 25 mV 0.521 V 0.679 V 0x690 0x8CF SD4 VOUT/2 VOUT/2 – 6 mV VOUT/2 + 6 mV VOUT – 12 mV VOUT + 12 mV Expected – 0x040 Expected + 0x040 The alarm threshold for the SD4 input depends on the expected ADC measurement based on the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/EQUATION-BLOCK_QF3_WXF_QVB shows the expected ADC code for SD4. ADC Expected Code = DAC_CODE[MSB:MSB-11] There are two fields within the ADC_CFG register: FLT_CNT and HYST. These fields are applied to the assertion and deassertion of alarm conditions for all the ADC channels. ADC_CFG.FLT_CNT determines the maximum number of accepted consecutive failures before an alarm condition is reported. For example, if ADC_CFG.FLT_CNT is set for two counts, then three consecutive conversions must be outside of the thresholds to trigger an alarm. Each failure counts towards the FLT_CNT limit even if the failures alternate between high threshold and low threshold. ADC_CFG.HYST sets the hysteresis used by the alarm-detection circuit. After an alarm is triggered, the hysteresis is applied before the alarm condition is released. In the case of the high threshold, the hysteresis is subtracted from the threshold value. In the case of the low threshold limit, the hysteresis is added to the threshold value. Channels AIN0, AIN1, and TEMP have high and low thresholds associated with them. If a conversion value falls outside of these limits (that is, if TEMP < low threshold or TEMP > high threshold), an alarm condition for that channel is set. The alarms are disabled by setting 0x000 for the low threshold and 0xFFF for the high threshold, respectively. These alarms are disabled by default. Because the configuration fields for the thresholds are only eight bits wide, the four LSBs are hardcoded for each threshold. The high thresholds four LSBs are hardcoded to 0xF, and the low thresholds four LSBs are hardcoded to 0x0. All the self diagnostic (SD) channels have fixed thresholds, except SD4, which measures the VOUT of the main DAC. The threshold for SD4 tracks the VOUT with respect to the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/TABLE_BCL_BCQ_PQB shows the calculations used to determine the high and low ADC thresholds for each SD channel. The limits in the two right-most columns are determined by the threshold columns to the left and given some margin. The four LSBs are assigned as described previously. Self Diagnostic (SD) Alarm ADC Thresholds SD ADC INPUT ACCEPTED LOW VALUE ACCEPTED HIGH VALUE LOW THRESHOLD HIGH THRESHOLD ADC LOW (HEX) ADC HIGH (HEX) SD0 VREF/2 VREF/2 – 9% – 25 mV VREF/2 + 9% + 25 mV 0.54375 V 0.70625 V 0x6D0 0x92F SD1 PVDD/6 1.65/6 – 25 mV 6/6 + 25 mV 0.25 V 1.025 V 0x310 0xD3F SD2 VDD/2 1.6/2 – 25 mV 2/2 + 25 mV 0.775 V 1.025 V 0x9C0 0xD3F SD3 0.6 V 0.6 V – 9% – 25 mV 0.6 V + 9% + 25 mV 0.521 V 0.679 V 0x690 0x8CF SD4 VOUT/2 VOUT/2 – 6 mV VOUT/2 + 6 mV VOUT – 12 mV VOUT + 12 mV Expected – 0x040 Expected + 0x040 The alarm threshold for the SD4 input depends on the expected ADC measurement based on the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/EQUATION-BLOCK_QF3_WXF_QVB shows the expected ADC code for SD4. ADC Expected Code = DAC_CODE[MSB:MSB-11] There are two fields within the ADC_CFG register: FLT_CNT and HYST. These fields are applied to the assertion and deassertion of alarm conditions for all the ADC channels.ADC_CFG.FLT_CNT determines the maximum number of accepted consecutive failures before an alarm condition is reported. For example, if ADC_CFG.FLT_CNT is set for two counts, then three consecutive conversions must be outside of the thresholds to trigger an alarm. Each failure counts towards the FLT_CNT limit even if the failures alternate between high threshold and low threshold.ADC_CFG.HYST sets the hysteresis used by the alarm-detection circuit. After an alarm is triggered, the hysteresis is applied before the alarm condition is released. In the case of the high threshold, the hysteresis is subtracted from the threshold value. In the case of the low threshold limit, the hysteresis is added to the threshold value.Channels AIN0, AIN1, and TEMP have high and low thresholds associated with them. If a conversion value falls outside of these limits (that is, if TEMP < low threshold or TEMP > high threshold), an alarm condition for that channel is set. The alarms are disabled by setting 0x000 for the low threshold and 0xFFF for the high threshold, respectively. These alarms are disabled by default. Because the configuration fields for the thresholds are only eight bits wide, the four LSBs are hardcoded for each threshold. The high thresholds four LSBs are hardcoded to 0xF, and the low thresholds four LSBs are hardcoded to 0x0.All the self diagnostic (SD) channels have fixed thresholds, except SD4, which measures the VOUT of the main DAC. The threshold for SD4 tracks the VOUT with respect to the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/TABLE_BCL_BCQ_PQB shows the calculations used to determine the high and low ADC thresholds for each SD channel. The limits in the two right-most columns are determined by the threshold columns to the left and given some margin. The four LSBs are assigned as described previously.#GUID-C1F70FC2-E981-4894-8A05-DB640937C351/TABLE_BCL_BCQ_PQB Self Diagnostic (SD) Alarm ADC Thresholds SD ADC INPUT ACCEPTED LOW VALUE ACCEPTED HIGH VALUE LOW THRESHOLD HIGH THRESHOLD ADC LOW (HEX) ADC HIGH (HEX) SD0 VREF/2 VREF/2 – 9% – 25 mV VREF/2 + 9% + 25 mV 0.54375 V 0.70625 V 0x6D0 0x92F SD1 PVDD/6 1.65/6 – 25 mV 6/6 + 25 mV 0.25 V 1.025 V 0x310 0xD3F SD2 VDD/2 1.6/2 – 25 mV 2/2 + 25 mV 0.775 V 1.025 V 0x9C0 0xD3F SD3 0.6 V 0.6 V – 9% – 25 mV 0.6 V + 9% + 25 mV 0.521 V 0.679 V 0x690 0x8CF SD4 VOUT/2 VOUT/2 – 6 mV VOUT/2 + 6 mV VOUT – 12 mV VOUT + 12 mV Expected – 0x040 Expected + 0x040 Self Diagnostic (SD) Alarm ADC Thresholds SD ADC INPUT ACCEPTED LOW VALUE ACCEPTED HIGH VALUE LOW THRESHOLD HIGH THRESHOLD ADC LOW (HEX) ADC HIGH (HEX) SD0 VREF/2 VREF/2 – 9% – 25 mV VREF/2 + 9% + 25 mV 0.54375 V 0.70625 V 0x6D0 0x92F SD1 PVDD/6 1.65/6 – 25 mV 6/6 + 25 mV 0.25 V 1.025 V 0x310 0xD3F SD2 VDD/2 1.6/2 – 25 mV 2/2 + 25 mV 0.775 V 1.025 V 0x9C0 0xD3F SD3 0.6 V 0.6 V – 9% – 25 mV 0.6 V + 9% + 25 mV 0.521 V 0.679 V 0x690 0x8CF SD4 VOUT/2 VOUT/2 – 6 mV VOUT/2 + 6 mV VOUT – 12 mV VOUT + 12 mV Expected – 0x040 Expected + 0x040 SD ADC INPUT ACCEPTED LOW VALUE ACCEPTED HIGH VALUE LOW THRESHOLD HIGH THRESHOLD ADC LOW (HEX) ADC HIGH (HEX) SD ADC INPUT ACCEPTED LOW VALUE ACCEPTED HIGH VALUE LOW THRESHOLD HIGH THRESHOLD ADC LOW (HEX) ADC HIGH (HEX) SDADC INPUTACCEPTED LOW VALUEACCEPTED HIGH VALUELOW THRESHOLDHIGH THRESHOLDADC LOW (HEX)ADC HIGH (HEX) SD0 VREF/2 VREF/2 – 9% – 25 mV VREF/2 + 9% + 25 mV 0.54375 V 0.70625 V 0x6D0 0x92F SD1 PVDD/6 1.65/6 – 25 mV 6/6 + 25 mV 0.25 V 1.025 V 0x310 0xD3F SD2 VDD/2 1.6/2 – 25 mV 2/2 + 25 mV 0.775 V 1.025 V 0x9C0 0xD3F SD3 0.6 V 0.6 V – 9% – 25 mV 0.6 V + 9% + 25 mV 0.521 V 0.679 V 0x690 0x8CF SD4 VOUT/2 VOUT/2 – 6 mV VOUT/2 + 6 mV VOUT – 12 mV VOUT + 12 mV Expected – 0x040 Expected + 0x040 SD0 VREF/2 VREF/2 – 9% – 25 mV VREF/2 + 9% + 25 mV 0.54375 V 0.70625 V 0x6D0 0x92F SD0VREF/2VREF/2 – 9% – 25 mVVREF/2 + 9% + 25 mV0.54375 V0.70625 V0x6D00x92F SD1 PVDD/6 1.65/6 – 25 mV 6/6 + 25 mV 0.25 V 1.025 V 0x310 0xD3F SD1PVDD/61.65/6 – 25 mV6/6 + 25 mV0.25 V1.025 V0x3100xD3F SD2 VDD/2 1.6/2 – 25 mV 2/2 + 25 mV 0.775 V 1.025 V 0x9C0 0xD3F SD2VDD/21.6/2 – 25 mV2/2 + 25 mV0.775 V1.025 V0x9C00xD3F SD3 0.6 V 0.6 V – 9% – 25 mV 0.6 V + 9% + 25 mV 0.521 V 0.679 V 0x690 0x8CF SD30.6 V0.6 V – 9% – 25 mV0.6 V + 9% + 25 mV0.521 V0.679 V0x6900x8CF SD4 VOUT/2 VOUT/2 – 6 mV VOUT/2 + 6 mV VOUT – 12 mV VOUT + 12 mV Expected – 0x040 Expected + 0x040 SD4VOUT/2VOUT/2 – 6 mVVOUT/2 + 6 mVVOUT – 12 mVVOUT + 12 mVExpected – 0x040Expected + 0x040The alarm threshold for the SD4 input depends on the expected ADC measurement based on the DAC code. #GUID-C1F70FC2-E981-4894-8A05-DB640937C351/EQUATION-BLOCK_QF3_WXF_QVB shows the expected ADC code for SD4.#GUID-C1F70FC2-E981-4894-8A05-DB640937C351/EQUATION-BLOCK_QF3_WXF_QVBADC Expected Code = DAC_CODE[MSB:MSB-11] IRQ The devices include an interrupt request (IRQ) to communicate the occurrence of a variety of events to the host controller. The IRQ block initiates interrupts that are reported internally in a status register, externally on the IRQ pin if the function is enabled, or on the ALARM pin if the condition is from the ALARM_STATUS register. shows the IRQ block diagram. IRQ Block Diagram There are three registers that can generate interrupts: GEN_STATUS, MODEM_STATUS, and ALARM_STATUS. Each of these registers has a corresponding STATUS_MASK register. The mask register controls which of the events trigger an interrupt. Writing a 1 in the mask register masks, or disables, the event from triggering an interrupt. Writing a 0 in the mask register allows the event to trigger an IRQ. All bits are masked by default. Some status bits are sticky. Reading the corresponding register clears a sticky bit, unless the condition still exists. The IRQ is configured through CONFIG.IRQ_LVL to be edge- or level-sensitive. Set this bit to logic 1 to enable level-sensitive functionality (default). In edge-sensitive mode, the IRQ signal is a synchronous pulse, one internal clock period wide (813 ns). In level-sensitive mode, the IRQ is set and remains set as long as the condition exists. After the IRQ condition is removed, the condition is cleared by reading the corresponding status register. Trying to clear the bit while the condition still exists does not allow the bit to be cleared if the bit is sticky. CONFIG.IRQ_POL determines the active level of the IRQ. A logic 1 configures IRQ to be active high. When using edge-sensitive IRQ signals, there is a clock cycle delay for synchronization and edge detection. With a 307.2-kHz clock, this delay is up to 3.26 μs. For level-sensitive mode, the delay is approximately 10 ns to 20 ns. Most status bits have two versions within the design. The first version is an edge event that is created when the status is asserted. This signal is used to generate edge-sensitive IRQs. This edge detection prevents multiple status events from blocking one another. The second version is the sticky version of the status bit. This signal is set upon assertion of the status bit and cleared when the corresponding status register is read, as long as the status condition does not still persist. Signals GEN_IRQ, MODEM_IRQ, and ALARM_IRQ are driven by the logical OR of the of the status bits within the corresponding register. If a status bit is unmasked and the sticky version of that bit has been asserted, and the IRQ is level-sensitive, then an interrupt is triggered as soon as the bit is unmasked. If the IRQ is edge-sensitive then a status event must occur after the bit has been unmasked to assert an interrupt. FIFO flags are not sticky; therefore, an IRQ can be triggered, but the status flag can be deasserted by the time the status information is transmitted at the output. For example, If FIFO_U2H_LEVEL_FLAG is unmasked and the FIFO_U2H level drops below the set threshold, the IRQ triggers. If the device is configured to output UBM IRQ messages and a HART data byte is received on UARTIN after the IRQ, but before the UBM captures the IRQ status, then the IRQ status and data information reads back all zeros. If UBM IRQ mode is used, wait until the IRQ message is fully transmitted on UARTOUT before putting data on UARTIN. IRQ The devices include an interrupt request (IRQ) to communicate the occurrence of a variety of events to the host controller. The IRQ block initiates interrupts that are reported internally in a status register, externally on the IRQ pin if the function is enabled, or on the ALARM pin if the condition is from the ALARM_STATUS register. shows the IRQ block diagram. IRQ Block Diagram There are three registers that can generate interrupts: GEN_STATUS, MODEM_STATUS, and ALARM_STATUS. Each of these registers has a corresponding STATUS_MASK register. The mask register controls which of the events trigger an interrupt. Writing a 1 in the mask register masks, or disables, the event from triggering an interrupt. Writing a 0 in the mask register allows the event to trigger an IRQ. All bits are masked by default. Some status bits are sticky. Reading the corresponding register clears a sticky bit, unless the condition still exists. The IRQ is configured through CONFIG.IRQ_LVL to be edge- or level-sensitive. Set this bit to logic 1 to enable level-sensitive functionality (default). In edge-sensitive mode, the IRQ signal is a synchronous pulse, one internal clock period wide (813 ns). In level-sensitive mode, the IRQ is set and remains set as long as the condition exists. After the IRQ condition is removed, the condition is cleared by reading the corresponding status register. Trying to clear the bit while the condition still exists does not allow the bit to be cleared if the bit is sticky. CONFIG.IRQ_POL determines the active level of the IRQ. A logic 1 configures IRQ to be active high. When using edge-sensitive IRQ signals, there is a clock cycle delay for synchronization and edge detection. With a 307.2-kHz clock, this delay is up to 3.26 μs. For level-sensitive mode, the delay is approximately 10 ns to 20 ns. Most status bits have two versions within the design. The first version is an edge event that is created when the status is asserted. This signal is used to generate edge-sensitive IRQs. This edge detection prevents multiple status events from blocking one another. The second version is the sticky version of the status bit. This signal is set upon assertion of the status bit and cleared when the corresponding status register is read, as long as the status condition does not still persist. Signals GEN_IRQ, MODEM_IRQ, and ALARM_IRQ are driven by the logical OR of the of the status bits within the corresponding register. If a status bit is unmasked and the sticky version of that bit has been asserted, and the IRQ is level-sensitive, then an interrupt is triggered as soon as the bit is unmasked. If the IRQ is edge-sensitive then a status event must occur after the bit has been unmasked to assert an interrupt. FIFO flags are not sticky; therefore, an IRQ can be triggered, but the status flag can be deasserted by the time the status information is transmitted at the output. For example, If FIFO_U2H_LEVEL_FLAG is unmasked and the FIFO_U2H level drops below the set threshold, the IRQ triggers. If the device is configured to output UBM IRQ messages and a HART data byte is received on UARTIN after the IRQ, but before the UBM captures the IRQ status, then the IRQ status and data information reads back all zeros. If UBM IRQ mode is used, wait until the IRQ message is fully transmitted on UARTOUT before putting data on UARTIN. The devices include an interrupt request (IRQ) to communicate the occurrence of a variety of events to the host controller. The IRQ block initiates interrupts that are reported internally in a status register, externally on the IRQ pin if the function is enabled, or on the ALARM pin if the condition is from the ALARM_STATUS register. shows the IRQ block diagram. IRQ Block Diagram There are three registers that can generate interrupts: GEN_STATUS, MODEM_STATUS, and ALARM_STATUS. Each of these registers has a corresponding STATUS_MASK register. The mask register controls which of the events trigger an interrupt. Writing a 1 in the mask register masks, or disables, the event from triggering an interrupt. Writing a 0 in the mask register allows the event to trigger an IRQ. All bits are masked by default. Some status bits are sticky. Reading the corresponding register clears a sticky bit, unless the condition still exists. The IRQ is configured through CONFIG.IRQ_LVL to be edge- or level-sensitive. Set this bit to logic 1 to enable level-sensitive functionality (default). In edge-sensitive mode, the IRQ signal is a synchronous pulse, one internal clock period wide (813 ns). In level-sensitive mode, the IRQ is set and remains set as long as the condition exists. After the IRQ condition is removed, the condition is cleared by reading the corresponding status register. Trying to clear the bit while the condition still exists does not allow the bit to be cleared if the bit is sticky. CONFIG.IRQ_POL determines the active level of the IRQ. A logic 1 configures IRQ to be active high. When using edge-sensitive IRQ signals, there is a clock cycle delay for synchronization and edge detection. With a 307.2-kHz clock, this delay is up to 3.26 μs. For level-sensitive mode, the delay is approximately 10 ns to 20 ns. Most status bits have two versions within the design. The first version is an edge event that is created when the status is asserted. This signal is used to generate edge-sensitive IRQs. This edge detection prevents multiple status events from blocking one another. The second version is the sticky version of the status bit. This signal is set upon assertion of the status bit and cleared when the corresponding status register is read, as long as the status condition does not still persist. Signals GEN_IRQ, MODEM_IRQ, and ALARM_IRQ are driven by the logical OR of the of the status bits within the corresponding register. If a status bit is unmasked and the sticky version of that bit has been asserted, and the IRQ is level-sensitive, then an interrupt is triggered as soon as the bit is unmasked. If the IRQ is edge-sensitive then a status event must occur after the bit has been unmasked to assert an interrupt. FIFO flags are not sticky; therefore, an IRQ can be triggered, but the status flag can be deasserted by the time the status information is transmitted at the output. For example, If FIFO_U2H_LEVEL_FLAG is unmasked and the FIFO_U2H level drops below the set threshold, the IRQ triggers. If the device is configured to output UBM IRQ messages and a HART data byte is received on UARTIN after the IRQ, but before the UBM captures the IRQ status, then the IRQ status and data information reads back all zeros. If UBM IRQ mode is used, wait until the IRQ message is fully transmitted on UARTOUT before putting data on UARTIN. The devices include an interrupt request (IRQ) to communicate the occurrence of a variety of events to the host controller. The IRQ block initiates interrupts that are reported internally in a status register, externally on the IRQ pin if the function is enabled, or on the ALARM pin if the condition is from the ALARM_STATUS register. shows the IRQ block diagram.ALARM IRQ Block Diagram IRQ Block DiagramThere are three registers that can generate interrupts: GEN_STATUS, MODEM_STATUS, and ALARM_STATUS. Each of these registers has a corresponding STATUS_MASK register. The mask register controls which of the events trigger an interrupt. Writing a 1 in the mask register masks, or disables, the event from triggering an interrupt. Writing a 0 in the mask register allows the event to trigger an IRQ. All bits are masked by default. Some status bits are sticky. Reading the corresponding register clears a sticky bit, unless the condition still exists.three, MODEM_STATUS,The IRQ is configured through CONFIG.IRQ_LVL to be edge- or level-sensitive. Set this bit to logic 1 to enable level-sensitive functionality (default). In edge-sensitive mode, the IRQ signal is a synchronous pulse, one internal clock period wide (813 ns). In level-sensitive mode, the IRQ is set and remains set as long as the condition exists. After the IRQ condition is removed, the condition is cleared by reading the corresponding status register. Trying to clear the bit while the condition still exists does not allow the bit to be cleared if the bit is sticky.CONFIG.IRQ_POL determines the active level of the IRQ. A logic 1 configures IRQ to be active high.When using edge-sensitive IRQ signals, there is a clock cycle delay for synchronization and edge detection. With a 307.2-kHz clock, this delay is up to 3.26 μs. For level-sensitive mode, the delay is approximately 10 ns to 20 ns.Most status bits have two versions within the design. The first version is an edge event that is created when the status is asserted. This signal is used to generate edge-sensitive IRQs. This edge detection prevents multiple status events from blocking one another. The second version is the sticky version of the status bit. This signal is set upon assertion of the status bit and cleared when the corresponding status register is read, as long as the status condition does not still persist. Signals GEN_IRQ, MODEM_IRQ, and ALARM_IRQ are driven by the logical OR of the of the status bits within the corresponding register. , MODEM_IRQ,If a status bit is unmasked and the sticky version of that bit has been asserted, and the IRQ is level-sensitive, then an interrupt is triggered as soon as the bit is unmasked. If the IRQ is edge-sensitive then a status event must occur after the bit has been unmasked to assert an interrupt.FIFO flags are not sticky; therefore, an IRQ can be triggered, but the status flag can be deasserted by the time the status information is transmitted at the output. For example, If FIFO_U2H_LEVEL_FLAG is unmasked and the FIFO_U2H level drops below the set threshold, the IRQ triggers. If the device is configured to output UBM IRQ messages and a HART data byte is received on UARTIN after the IRQ, but before the UBM captures the IRQ status, then the IRQ status and data information reads back all zeros. If UBM IRQ mode is used, wait until the IRQ message is fully transmitted on UARTOUT before putting data on UARTIN. HART Interface On the AFEx82H1, a HART frequency-shift keyed (FSK) signal can be modulated onto the MOD_OUT pin. illustrates the output current versus time operation for a typical HART interface. Output Current vs Time DC current = 6 mA To enable the HART interface, set the HART_EN bit in the MODEM_CFG register. An external capacitor, placed in series between the RX_IN pin and HART FSK source, is required to ac-couple the HART FSK signal to the RX_IN pin. The recommended capacitance for this external capacitor is 2.2 nF. If additional filtering is required, the AFEx82H1 also support an external band-pass filter. For this configuration, use the RX_INF pin instead of RX_IN pin. FIFO Buffers First-in, first-out (FIFO) buffers are used to transmit and receive HART data using both the SPI and UART. Both the transmit FIFO (FIFO_U2H) and receive FIFO (FIFO_H2U) buffers are 32 rows and 9-bits wide. The 9-bit width allows the storage of the parity bit with the data byte. Bit[8] is the parity bit as received by either the UART or HART demodulator, depending on the direction of the data flow. The device does not calculate the parity bit in this case, and transmits the data with the wrong parity bit if the wrong parity bit was received. Bits[7:0] are the data. The AFEx82H1 HART implementation is shown in . HART Architecture HART data bytes are enqueued into a transmit FIFO_U2H buffer using the SPI or UART. The input data bits are translated into the mark (1200 Hz) and space (2200 Hz) FSK analog signals (see ) used in HART communication by the internal HART transmit modulator. The receive demodulator enqueues HART data into the receive FIFO_H2U buffer. An arbiter is implemented with signals to CD and from the RTS pins to manage the HART physical connections on MOD_OUT, and either the RX_IN or RX_INF pin. To enable efficient and error-free communication, the arbiter in conjunction with the two FIFO buffers can be used to produce an IRQ for the system controller. An incorrect stop bit in the HART receive character causes a HART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the HART data are not enqueued into FIFO_H2U. If the frame error check is not masked, an IRQ event is also triggered. Similarly, an incorrect stop bit in the UARTIN character causes a UART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the UART data are not enqueued into FIFO_U2H. If the frame error check is not masked, an IRQ event is also triggered. FIFO Buffer Access In SPI only mode, both FIFO buffers are accessed using register addresses. HART bus communication activity is reported to the host controller through the IRQ pin and MODEM_STATUS register. See for recommended IRQ based communication techniques when using the AFEx82H1 to convert between the SPI and HART. Write to the FIFO_U2H_WR register to enqueue the HART transmit data into FIFO_U2H. Calculate the correct parity bit and include the parity bit with the data. Do not attempt to read data from the FIFO_U2H because a read request from the FIFO_U2H_WR register is not supported. The read from the FIFO_U2H_WR register returns the data from the dequeue pointer location of FIFO_U2H, but does not dequeue the data. Read the FIFO_H2U_RD register to dequeue the HART receive data from FIFO_H2U. If CRC is enabled and a CRC error occurs during a read request, no data are dequeued from the FIFO_H2U buffer, and the data in the readback frame are invalid. A write to the FIFO_H2U_RD register is ignored. When communicating with the HART modem through the UART interface in SPI plus UART mode, any character received on the UARTIN pin is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the clear-to-send (CTS) response is asserted. Similarly, any character received on the RX_IN or RX_INF pin is directly enqueued into FIFO_H2U. The character is then automatically dequeued from FIFO_H2U and transmitted on UARTOUT as a normal UART character. The FIFO buffers are accessed directly by the UART; therefore, do not use the FIFO_U2H_WR and FIFO_H2U_RD registers with the SPI. As a result of using FIFO_U2H in the data path, there is a latency from the UARTIN pin to the MOD_OUT pin; see also . Similarly, as a result of using FIFO_H2U, there is a latency from the RX_IN or RX_INF pin to the UARTOUT pin; see also . HART bus communication activity is interfaced to the host controller through the CD and RTS pins. If the CD and RTS pins are not used, poll the MODEM_STATUS register regularly to monitor the status of the modem. In UBM mode, any character received on the UARTIN pin that is not a part of a break command is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the CTS response is asserted. Although the UBM packets can access all registers, do not use the break command to write the HART transmit data into FIFO_U2H_WR register. Use the standard 8O1 UART character format to enqueue data into the FIFO_U2H buffer, and thus to the HART modulator. Similarly, do not use the break command to read the HART receive data from the FIFO_H2U_RD register. HART receive data are automatically dequeued from FIFO_H2U and transmitted on UARTOUT as normal UART characters in UBM mode. FIFO Buffer Flags Status bits exist for both transmit and receive FIFO buffers in the MODEM_STATUS, FIFO_STATUS and FIFO_H2U_RD registers. These include full, empty, and level flags. Buffer level flags are used to trigger IRQs for HART communication; see also . The status fields in the FIFO_H2U_RD register represent the state of FIFO_H2U before the read is performed and the data byte is dequeued. This implementation means that if the EMPTY_ FLAG is set, the data byte received in that frame is invalid. Similarly, the LEVEL field represents the 4 MSBs for the FIFO_H2U level before dequeuing. The LSB is not reported, and there are only five internal bits to represent 32 levels; therefore, the LEVEL = 0 is reported when the actual level is 0, 1, or 32. Use FULL_FLAG and EMPTY_FLAG when LEVEL = 0 to differentiate between these three cases. The FIFO_H2U and FIFO_U2H buffers have 32 levels; however, the level setting for generating IRQ events only uses four bits. For the receive FIFO_H2U buffer, the LSB in the FIFO level threshold comparison is always 1 (FIFO_CFG.H2U_LEVEL_SET[3:0], 1). This configuration is designed to alert the user when FIFO_H2U is getting nearly full so as to enable a timely data dequeue, and prevent the loss of incoming HART data due to FIFO overload. For this reason, the FIFO_H2U_LEVEL_FLAG is also a greater-than (>) comparison to the FIFO_CFG.H2U_LEVEL_SET. For example, if FIFO_CFG.H2U_LEVEL_SET = 4’b1000, then when the level of the FIFO_H2U > 5’b10001, the FIFO_H2U_LEVEL_FLAG is set. Setting FIFO_CFG.H2U_LEVEL_SET = 4’b1111 (default) effectively disables this flag. Use FIFO_H2U_FULL_ FLAG to detect the FIFO_H2U full event. When the FIFO_H2U is full, the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. Similarly, for the transmit FIFO_U2H buffer, the LSB in the FIFO level threshold comparison is always 0 (FIFO_CFG.U2H_LEVEL_SET[3:0], 0). This configuration is designed to alert the user when FIFO_U2H is getting nearly empty so as to enable a timely data enqueue, and prevent FIFO_U2H from becoming empty prematurely and causing a gap error on the HART bus. For this reason, the FIFO_U2H_LEVEL_FLAG is also a less-than (<) comparison with the FIFO_CFG.U2H_LEVEL_SET. For example, if FIFO_CFG.U2H_LEVEL_SET = 4’b1000, then when the level of the FIFO_U2H < 5’b10000, the FIFO_U2H_LEVEL_FLAG is set. Setting FIFO_CFG.U2H_LEVEL_SET = 4’b0000 (default) effectively disables this flag. Use FIFO_U2H_EMPTY_ FLAG to detect the FIFO_U2H empty event. To avoid buffer overflow, monitor the level of FIFO_U2H by watching for a buffer-full or buffer-threshold event. If the FIFO_U2H_LEVEL_FLAG bit in the MODEM_STATUS_MASK register is set to 0, the IRQ pin toggles when the threshold is exceeded. Similarly, an alarm can be triggered based on the FIFO_U2H_FULL_FLAG bit in the MODEM_STATUS register. When the FIFO_U2H is full the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. HART Modulator The HART modulator implements a look-up table (LUT) containing 128, 8-bit, signed values that represent a single-phase, continuous sinusoidal cycle. A counter is implemented that incrementally loads the table values to a DAC at a clock frequency determined by the binary value of the input data. The DAC clock frequency is determined by the logical value of the data bit being transmitted. A logic 1 transmits at the internal clock frequency of 32 (default) steps times 1200 Hz. A logic 0 transmits at the internal clock frequency of 32 (default) steps times 2200 Hz. All frequencies are derived from 1.2288 MHz. This process creates the mark and space analog output signals used to represent HART data. The default mode uses 32 sinusoidal codes per period from the LUT for power savings. To generate a 128-step-per-period sinusoidal signal set MODEM_CFG.TxRES = 1. shows the HART modulator architecture. HART Modulator Architecture HART Demodulator The HART demodulator converts the HART FSK input signals applied at the HART input pins (RX_IN and RX_INF) to binary data that are enqueued into the receive FIFO (FIFO_H2U). Data from the FIFO_H2U can then be dequeued by the host controller using the SPI or output on UARTOUT. shows the HART demodulator architecture. The AFEx82H1 supports two different input bandpass filter modes: internal and external. In internal filter mode, the HART input signal is connected to the RX_IN pin through the high-pass filter capacitor. In this mode, the low-pass filter capacitor is connected to the RX_INF pin. In external filter mode, the band-pass filter is implemented with external components for better flexibility, and the resulting band-pass-filtered signal is connected to the RX_INF pin. In this mode, float the RX_IN pin. Use the MODEM_CFG.RX_EXFILT_EN bit to select between these two modes, depending on the external band-pass filter implementation and HART input signal connection. The input band-pass filter (either fully external or partially internal with external capacitors and internal resistors) is followed by the internal second-order high-pass filter and the internal second-order low-pass filter. To enable the second-order low-pass filter, use the MODEM_CFG.RX_HORD_EN bit. HART Demodulator Architecture The HART demodulator asserts a carrier detect (CD) signal, when a carrier-above-threshold level is detected. Hysteresis is implemented with the carrier-detect feature to prevent erroneous carrier-detection signals. The glitch-free CD signal is available internally to the arbiter and externally to the system controller on the CD pin. HART Modem Modes The HART modulator‑demodulator operates in either half‑duplex or full‑duplex mode. Half-Duplex Mode Half-duplex mode is the main functional mode of operation for the AFEx82H1, in conjunction with the half‑duplex HART protocol. In half-duplex mode, either the modulator or demodulator is active at any given instant, but never simultaneously enabled. By default, the demodulator is active and the modulator is inactive. When using half-duplex mode, the modem arbitrates when modulator and demodulator are active. For more details, see . Full-Duplex Mode In full‑duplex mode, the modulator and demodulator are simultaneously enabled. This configuration allows a self‑test feature to verify functionality of the transmit and receive signal chains to improve system diagnostics. There are internal and external full-duplex modes. In internal full-duplex mode, the MOD_OUT pin is internally shorted to the RX_INF pin. Set MODEM_CFG.DUPLEX = 1 to enable an internal connection between the HART transmitter and receiver to verify communication. In external full-duplex mode, the HART modulator and demodulator are enabled, but the MOD_OUT pin is not internally shorted to the RX_IN or RX_INF pins. To enable the external full‑duplex mode, short MOD_OUT to RX_IN or RX_INF pins externally, and set MODEM_CFG.DUPLEX_EXT = 1. HART Modulation and Demodulation Arbitration In half‑duplex HART-protocol mode, the device arbitrates when the modulator and demodulator are active, based on activity on the HART bus. The system controller has various means of monitoring and interacting with the AFEx82H1. For the methods used in SPI mode, see . For the reporting method used in UART mode, see . In the default idle state, the RTS pin is high (inactive), and the CD pin is low. The demodulator is active and the modulator is inactive. HART Receive Mode When a carrier is detected, the CD pin toggles high, and data bytes received by the modem are automatically enqueued into FIFO_H2U. This mode is the highest priority, and the device continues to remain in this mode as long as a valid carrier is present. The system controller must timely dequeue the data from the FIFO_H2U as long as CD remains high and the demodulator enqueues new data into FIFO_H2U. CD is deasserted when the level of the incoming carrier is reduced to less than the HART specification. For receive operation timing details, see . HART Transmit Mode To transmit the HART data, issue a request to send (RTS) either by toggling the RTS pin low or asserting MODEM_CFG.RTS, depending on the selected communication setup. When the HART bus is available for transmission and no carrier is detected, the device deasserts the CD pin, disables the demodulator, asserts the CTS response by setting MODEM_STATUS.CTS_ASSERT = 1, and begins modulating the carrier. If the CD pin is used, wait for the CD pin to be deasserted. Otherwise, unmask CTS_ASSERT and set up the appropriate IRQs for the FIFO_U2H levels and CTS flags to enable the system controller to receive an IRQ when CTS is asserted. See also . When the CD pin and IRQ are not used, poll the MODEM_STATUS register regularly to detect when the CTS response is asserted. As long as the CD pin is asserted, the demodulator remains active and the RTS request is held pending by the arbiter. Any HART transmit data bytes received by the AFEx82H1 are enqueued into FIFO_U2H, but not transmitted immediately. The system controller must monitor the FIFO_U2H level to avoid buffer overflow in this condition. When the CTS response is asserted, the data enqueued into FIFO_U2H are dequeued and transmitted onto the MOD_OUT pin. If no data are enqueued into FIFO_U2H, the modulator starts transmitting the mark signal. The beginning of the bit stream must meet the minimum bit times requirement to make sure there is enough time for successful detection of the mark-to-space transition on the receiving side; see also . The system controller is then required to maintain adequate an FIFO_U2H buffer level to avoid gap errors and deassert the RTS at the end of bit stream with the correct timing delays; see also . HART Modulator Timing and Preamble Requirements The HART modulator starts modulating the carrier as soon as the CTS response is asserted. If data are enqueued into FIFO_U2H before the CTS is asserted, make sure to enqueue the required preamble bytes at the beginning of the data packet in accordance with . The first byte is used by the HART recipient receiver to recognize the carrier and properly detect the mark-to-space transition of the start bit in the second character. Alternatively, wait for CTS_ASSERT, and give an appropriate delay while the modulator is transmitting the mark signal. Then enqueue the preamble bytes followed by the data bytes into FIFO_U2H. Monitor the level of FIFO_U2H and timely enqueue the new data to avoid transmission gap errors. Carrier Detect and Preamble HART REQUIREMENT FIFO_U2H STATE AFEx82H1 BEHAVIOR RECOMMENDED USE CASE Transmit at least 6 bit times of HART signal of specified amplitude for the carrier to be detected by the receiver. FIFO_U2H is empty. HART modulator starts sending mark FSK signal as soon as CTS is asserted. Wait at least 6 bit times from CTS assert before transmitting first preamble byte. Calculate the time to enqueue the data into FIFO_U2H based on the interface mode used. FIFO_U2H is preloaded with data. HART modulator starts sending FIFO_U2H data as soon as CTS is asserted. Preload FIFO_U2H with one additional preamble byte. Depending on the interface mode, there is a latency from the UARTIN or CS pin to the MOD_OUT pin as a result of using FIFO_U2H in the data path. In the SPI plus UART and UBM modes, a delay of approximately 1.5 bit times (1.5 × tBAUDUART) occurs from the stop bit on the UARTIN pin until the data are enqueued into FIFO_U2H as a result of data decoding and synchronization. shows this timing. HART Transmit Start Timing Diagram (UART Mode) In SPI only mode, the HART transmit data are enqueued into FIFO_U2H using FIFO_U2H_WR register. Therefore, in this mode, take the standard SPI timing into consideration while calculating the latency of the HART transmit data from the CS pin to the MOD_OUT pin. shows the HART transmit start timing for SPI mode. HART Transmit Start Timing Diagram (SPI Mode) The HART character contains 11 bits; therefore, a delay of approximately 11 bit times (11 × tBAUDHART) occurs from the moment the data are dequeued from FIFO_U2H until the data are fully transmitted on the MOD_OUT pin (see ). Additional delay is accumulated when there is a frequency mismatch between the incoming UART_IN data and the HART data transmitted on MOD_OUT. If the UART_IN data frequency is 2% greater compared to the MOD_OUT data frequency, a delay of approximately 1 bit time is accumulated every five HART characters. Add a gap of at least 1 bit time between every five HART characters to account for this latency. Keep the request to send (RTS) asserted until the data are fully transmitted on MOD_OUT. HART Transmit End Timing Diagram (UBM, UART Plus SPI Modes) HART Demodulator Timing and Preamble Requirements The RX_IN and RX_INF pins are continuously monitored by the HART demodulator when not transmitting. AFEx82H1 requires at least 3 mark bits (3 × tBAUDHART) of 1200 Hz for carrier detection. For UART-based communication setup, the HART data are automatically dequeued from FIFO_H2U and transmitted on the UARTOUT pin as UART characters. A delay of approximately 1.5 bit times (1.5 × tBAUDHART) occurs as a result of data decoding and synchronization from the end of the character on RX_IN or RX_INF pin until the data are enqueued into FIFO_H2U. Thus, when CD deasserts, there is typically still one UART character pending transfer to the system controller on UARTOUT (see ). FIFO latency is as low as a few microseconds when using the SPI to dequeue the data from FIFO_H2U by reading FIFO_H2U_RD register. and show the timing diagrams for the start and end of the HART receive character, respectively. HART Receive Start Timing Diagram (SPI and UART Modes) HART Receive End Timing Diagram (UART Mode) IRQ Configuration for HART Communication To enable robust and error-free communicate on the HART bus, the events listed in #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/TABLE_BCL_BCQ_PQB must be detected from the AFEx82H1 by the system controller in a timely manner. If the IRQ signal is not directly connected to the system controller, poll the corresponding status flags. In UART mode, the automatic dequeue of FIFO_H2U simplifies event management significantly, and not all events must be translated to IRQs. When using the HART modem with the IRQ, the IRQ features help control communication in both directions. Enable IRQ functionality by following these steps: Configure the IRQ to be either edge or level sensitive using CONFIG.IRQ_LVL. See also . Configure the IRQ polarity with CONFIG.IRQ_POL, as needed per the respective system. See also . For SPI only mode, set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the UARTOUT pin. Also, set CONFIG.UART_DIS = 1 to disable all UART functionality. For UBM, use one of the two following methods: Set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the SDO pin, or Set CONFIG.UBM_IRQ_EN = 1 to enable interrupts being sent UARTOUT using UBM. After IRQ functionality is enabled, unmask all the required interrupt signals in the MODEM_STATUS_MASK register (set each bit = 0). IRQ Sources and Uses AFEx82H1HART STATE EVENT MODEM_STATUS FLAG ASSERTION METHOD #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWB ACTION Receive RTS deasserted CTS_DEASSERT Toggle RTS pin high or set MODEM_CFG.RTS = 0. Demodulator enabled and ready to receive HART data. Carrier detect asserted CD_ASSERT Demodulator detects the HART carrier signal of valid amplitude. Expect to receive HART data. Set desired FIFO_H2U level trigger threshold. FIFO_H2U level threshold trigger FIFO_H2U_LEVEL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. Dequeue data from FIFO_H2U when level exceeds the set threshold. Prevent FIFO_H2U from being full to avoid the loss of incoming data. FIFO_H2U full FIFO_H2U_FULL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. System controller has not dequeued FIFO_H2U. Critical flag. Dequeue FIFO_H2U immediately to avoid the loss of incoming data. Carrier detect deasserted CD_DEASSERT Demodulator stops detecting the HART carrier signal of valid amplitude. Dequeue remaining data from FIFO_H2U. Monitor the empty flag to make sure that all data have been received. FIFO_H2U empty FIFO_H2U_EMPTY_FLAG Dequeue of FIFO_H2U by system controller. If using UART, wait to make sure the last character is received on UARTOUT. Transmit RTS asserted NA Toggle RTS pin low or write set MODEM_CFG.RTS = 1. Wait for clear-to-send confirmation flag. Clear to send (CTS) CTS_ASSERT RTS asserted and CD deasserted. Modulator enabled. Device starts modulating the carrier on MOD_OUT. Set desired FIFO_U2H level trigger threshold. Enqueue data into FIFO_U2H. Modulator automatically dequeues FIFO_U2H and transmits the HART data. FIFO_U2H level threshold trigger FIFO_U2H_LEVEL_FLAG Automatic dequeue of FIFO_U2H by HART modulator. Enqueue new data into FIFO_U2H when the level drops below the set threshold. Prevent FIFO_U2H from being empty to avoid a gap in transmission. FIFO_U2H full FIFO_U2H_FULL_FLAG System controller enqueue of the new data into FIFO_U2H. Critical flag.Stop enqueue of data into FIFO_U2H immediately to avoid loss of HART data. FIFO_U2H empty FIFO_U2H_EMPTY_FLAG Automatic dequeue of FIFO_U2H by HART modulator. System controller has not enqueued new data into FIFO_U2H. Critical flag in the middle of the data packet.Enqueue new data into FIFO_U2H immediately to avoid a gap in transmission. When the last character is dequeued from FIFO_U2H, wait until the character is fully transmitted on MOD_OUT before deasserting RTS. For CD, RTS, ALARM, and IRQ connection choices, see . HART Communication Using the SPI HART bus communication activity is reported to the host controller through the IRQ signal routed to the UARTOUT pin and MODEM_STATUS register. Read the MODEM_STATUS register to determine the source of the IRQ when an IRQ is received. If the UARTOUT pin is not connected, poll the status registers regularly through the SPI. To transmit data, set up the desired FIFO_U2H level thresholds using FIFO_CFG.U2H_LEVEL_SET. Assert the RTS. After CTS_ASSERT is set, begin to fill FIFO_U2H. Enqueue enough data into FIFO_U2H to fill the FIFO above the set threshold level. The HART modulator automatically dequeues the data from FIFO_U2H and transmits the data on MOD_OUT. When FIFO_U2H level drops below the set threshold, an IRQ triggers, indicating that new data bytes can be enqueued without losing any data. After the last set of data have been enqueued into FIFO_U2H, an IRQ event triggered by the level flag can be ignored. Wait for the IRQ event triggered by FIFO_U2H_EMPTY_FLAG. Deassert the RTS after required delay; see also . When the RTS is deasserted, the CTS_DEASSERT bit is set. CTS_DEASSERT is an informational bit. To receive data, set up an IRQ event based on CD_ASSERT to know when the carrier is detected and the new data bytes are expected. Also, set up the additional IRQ events to trigger each time FIFO_H2U_LEVEL_FLAG is set. Select the desired level of FIFO_H2U. Dequeue the data from FIFO_H2U every time the level exceeds the set threshold. Also, set up IRQ event trigger based on CD_DEASSERT to know when all the data have been received. At this point, monitor FIFO_H2U.EMPTY_FLAG when dequeuing each character to know when FIFO_H2U is empty and all the data bytes have been dequeued and transmitted to the microcontroller. Alternatively, the CD pin can be directly connected to the microcontroller to monitor the status of the HART bus. In this configuration, mask CD_ASSERT flag by setting MODEM_STATUS_MASK.CD_ASSERT bit = 1 to prevent CD_ASSERT from generating an IRQ event. HART Communication Using UART In SPI plus UART mode, the UART data are transmitted and received at 1200 baud, which is matched to the HART FSK input and output signals. Both SDO and UARTOUT pins are used; therefore, the IRQ functionality is not available in SPI plus UART mode. FIFO_H2U level monitoring is not required because any HART data received by the demodulator and enqueued into FIFO_H2U are automatically dequeued and transmitted on UARTOUT. FIFO_U2H level monitoring is also not required if HART bus communication activity is interfaced to the host controller through the CD and RTS pins. The host controller can properly time the RTS pin to transmit the HART data when no carrier is detected on the bus. If the CD and RTS pins are not used in SPI plus UART mode, the host controller can periodically poll the MODEM_STATUS register through the SPI to detect when the carrier is not present on the HART bus, and assert the request to send by setting MODEM_CFG.RTS bit = 1. In UBM, the UART data are transmitted and received at 9600 baud. The HART data characters are interleaved with break commands for register map access or interrupt reporting; see also . Similar to SPI plus UART mode, monitoring of FIFO_H2U and FIFO_U2H levels is not required. The CD and RTS pins are available to interface the HART bus activity with the microcontroller. IRQ functionality is also available on the SDO pin. If the SDO pin is connected to the microcontroller, the IRQ event based on CD_ASSERT can be set to report when the carrier is detected. In this case, CD pin connection to the microcontroller is not required. Similarly, RTS pin connection is not required if MODEM_CFG.RTS is used to issue a request to send. The SDO pin connection to the microcontroller is also not required if the microcontroller can periodically poll the MODEM_STATUS register using break commands, and monitor all the required flags. Memory Built-In Self-Test (MBIST) Memory built-in self-test (MBIST) verifies the validity of the static random-access memory (SRAM) used for the FIFO buffers. When initiated, the MBIST takes control of the SRAM module until completion. Disable HART communication while the MBIST is running. Communication with the FIFO buffers during the MBIST produces unreliable results. Two status bits, GEN_STATUS.MBIST_DONE and GEN_STATUS.MBIST_FAIL, can be monitored for completion or failure, or used to create IRQ events. Do not try to read back the GEN_STATUS register while the MBIST is running. The MBIST control logic generates narrow pulses for the MBIST_DONE and MBIST_FAIL status flags. The status flags can be missed if these pulses occur during the readback of the GEN_STATUS register. To avoid missing the MBIST_DONE flag, mask all the status bits except GEN_STATUS_MASK.MBIST_DONE and then either: monitor for an IRQ event, or periodically send a NOP and check the GEN_IRQ status bit. Wait until MBIST_DONE is reported, verify the status of the MBIST_FAIL flag, and then resume normal operation. HART Interface On the AFEx82H1, a HART frequency-shift keyed (FSK) signal can be modulated onto the MOD_OUT pin. illustrates the output current versus time operation for a typical HART interface. Output Current vs Time DC current = 6 mA To enable the HART interface, set the HART_EN bit in the MODEM_CFG register. An external capacitor, placed in series between the RX_IN pin and HART FSK source, is required to ac-couple the HART FSK signal to the RX_IN pin. The recommended capacitance for this external capacitor is 2.2 nF. If additional filtering is required, the AFEx82H1 also support an external band-pass filter. For this configuration, use the RX_INF pin instead of RX_IN pin. On the AFEx82H1, a HART frequency-shift keyed (FSK) signal can be modulated onto the MOD_OUT pin. illustrates the output current versus time operation for a typical HART interface. Output Current vs Time DC current = 6 mA To enable the HART interface, set the HART_EN bit in the MODEM_CFG register. An external capacitor, placed in series between the RX_IN pin and HART FSK source, is required to ac-couple the HART FSK signal to the RX_IN pin. The recommended capacitance for this external capacitor is 2.2 nF. If additional filtering is required, the AFEx82H1 also support an external band-pass filter. For this configuration, use the RX_INF pin instead of RX_IN pin. On the AFEx82H1, a HART frequency-shift keyed (FSK) signal can be modulated onto the MOD_OUT pin. illustrates the output current versus time operation for a typical HART interface.AFEx82H1 Output Current vs Time DC current = 6 mA Output Current vs Time DC current = 6 mA DC current = 6 mA DC current = 6 mA DC current = 6 mA DC current = 6 mA DC current = 6 mATo enable the HART interface, set the HART_EN bit in the MODEM_CFG register. An external capacitor, placed in series between the RX_IN pin and HART FSK source, is required to ac-couple the HART FSK signal to the RX_IN pin. The recommended capacitance for this external capacitor is 2.2 nF. If additional filtering is required, the AFEx82H1 also support an external band-pass filter. For this configuration, use the RX_INF pin instead of RX_IN pin.AFEx82H1 FIFO Buffers First-in, first-out (FIFO) buffers are used to transmit and receive HART data using both the SPI and UART. Both the transmit FIFO (FIFO_U2H) and receive FIFO (FIFO_H2U) buffers are 32 rows and 9-bits wide. The 9-bit width allows the storage of the parity bit with the data byte. Bit[8] is the parity bit as received by either the UART or HART demodulator, depending on the direction of the data flow. The device does not calculate the parity bit in this case, and transmits the data with the wrong parity bit if the wrong parity bit was received. Bits[7:0] are the data. The AFEx82H1 HART implementation is shown in . HART Architecture HART data bytes are enqueued into a transmit FIFO_U2H buffer using the SPI or UART. The input data bits are translated into the mark (1200 Hz) and space (2200 Hz) FSK analog signals (see ) used in HART communication by the internal HART transmit modulator. The receive demodulator enqueues HART data into the receive FIFO_H2U buffer. An arbiter is implemented with signals to CD and from the RTS pins to manage the HART physical connections on MOD_OUT, and either the RX_IN or RX_INF pin. To enable efficient and error-free communication, the arbiter in conjunction with the two FIFO buffers can be used to produce an IRQ for the system controller. An incorrect stop bit in the HART receive character causes a HART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the HART data are not enqueued into FIFO_H2U. If the frame error check is not masked, an IRQ event is also triggered. Similarly, an incorrect stop bit in the UARTIN character causes a UART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the UART data are not enqueued into FIFO_U2H. If the frame error check is not masked, an IRQ event is also triggered. FIFO Buffer Access In SPI only mode, both FIFO buffers are accessed using register addresses. HART bus communication activity is reported to the host controller through the IRQ pin and MODEM_STATUS register. See for recommended IRQ based communication techniques when using the AFEx82H1 to convert between the SPI and HART. Write to the FIFO_U2H_WR register to enqueue the HART transmit data into FIFO_U2H. Calculate the correct parity bit and include the parity bit with the data. Do not attempt to read data from the FIFO_U2H because a read request from the FIFO_U2H_WR register is not supported. The read from the FIFO_U2H_WR register returns the data from the dequeue pointer location of FIFO_U2H, but does not dequeue the data. Read the FIFO_H2U_RD register to dequeue the HART receive data from FIFO_H2U. If CRC is enabled and a CRC error occurs during a read request, no data are dequeued from the FIFO_H2U buffer, and the data in the readback frame are invalid. A write to the FIFO_H2U_RD register is ignored. When communicating with the HART modem through the UART interface in SPI plus UART mode, any character received on the UARTIN pin is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the clear-to-send (CTS) response is asserted. Similarly, any character received on the RX_IN or RX_INF pin is directly enqueued into FIFO_H2U. The character is then automatically dequeued from FIFO_H2U and transmitted on UARTOUT as a normal UART character. The FIFO buffers are accessed directly by the UART; therefore, do not use the FIFO_U2H_WR and FIFO_H2U_RD registers with the SPI. As a result of using FIFO_U2H in the data path, there is a latency from the UARTIN pin to the MOD_OUT pin; see also . Similarly, as a result of using FIFO_H2U, there is a latency from the RX_IN or RX_INF pin to the UARTOUT pin; see also . HART bus communication activity is interfaced to the host controller through the CD and RTS pins. If the CD and RTS pins are not used, poll the MODEM_STATUS register regularly to monitor the status of the modem. In UBM mode, any character received on the UARTIN pin that is not a part of a break command is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the CTS response is asserted. Although the UBM packets can access all registers, do not use the break command to write the HART transmit data into FIFO_U2H_WR register. Use the standard 8O1 UART character format to enqueue data into the FIFO_U2H buffer, and thus to the HART modulator. Similarly, do not use the break command to read the HART receive data from the FIFO_H2U_RD register. HART receive data are automatically dequeued from FIFO_H2U and transmitted on UARTOUT as normal UART characters in UBM mode. FIFO Buffer Flags Status bits exist for both transmit and receive FIFO buffers in the MODEM_STATUS, FIFO_STATUS and FIFO_H2U_RD registers. These include full, empty, and level flags. Buffer level flags are used to trigger IRQs for HART communication; see also . The status fields in the FIFO_H2U_RD register represent the state of FIFO_H2U before the read is performed and the data byte is dequeued. This implementation means that if the EMPTY_ FLAG is set, the data byte received in that frame is invalid. Similarly, the LEVEL field represents the 4 MSBs for the FIFO_H2U level before dequeuing. The LSB is not reported, and there are only five internal bits to represent 32 levels; therefore, the LEVEL = 0 is reported when the actual level is 0, 1, or 32. Use FULL_FLAG and EMPTY_FLAG when LEVEL = 0 to differentiate between these three cases. The FIFO_H2U and FIFO_U2H buffers have 32 levels; however, the level setting for generating IRQ events only uses four bits. For the receive FIFO_H2U buffer, the LSB in the FIFO level threshold comparison is always 1 (FIFO_CFG.H2U_LEVEL_SET[3:0], 1). This configuration is designed to alert the user when FIFO_H2U is getting nearly full so as to enable a timely data dequeue, and prevent the loss of incoming HART data due to FIFO overload. For this reason, the FIFO_H2U_LEVEL_FLAG is also a greater-than (>) comparison to the FIFO_CFG.H2U_LEVEL_SET. For example, if FIFO_CFG.H2U_LEVEL_SET = 4’b1000, then when the level of the FIFO_H2U > 5’b10001, the FIFO_H2U_LEVEL_FLAG is set. Setting FIFO_CFG.H2U_LEVEL_SET = 4’b1111 (default) effectively disables this flag. Use FIFO_H2U_FULL_ FLAG to detect the FIFO_H2U full event. When the FIFO_H2U is full, the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. Similarly, for the transmit FIFO_U2H buffer, the LSB in the FIFO level threshold comparison is always 0 (FIFO_CFG.U2H_LEVEL_SET[3:0], 0). This configuration is designed to alert the user when FIFO_U2H is getting nearly empty so as to enable a timely data enqueue, and prevent FIFO_U2H from becoming empty prematurely and causing a gap error on the HART bus. For this reason, the FIFO_U2H_LEVEL_FLAG is also a less-than (<) comparison with the FIFO_CFG.U2H_LEVEL_SET. For example, if FIFO_CFG.U2H_LEVEL_SET = 4’b1000, then when the level of the FIFO_U2H < 5’b10000, the FIFO_U2H_LEVEL_FLAG is set. Setting FIFO_CFG.U2H_LEVEL_SET = 4’b0000 (default) effectively disables this flag. Use FIFO_U2H_EMPTY_ FLAG to detect the FIFO_U2H empty event. To avoid buffer overflow, monitor the level of FIFO_U2H by watching for a buffer-full or buffer-threshold event. If the FIFO_U2H_LEVEL_FLAG bit in the MODEM_STATUS_MASK register is set to 0, the IRQ pin toggles when the threshold is exceeded. Similarly, an alarm can be triggered based on the FIFO_U2H_FULL_FLAG bit in the MODEM_STATUS register. When the FIFO_U2H is full the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. FIFO Buffers First-in, first-out (FIFO) buffers are used to transmit and receive HART data using both the SPI and UART. Both the transmit FIFO (FIFO_U2H) and receive FIFO (FIFO_H2U) buffers are 32 rows and 9-bits wide. The 9-bit width allows the storage of the parity bit with the data byte. Bit[8] is the parity bit as received by either the UART or HART demodulator, depending on the direction of the data flow. The device does not calculate the parity bit in this case, and transmits the data with the wrong parity bit if the wrong parity bit was received. Bits[7:0] are the data. The AFEx82H1 HART implementation is shown in . HART Architecture HART data bytes are enqueued into a transmit FIFO_U2H buffer using the SPI or UART. The input data bits are translated into the mark (1200 Hz) and space (2200 Hz) FSK analog signals (see ) used in HART communication by the internal HART transmit modulator. The receive demodulator enqueues HART data into the receive FIFO_H2U buffer. An arbiter is implemented with signals to CD and from the RTS pins to manage the HART physical connections on MOD_OUT, and either the RX_IN or RX_INF pin. To enable efficient and error-free communication, the arbiter in conjunction with the two FIFO buffers can be used to produce an IRQ for the system controller. An incorrect stop bit in the HART receive character causes a HART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the HART data are not enqueued into FIFO_H2U. If the frame error check is not masked, an IRQ event is also triggered. Similarly, an incorrect stop bit in the UARTIN character causes a UART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the UART data are not enqueued into FIFO_U2H. If the frame error check is not masked, an IRQ event is also triggered. First-in, first-out (FIFO) buffers are used to transmit and receive HART data using both the SPI and UART. Both the transmit FIFO (FIFO_U2H) and receive FIFO (FIFO_H2U) buffers are 32 rows and 9-bits wide. The 9-bit width allows the storage of the parity bit with the data byte. Bit[8] is the parity bit as received by either the UART or HART demodulator, depending on the direction of the data flow. The device does not calculate the parity bit in this case, and transmits the data with the wrong parity bit if the wrong parity bit was received. Bits[7:0] are the data. The AFEx82H1 HART implementation is shown in . HART Architecture HART data bytes are enqueued into a transmit FIFO_U2H buffer using the SPI or UART. The input data bits are translated into the mark (1200 Hz) and space (2200 Hz) FSK analog signals (see ) used in HART communication by the internal HART transmit modulator. The receive demodulator enqueues HART data into the receive FIFO_H2U buffer. An arbiter is implemented with signals to CD and from the RTS pins to manage the HART physical connections on MOD_OUT, and either the RX_IN or RX_INF pin. To enable efficient and error-free communication, the arbiter in conjunction with the two FIFO buffers can be used to produce an IRQ for the system controller. An incorrect stop bit in the HART receive character causes a HART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the HART data are not enqueued into FIFO_H2U. If the frame error check is not masked, an IRQ event is also triggered. Similarly, an incorrect stop bit in the UARTIN character causes a UART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the UART data are not enqueued into FIFO_U2H. If the frame error check is not masked, an IRQ event is also triggered. First-in, first-out (FIFO) buffers are used to transmit and receive HART data using both the SPI and UART. Both the transmit FIFO (FIFO_U2H) and receive FIFO (FIFO_H2U) buffers are 32 rows and 9-bits wide. The 9-bit width allows the storage of the parity bit with the data byte. Bit[8] is the parity bit as received by either the UART or HART demodulator, depending on the direction of the data flow. The device does not calculate the parity bit in this case, and transmits the data with the wrong parity bit if the wrong parity bit was received. Bits[7:0] are the data.The AFEx82H1 HART implementation is shown in .AFEx82H1 HART Architecture HART ArchitectureHART data bytes are enqueued into a transmit FIFO_U2H buffer using the SPI or UART. The input data bits are translated into the mark (1200 Hz) and space (2200 Hz) FSK analog signals (see ) used in HART communication by the internal HART transmit modulator. The receive demodulator enqueues HART data into the receive FIFO_H2U buffer. An arbiter is implemented with signals to CD and from the RTS pins to manage the HART physical connections on MOD_OUT, and either the RX_IN or RX_INF pin. To enable efficient and error-free communication, the arbiter in conjunction with the two FIFO buffers can be used to produce an IRQ for the system controller.markspaceRTSAn incorrect stop bit in the HART receive character causes a HART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the HART data are not enqueued into FIFO_H2U. If the frame error check is not masked, an IRQ event is also triggered.Similarly, an incorrect stop bit in the UARTIN character causes a UART frame error. The device reports the frame error in the status register and discards the character. When the character is discarded, the UART data are not enqueued into FIFO_U2H. If the frame error check is not masked, an IRQ event is also triggered. FIFO Buffer Access In SPI only mode, both FIFO buffers are accessed using register addresses. HART bus communication activity is reported to the host controller through the IRQ pin and MODEM_STATUS register. See for recommended IRQ based communication techniques when using the AFEx82H1 to convert between the SPI and HART. Write to the FIFO_U2H_WR register to enqueue the HART transmit data into FIFO_U2H. Calculate the correct parity bit and include the parity bit with the data. Do not attempt to read data from the FIFO_U2H because a read request from the FIFO_U2H_WR register is not supported. The read from the FIFO_U2H_WR register returns the data from the dequeue pointer location of FIFO_U2H, but does not dequeue the data. Read the FIFO_H2U_RD register to dequeue the HART receive data from FIFO_H2U. If CRC is enabled and a CRC error occurs during a read request, no data are dequeued from the FIFO_H2U buffer, and the data in the readback frame are invalid. A write to the FIFO_H2U_RD register is ignored. When communicating with the HART modem through the UART interface in SPI plus UART mode, any character received on the UARTIN pin is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the clear-to-send (CTS) response is asserted. Similarly, any character received on the RX_IN or RX_INF pin is directly enqueued into FIFO_H2U. The character is then automatically dequeued from FIFO_H2U and transmitted on UARTOUT as a normal UART character. The FIFO buffers are accessed directly by the UART; therefore, do not use the FIFO_U2H_WR and FIFO_H2U_RD registers with the SPI. As a result of using FIFO_U2H in the data path, there is a latency from the UARTIN pin to the MOD_OUT pin; see also . Similarly, as a result of using FIFO_H2U, there is a latency from the RX_IN or RX_INF pin to the UARTOUT pin; see also . HART bus communication activity is interfaced to the host controller through the CD and RTS pins. If the CD and RTS pins are not used, poll the MODEM_STATUS register regularly to monitor the status of the modem. In UBM mode, any character received on the UARTIN pin that is not a part of a break command is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the CTS response is asserted. Although the UBM packets can access all registers, do not use the break command to write the HART transmit data into FIFO_U2H_WR register. Use the standard 8O1 UART character format to enqueue data into the FIFO_U2H buffer, and thus to the HART modulator. Similarly, do not use the break command to read the HART receive data from the FIFO_H2U_RD register. HART receive data are automatically dequeued from FIFO_H2U and transmitted on UARTOUT as normal UART characters in UBM mode. FIFO Buffer Access In SPI only mode, both FIFO buffers are accessed using register addresses. HART bus communication activity is reported to the host controller through the IRQ pin and MODEM_STATUS register. See for recommended IRQ based communication techniques when using the AFEx82H1 to convert between the SPI and HART. Write to the FIFO_U2H_WR register to enqueue the HART transmit data into FIFO_U2H. Calculate the correct parity bit and include the parity bit with the data. Do not attempt to read data from the FIFO_U2H because a read request from the FIFO_U2H_WR register is not supported. The read from the FIFO_U2H_WR register returns the data from the dequeue pointer location of FIFO_U2H, but does not dequeue the data. Read the FIFO_H2U_RD register to dequeue the HART receive data from FIFO_H2U. If CRC is enabled and a CRC error occurs during a read request, no data are dequeued from the FIFO_H2U buffer, and the data in the readback frame are invalid. A write to the FIFO_H2U_RD register is ignored. When communicating with the HART modem through the UART interface in SPI plus UART mode, any character received on the UARTIN pin is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the clear-to-send (CTS) response is asserted. Similarly, any character received on the RX_IN or RX_INF pin is directly enqueued into FIFO_H2U. The character is then automatically dequeued from FIFO_H2U and transmitted on UARTOUT as a normal UART character. The FIFO buffers are accessed directly by the UART; therefore, do not use the FIFO_U2H_WR and FIFO_H2U_RD registers with the SPI. As a result of using FIFO_U2H in the data path, there is a latency from the UARTIN pin to the MOD_OUT pin; see also . Similarly, as a result of using FIFO_H2U, there is a latency from the RX_IN or RX_INF pin to the UARTOUT pin; see also . HART bus communication activity is interfaced to the host controller through the CD and RTS pins. If the CD and RTS pins are not used, poll the MODEM_STATUS register regularly to monitor the status of the modem. In UBM mode, any character received on the UARTIN pin that is not a part of a break command is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the CTS response is asserted. Although the UBM packets can access all registers, do not use the break command to write the HART transmit data into FIFO_U2H_WR register. Use the standard 8O1 UART character format to enqueue data into the FIFO_U2H buffer, and thus to the HART modulator. Similarly, do not use the break command to read the HART receive data from the FIFO_H2U_RD register. HART receive data are automatically dequeued from FIFO_H2U and transmitted on UARTOUT as normal UART characters in UBM mode. In SPI only mode, both FIFO buffers are accessed using register addresses. HART bus communication activity is reported to the host controller through the IRQ pin and MODEM_STATUS register. See for recommended IRQ based communication techniques when using the AFEx82H1 to convert between the SPI and HART. Write to the FIFO_U2H_WR register to enqueue the HART transmit data into FIFO_U2H. Calculate the correct parity bit and include the parity bit with the data. Do not attempt to read data from the FIFO_U2H because a read request from the FIFO_U2H_WR register is not supported. The read from the FIFO_U2H_WR register returns the data from the dequeue pointer location of FIFO_U2H, but does not dequeue the data. Read the FIFO_H2U_RD register to dequeue the HART receive data from FIFO_H2U. If CRC is enabled and a CRC error occurs during a read request, no data are dequeued from the FIFO_H2U buffer, and the data in the readback frame are invalid. A write to the FIFO_H2U_RD register is ignored. When communicating with the HART modem through the UART interface in SPI plus UART mode, any character received on the UARTIN pin is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the clear-to-send (CTS) response is asserted. Similarly, any character received on the RX_IN or RX_INF pin is directly enqueued into FIFO_H2U. The character is then automatically dequeued from FIFO_H2U and transmitted on UARTOUT as a normal UART character. The FIFO buffers are accessed directly by the UART; therefore, do not use the FIFO_U2H_WR and FIFO_H2U_RD registers with the SPI. As a result of using FIFO_U2H in the data path, there is a latency from the UARTIN pin to the MOD_OUT pin; see also . Similarly, as a result of using FIFO_H2U, there is a latency from the RX_IN or RX_INF pin to the UARTOUT pin; see also . HART bus communication activity is interfaced to the host controller through the CD and RTS pins. If the CD and RTS pins are not used, poll the MODEM_STATUS register regularly to monitor the status of the modem. In UBM mode, any character received on the UARTIN pin that is not a part of a break command is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the CTS response is asserted. Although the UBM packets can access all registers, do not use the break command to write the HART transmit data into FIFO_U2H_WR register. Use the standard 8O1 UART character format to enqueue data into the FIFO_U2H buffer, and thus to the HART modulator. Similarly, do not use the break command to read the HART receive data from the FIFO_H2U_RD register. HART receive data are automatically dequeued from FIFO_H2U and transmitted on UARTOUT as normal UART characters in UBM mode. In SPI only mode, both FIFO buffers are accessed using register addresses. HART bus communication activity is reported to the host controller through the IRQ pin and MODEM_STATUS register. See for recommended IRQ based communication techniques when using the AFEx82H1 to convert between the SPI and HART. AFEx82H1Write to the FIFO_U2H_WR register to enqueue the HART transmit data into FIFO_U2H. Calculate the correct parity bit and include the parity bit with the data. Do not attempt to read data from the FIFO_U2H because a read request from the FIFO_U2H_WR register is not supported. The read from the FIFO_U2H_WR register returns the data from the dequeue pointer location of FIFO_U2H, but does not dequeue the data.Read the FIFO_H2U_RD register to dequeue the HART receive data from FIFO_H2U. If CRC is enabled and a CRC error occurs during a read request, no data are dequeued from the FIFO_H2U buffer, and the data in the readback frame are invalid. A write to the FIFO_H2U_RD register is ignored.When communicating with the HART modem through the UART interface in SPI plus UART mode, any character received on the UARTIN pin is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the clear-to-send (CTS) response is asserted. Similarly, any character received on the RX_IN or RX_INF pin is directly enqueued into FIFO_H2U. The character is then automatically dequeued from FIFO_H2U and transmitted on UARTOUT as a normal UART character. The FIFO buffers are accessed directly by the UART; therefore, do not use the FIFO_U2H_WR and FIFO_H2U_RD registers with the SPI. As a result of using FIFO_U2H in the data path, there is a latency from the UARTIN pin to the MOD_OUT pin; see also . Similarly, as a result of using FIFO_H2U, there is a latency from the RX_IN or RX_INF pin to the UARTOUT pin; see also .HART bus communication activity is interfaced to the host controller through the CD and RTS pins. If the CD and RTS pins are not used, poll the MODEM_STATUS register regularly to monitor the status of the modem.RTSRTSIn UBM mode, any character received on the UARTIN pin that is not a part of a break command is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the CTS response is asserted. Although the UBM packets can access all registers, do not use the break command to write the HART transmit data into FIFO_U2H_WR register. Use the standard 8O1 UART character format to enqueue data into the FIFO_U2H buffer, and thus to the HART modulator. Similarly, do not use the break command to read the HART receive data from the FIFO_H2U_RD register. HART receive data are automatically dequeued from FIFO_H2U and transmitted on UARTOUT as normal UART characters in UBM mode. FIFO Buffer Flags Status bits exist for both transmit and receive FIFO buffers in the MODEM_STATUS, FIFO_STATUS and FIFO_H2U_RD registers. These include full, empty, and level flags. Buffer level flags are used to trigger IRQs for HART communication; see also . The status fields in the FIFO_H2U_RD register represent the state of FIFO_H2U before the read is performed and the data byte is dequeued. This implementation means that if the EMPTY_ FLAG is set, the data byte received in that frame is invalid. Similarly, the LEVEL field represents the 4 MSBs for the FIFO_H2U level before dequeuing. The LSB is not reported, and there are only five internal bits to represent 32 levels; therefore, the LEVEL = 0 is reported when the actual level is 0, 1, or 32. Use FULL_FLAG and EMPTY_FLAG when LEVEL = 0 to differentiate between these three cases. The FIFO_H2U and FIFO_U2H buffers have 32 levels; however, the level setting for generating IRQ events only uses four bits. For the receive FIFO_H2U buffer, the LSB in the FIFO level threshold comparison is always 1 (FIFO_CFG.H2U_LEVEL_SET[3:0], 1). This configuration is designed to alert the user when FIFO_H2U is getting nearly full so as to enable a timely data dequeue, and prevent the loss of incoming HART data due to FIFO overload. For this reason, the FIFO_H2U_LEVEL_FLAG is also a greater-than (>) comparison to the FIFO_CFG.H2U_LEVEL_SET. For example, if FIFO_CFG.H2U_LEVEL_SET = 4’b1000, then when the level of the FIFO_H2U > 5’b10001, the FIFO_H2U_LEVEL_FLAG is set. Setting FIFO_CFG.H2U_LEVEL_SET = 4’b1111 (default) effectively disables this flag. Use FIFO_H2U_FULL_ FLAG to detect the FIFO_H2U full event. When the FIFO_H2U is full, the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. Similarly, for the transmit FIFO_U2H buffer, the LSB in the FIFO level threshold comparison is always 0 (FIFO_CFG.U2H_LEVEL_SET[3:0], 0). This configuration is designed to alert the user when FIFO_U2H is getting nearly empty so as to enable a timely data enqueue, and prevent FIFO_U2H from becoming empty prematurely and causing a gap error on the HART bus. For this reason, the FIFO_U2H_LEVEL_FLAG is also a less-than (<) comparison with the FIFO_CFG.U2H_LEVEL_SET. For example, if FIFO_CFG.U2H_LEVEL_SET = 4’b1000, then when the level of the FIFO_U2H < 5’b10000, the FIFO_U2H_LEVEL_FLAG is set. Setting FIFO_CFG.U2H_LEVEL_SET = 4’b0000 (default) effectively disables this flag. Use FIFO_U2H_EMPTY_ FLAG to detect the FIFO_U2H empty event. To avoid buffer overflow, monitor the level of FIFO_U2H by watching for a buffer-full or buffer-threshold event. If the FIFO_U2H_LEVEL_FLAG bit in the MODEM_STATUS_MASK register is set to 0, the IRQ pin toggles when the threshold is exceeded. Similarly, an alarm can be triggered based on the FIFO_U2H_FULL_FLAG bit in the MODEM_STATUS register. When the FIFO_U2H is full the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. FIFO Buffer Flags Status bits exist for both transmit and receive FIFO buffers in the MODEM_STATUS, FIFO_STATUS and FIFO_H2U_RD registers. These include full, empty, and level flags. Buffer level flags are used to trigger IRQs for HART communication; see also . The status fields in the FIFO_H2U_RD register represent the state of FIFO_H2U before the read is performed and the data byte is dequeued. This implementation means that if the EMPTY_ FLAG is set, the data byte received in that frame is invalid. Similarly, the LEVEL field represents the 4 MSBs for the FIFO_H2U level before dequeuing. The LSB is not reported, and there are only five internal bits to represent 32 levels; therefore, the LEVEL = 0 is reported when the actual level is 0, 1, or 32. Use FULL_FLAG and EMPTY_FLAG when LEVEL = 0 to differentiate between these three cases. The FIFO_H2U and FIFO_U2H buffers have 32 levels; however, the level setting for generating IRQ events only uses four bits. For the receive FIFO_H2U buffer, the LSB in the FIFO level threshold comparison is always 1 (FIFO_CFG.H2U_LEVEL_SET[3:0], 1). This configuration is designed to alert the user when FIFO_H2U is getting nearly full so as to enable a timely data dequeue, and prevent the loss of incoming HART data due to FIFO overload. For this reason, the FIFO_H2U_LEVEL_FLAG is also a greater-than (>) comparison to the FIFO_CFG.H2U_LEVEL_SET. For example, if FIFO_CFG.H2U_LEVEL_SET = 4’b1000, then when the level of the FIFO_H2U > 5’b10001, the FIFO_H2U_LEVEL_FLAG is set. Setting FIFO_CFG.H2U_LEVEL_SET = 4’b1111 (default) effectively disables this flag. Use FIFO_H2U_FULL_ FLAG to detect the FIFO_H2U full event. When the FIFO_H2U is full, the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. Similarly, for the transmit FIFO_U2H buffer, the LSB in the FIFO level threshold comparison is always 0 (FIFO_CFG.U2H_LEVEL_SET[3:0], 0). This configuration is designed to alert the user when FIFO_U2H is getting nearly empty so as to enable a timely data enqueue, and prevent FIFO_U2H from becoming empty prematurely and causing a gap error on the HART bus. For this reason, the FIFO_U2H_LEVEL_FLAG is also a less-than (<) comparison with the FIFO_CFG.U2H_LEVEL_SET. For example, if FIFO_CFG.U2H_LEVEL_SET = 4’b1000, then when the level of the FIFO_U2H < 5’b10000, the FIFO_U2H_LEVEL_FLAG is set. Setting FIFO_CFG.U2H_LEVEL_SET = 4’b0000 (default) effectively disables this flag. Use FIFO_U2H_EMPTY_ FLAG to detect the FIFO_U2H empty event. To avoid buffer overflow, monitor the level of FIFO_U2H by watching for a buffer-full or buffer-threshold event. If the FIFO_U2H_LEVEL_FLAG bit in the MODEM_STATUS_MASK register is set to 0, the IRQ pin toggles when the threshold is exceeded. Similarly, an alarm can be triggered based on the FIFO_U2H_FULL_FLAG bit in the MODEM_STATUS register. When the FIFO_U2H is full the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. Status bits exist for both transmit and receive FIFO buffers in the MODEM_STATUS, FIFO_STATUS and FIFO_H2U_RD registers. These include full, empty, and level flags. Buffer level flags are used to trigger IRQs for HART communication; see also . The status fields in the FIFO_H2U_RD register represent the state of FIFO_H2U before the read is performed and the data byte is dequeued. This implementation means that if the EMPTY_ FLAG is set, the data byte received in that frame is invalid. Similarly, the LEVEL field represents the 4 MSBs for the FIFO_H2U level before dequeuing. The LSB is not reported, and there are only five internal bits to represent 32 levels; therefore, the LEVEL = 0 is reported when the actual level is 0, 1, or 32. Use FULL_FLAG and EMPTY_FLAG when LEVEL = 0 to differentiate between these three cases. The FIFO_H2U and FIFO_U2H buffers have 32 levels; however, the level setting for generating IRQ events only uses four bits. For the receive FIFO_H2U buffer, the LSB in the FIFO level threshold comparison is always 1 (FIFO_CFG.H2U_LEVEL_SET[3:0], 1). This configuration is designed to alert the user when FIFO_H2U is getting nearly full so as to enable a timely data dequeue, and prevent the loss of incoming HART data due to FIFO overload. For this reason, the FIFO_H2U_LEVEL_FLAG is also a greater-than (>) comparison to the FIFO_CFG.H2U_LEVEL_SET. For example, if FIFO_CFG.H2U_LEVEL_SET = 4’b1000, then when the level of the FIFO_H2U > 5’b10001, the FIFO_H2U_LEVEL_FLAG is set. Setting FIFO_CFG.H2U_LEVEL_SET = 4’b1111 (default) effectively disables this flag. Use FIFO_H2U_FULL_ FLAG to detect the FIFO_H2U full event. When the FIFO_H2U is full, the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. Similarly, for the transmit FIFO_U2H buffer, the LSB in the FIFO level threshold comparison is always 0 (FIFO_CFG.U2H_LEVEL_SET[3:0], 0). This configuration is designed to alert the user when FIFO_U2H is getting nearly empty so as to enable a timely data enqueue, and prevent FIFO_U2H from becoming empty prematurely and causing a gap error on the HART bus. For this reason, the FIFO_U2H_LEVEL_FLAG is also a less-than (<) comparison with the FIFO_CFG.U2H_LEVEL_SET. For example, if FIFO_CFG.U2H_LEVEL_SET = 4’b1000, then when the level of the FIFO_U2H < 5’b10000, the FIFO_U2H_LEVEL_FLAG is set. Setting FIFO_CFG.U2H_LEVEL_SET = 4’b0000 (default) effectively disables this flag. Use FIFO_U2H_EMPTY_ FLAG to detect the FIFO_U2H empty event. To avoid buffer overflow, monitor the level of FIFO_U2H by watching for a buffer-full or buffer-threshold event. If the FIFO_U2H_LEVEL_FLAG bit in the MODEM_STATUS_MASK register is set to 0, the IRQ pin toggles when the threshold is exceeded. Similarly, an alarm can be triggered based on the FIFO_U2H_FULL_FLAG bit in the MODEM_STATUS register. When the FIFO_U2H is full the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. Status bits exist for both transmit and receive FIFO buffers in the MODEM_STATUS, FIFO_STATUS and FIFO_H2U_RD registers. These include full, empty, and level flags. Buffer level flags are used to trigger IRQs for HART communication; see also . The status fields in the FIFO_H2U_RD register represent the state of FIFO_H2U before the read is performed and the data byte is dequeued. This implementation means that if the EMPTY_ FLAG is set, the data byte received in that frame is invalid. Similarly, the LEVEL field represents the 4 MSBs for the FIFO_H2U level before dequeuing. The LSB is not reported, and there are only five internal bits to represent 32 levels; therefore, the LEVEL = 0 is reported when the actual level is 0, 1, or 32. Use FULL_FLAG and EMPTY_FLAG when LEVEL = 0 to differentiate between these three cases.The FIFO_H2U and FIFO_U2H buffers have 32 levels; however, the level setting for generating IRQ events only uses four bits. For the receive FIFO_H2U buffer, the LSB in the FIFO level threshold comparison is always 1 (FIFO_CFG.H2U_LEVEL_SET[3:0], 1). This configuration is designed to alert the user when FIFO_H2U is getting nearly full so as to enable a timely data dequeue, and prevent the loss of incoming HART data due to FIFO overload. For this reason, the FIFO_H2U_LEVEL_FLAG is also a greater-than (>) comparison to the FIFO_CFG.H2U_LEVEL_SET. For example, if FIFO_CFG.H2U_LEVEL_SET = 4’b1000, then when the level of the FIFO_H2U > 5’b10001, the FIFO_H2U_LEVEL_FLAG is set. Setting FIFO_CFG.H2U_LEVEL_SET = 4’b1111 (default) effectively disables this flag. Use FIFO_H2U_FULL_ FLAG to detect the FIFO_H2U full event. When the FIFO_H2U is full, the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data.Similarly, for the transmit FIFO_U2H buffer, the LSB in the FIFO level threshold comparison is always 0 (FIFO_CFG.U2H_LEVEL_SET[3:0], 0). This configuration is designed to alert the user when FIFO_U2H is getting nearly empty so as to enable a timely data enqueue, and prevent FIFO_U2H from becoming empty prematurely and causing a gap error on the HART bus. For this reason, the FIFO_U2H_LEVEL_FLAG is also a less-than (<) comparison with the FIFO_CFG.U2H_LEVEL_SET. For example, if FIFO_CFG.U2H_LEVEL_SET = 4’b1000, then when the level of the FIFO_U2H < 5’b10000, the FIFO_U2H_LEVEL_FLAG is set. Setting FIFO_CFG.U2H_LEVEL_SET = 4’b0000 (default) effectively disables this flag. Use FIFO_U2H_EMPTY_ FLAG to detect the FIFO_U2H empty event.To avoid buffer overflow, monitor the level of FIFO_U2H by watching for a buffer-full or buffer-threshold event. If the FIFO_U2H_LEVEL_FLAG bit in the MODEM_STATUS_MASK register is set to 0, the IRQ pin toggles when the threshold is exceeded. Similarly, an alarm can be triggered based on the FIFO_U2H_FULL_FLAG bit in the MODEM_STATUS register. When the FIFO_U2H is full the new incoming data are blocked from enqueuing into the FIFO and ignored to preserve the existing data. HART Modulator The HART modulator implements a look-up table (LUT) containing 128, 8-bit, signed values that represent a single-phase, continuous sinusoidal cycle. A counter is implemented that incrementally loads the table values to a DAC at a clock frequency determined by the binary value of the input data. The DAC clock frequency is determined by the logical value of the data bit being transmitted. A logic 1 transmits at the internal clock frequency of 32 (default) steps times 1200 Hz. A logic 0 transmits at the internal clock frequency of 32 (default) steps times 2200 Hz. All frequencies are derived from 1.2288 MHz. This process creates the mark and space analog output signals used to represent HART data. The default mode uses 32 sinusoidal codes per period from the LUT for power savings. To generate a 128-step-per-period sinusoidal signal set MODEM_CFG.TxRES = 1. shows the HART modulator architecture. HART Modulator Architecture HART Modulator The HART modulator implements a look-up table (LUT) containing 128, 8-bit, signed values that represent a single-phase, continuous sinusoidal cycle. A counter is implemented that incrementally loads the table values to a DAC at a clock frequency determined by the binary value of the input data. The DAC clock frequency is determined by the logical value of the data bit being transmitted. A logic 1 transmits at the internal clock frequency of 32 (default) steps times 1200 Hz. A logic 0 transmits at the internal clock frequency of 32 (default) steps times 2200 Hz. All frequencies are derived from 1.2288 MHz. This process creates the mark and space analog output signals used to represent HART data. The default mode uses 32 sinusoidal codes per period from the LUT for power savings. To generate a 128-step-per-period sinusoidal signal set MODEM_CFG.TxRES = 1. shows the HART modulator architecture. HART Modulator Architecture The HART modulator implements a look-up table (LUT) containing 128, 8-bit, signed values that represent a single-phase, continuous sinusoidal cycle. A counter is implemented that incrementally loads the table values to a DAC at a clock frequency determined by the binary value of the input data. The DAC clock frequency is determined by the logical value of the data bit being transmitted. A logic 1 transmits at the internal clock frequency of 32 (default) steps times 1200 Hz. A logic 0 transmits at the internal clock frequency of 32 (default) steps times 2200 Hz. All frequencies are derived from 1.2288 MHz. This process creates the mark and space analog output signals used to represent HART data. The default mode uses 32 sinusoidal codes per period from the LUT for power savings. To generate a 128-step-per-period sinusoidal signal set MODEM_CFG.TxRES = 1. shows the HART modulator architecture. HART Modulator Architecture The HART modulator implements a look-up table (LUT) containing 128, 8-bit, signed values that represent a single-phase, continuous sinusoidal cycle. A counter is implemented that incrementally loads the table values to a DAC at a clock frequency determined by the binary value of the input data. The DAC clock frequency is determined by the logical value of the data bit being transmitted. A logic 1 transmits at the internal clock frequency of 32 (default) steps times 1200 Hz. A logic 0 transmits at the internal clock frequency of 32 (default) steps times 2200 Hz. All frequencies are derived from 1.2288 MHz. This process creates the mark and space analog output signals used to represent HART data. The default mode uses 32 sinusoidal codes per period from the LUT for power savings. To generate a 128-step-per-period sinusoidal signal set MODEM_CFG.TxRES = 1. shows the HART modulator architecture.markspace HART Modulator Architecture HART Modulator Architecture HART Demodulator The HART demodulator converts the HART FSK input signals applied at the HART input pins (RX_IN and RX_INF) to binary data that are enqueued into the receive FIFO (FIFO_H2U). Data from the FIFO_H2U can then be dequeued by the host controller using the SPI or output on UARTOUT. shows the HART demodulator architecture. The AFEx82H1 supports two different input bandpass filter modes: internal and external. In internal filter mode, the HART input signal is connected to the RX_IN pin through the high-pass filter capacitor. In this mode, the low-pass filter capacitor is connected to the RX_INF pin. In external filter mode, the band-pass filter is implemented with external components for better flexibility, and the resulting band-pass-filtered signal is connected to the RX_INF pin. In this mode, float the RX_IN pin. Use the MODEM_CFG.RX_EXFILT_EN bit to select between these two modes, depending on the external band-pass filter implementation and HART input signal connection. The input band-pass filter (either fully external or partially internal with external capacitors and internal resistors) is followed by the internal second-order high-pass filter and the internal second-order low-pass filter. To enable the second-order low-pass filter, use the MODEM_CFG.RX_HORD_EN bit. HART Demodulator Architecture The HART demodulator asserts a carrier detect (CD) signal, when a carrier-above-threshold level is detected. Hysteresis is implemented with the carrier-detect feature to prevent erroneous carrier-detection signals. The glitch-free CD signal is available internally to the arbiter and externally to the system controller on the CD pin. HART Demodulator The HART demodulator converts the HART FSK input signals applied at the HART input pins (RX_IN and RX_INF) to binary data that are enqueued into the receive FIFO (FIFO_H2U). Data from the FIFO_H2U can then be dequeued by the host controller using the SPI or output on UARTOUT. shows the HART demodulator architecture. The AFEx82H1 supports two different input bandpass filter modes: internal and external. In internal filter mode, the HART input signal is connected to the RX_IN pin through the high-pass filter capacitor. In this mode, the low-pass filter capacitor is connected to the RX_INF pin. In external filter mode, the band-pass filter is implemented with external components for better flexibility, and the resulting band-pass-filtered signal is connected to the RX_INF pin. In this mode, float the RX_IN pin. Use the MODEM_CFG.RX_EXFILT_EN bit to select between these two modes, depending on the external band-pass filter implementation and HART input signal connection. The input band-pass filter (either fully external or partially internal with external capacitors and internal resistors) is followed by the internal second-order high-pass filter and the internal second-order low-pass filter. To enable the second-order low-pass filter, use the MODEM_CFG.RX_HORD_EN bit. HART Demodulator Architecture The HART demodulator asserts a carrier detect (CD) signal, when a carrier-above-threshold level is detected. Hysteresis is implemented with the carrier-detect feature to prevent erroneous carrier-detection signals. The glitch-free CD signal is available internally to the arbiter and externally to the system controller on the CD pin. The HART demodulator converts the HART FSK input signals applied at the HART input pins (RX_IN and RX_INF) to binary data that are enqueued into the receive FIFO (FIFO_H2U). Data from the FIFO_H2U can then be dequeued by the host controller using the SPI or output on UARTOUT. shows the HART demodulator architecture. The AFEx82H1 supports two different input bandpass filter modes: internal and external. In internal filter mode, the HART input signal is connected to the RX_IN pin through the high-pass filter capacitor. In this mode, the low-pass filter capacitor is connected to the RX_INF pin. In external filter mode, the band-pass filter is implemented with external components for better flexibility, and the resulting band-pass-filtered signal is connected to the RX_INF pin. In this mode, float the RX_IN pin. Use the MODEM_CFG.RX_EXFILT_EN bit to select between these two modes, depending on the external band-pass filter implementation and HART input signal connection. The input band-pass filter (either fully external or partially internal with external capacitors and internal resistors) is followed by the internal second-order high-pass filter and the internal second-order low-pass filter. To enable the second-order low-pass filter, use the MODEM_CFG.RX_HORD_EN bit. HART Demodulator Architecture The HART demodulator asserts a carrier detect (CD) signal, when a carrier-above-threshold level is detected. Hysteresis is implemented with the carrier-detect feature to prevent erroneous carrier-detection signals. The glitch-free CD signal is available internally to the arbiter and externally to the system controller on the CD pin. The HART demodulator converts the HART FSK input signals applied at the HART input pins (RX_IN and RX_INF) to binary data that are enqueued into the receive FIFO (FIFO_H2U). Data from the FIFO_H2U can then be dequeued by the host controller using the SPI or output on UARTOUT. shows the HART demodulator architecture. The AFEx82H1 supports two different input bandpass filter modes: internal and external. AFEx82H1In internal filter mode, the HART input signal is connected to the RX_IN pin through the high-pass filter capacitor. In this mode, the low-pass filter capacitor is connected to the RX_INF pin.In external filter mode, the band-pass filter is implemented with external components for better flexibility, and the resulting band-pass-filtered signal is connected to the RX_INF pin. In this mode, float the RX_IN pin.Use the MODEM_CFG.RX_EXFILT_EN bit to select between these two modes, depending on the external band-pass filter implementation and HART input signal connection.The input band-pass filter (either fully external or partially internal with external capacitors and internal resistors) is followed by the internal second-order high-pass filter and the internal second-order low-pass filter. To enable the second-order low-pass filter, use the MODEM_CFG.RX_HORD_EN bit. HART Demodulator Architecture HART Demodulator ArchitectureThe HART demodulator asserts a carrier detect (CD) signal, when a carrier-above-threshold level is detected. Hysteresis is implemented with the carrier-detect feature to prevent erroneous carrier-detection signals. The glitch-free CD signal is available internally to the arbiter and externally to the system controller on the CD pin. HART Modem Modes The HART modulator‑demodulator operates in either half‑duplex or full‑duplex mode. Half-Duplex Mode Half-duplex mode is the main functional mode of operation for the AFEx82H1, in conjunction with the half‑duplex HART protocol. In half-duplex mode, either the modulator or demodulator is active at any given instant, but never simultaneously enabled. By default, the demodulator is active and the modulator is inactive. When using half-duplex mode, the modem arbitrates when modulator and demodulator are active. For more details, see . Full-Duplex Mode In full‑duplex mode, the modulator and demodulator are simultaneously enabled. This configuration allows a self‑test feature to verify functionality of the transmit and receive signal chains to improve system diagnostics. There are internal and external full-duplex modes. In internal full-duplex mode, the MOD_OUT pin is internally shorted to the RX_INF pin. Set MODEM_CFG.DUPLEX = 1 to enable an internal connection between the HART transmitter and receiver to verify communication. In external full-duplex mode, the HART modulator and demodulator are enabled, but the MOD_OUT pin is not internally shorted to the RX_IN or RX_INF pins. To enable the external full‑duplex mode, short MOD_OUT to RX_IN or RX_INF pins externally, and set MODEM_CFG.DUPLEX_EXT = 1. HART Modem Modes The HART modulator‑demodulator operates in either half‑duplex or full‑duplex mode. The HART modulator‑demodulator operates in either half‑duplex or full‑duplex mode. The HART modulator‑demodulator operates in either half‑duplex or full‑duplex mode. Half-Duplex Mode Half-duplex mode is the main functional mode of operation for the AFEx82H1, in conjunction with the half‑duplex HART protocol. In half-duplex mode, either the modulator or demodulator is active at any given instant, but never simultaneously enabled. By default, the demodulator is active and the modulator is inactive. When using half-duplex mode, the modem arbitrates when modulator and demodulator are active. For more details, see . Half-Duplex Mode Half-duplex mode is the main functional mode of operation for the AFEx82H1, in conjunction with the half‑duplex HART protocol. In half-duplex mode, either the modulator or demodulator is active at any given instant, but never simultaneously enabled. By default, the demodulator is active and the modulator is inactive. When using half-duplex mode, the modem arbitrates when modulator and demodulator are active. For more details, see . Half-duplex mode is the main functional mode of operation for the AFEx82H1, in conjunction with the half‑duplex HART protocol. In half-duplex mode, either the modulator or demodulator is active at any given instant, but never simultaneously enabled. By default, the demodulator is active and the modulator is inactive. When using half-duplex mode, the modem arbitrates when modulator and demodulator are active. For more details, see . Half-duplex mode is the main functional mode of operation for the AFEx82H1, in conjunction with the half‑duplex HART protocol. In half-duplex mode, either the modulator or demodulator is active at any given instant, but never simultaneously enabled. By default, the demodulator is active and the modulator is inactive. When using half-duplex mode, the modem arbitrates when modulator and demodulator are active. For more details, see . AFEx82H1 Full-Duplex Mode In full‑duplex mode, the modulator and demodulator are simultaneously enabled. This configuration allows a self‑test feature to verify functionality of the transmit and receive signal chains to improve system diagnostics. There are internal and external full-duplex modes. In internal full-duplex mode, the MOD_OUT pin is internally shorted to the RX_INF pin. Set MODEM_CFG.DUPLEX = 1 to enable an internal connection between the HART transmitter and receiver to verify communication. In external full-duplex mode, the HART modulator and demodulator are enabled, but the MOD_OUT pin is not internally shorted to the RX_IN or RX_INF pins. To enable the external full‑duplex mode, short MOD_OUT to RX_IN or RX_INF pins externally, and set MODEM_CFG.DUPLEX_EXT = 1. Full-Duplex Mode In full‑duplex mode, the modulator and demodulator are simultaneously enabled. This configuration allows a self‑test feature to verify functionality of the transmit and receive signal chains to improve system diagnostics. There are internal and external full-duplex modes. In internal full-duplex mode, the MOD_OUT pin is internally shorted to the RX_INF pin. Set MODEM_CFG.DUPLEX = 1 to enable an internal connection between the HART transmitter and receiver to verify communication. In external full-duplex mode, the HART modulator and demodulator are enabled, but the MOD_OUT pin is not internally shorted to the RX_IN or RX_INF pins. To enable the external full‑duplex mode, short MOD_OUT to RX_IN or RX_INF pins externally, and set MODEM_CFG.DUPLEX_EXT = 1. In full‑duplex mode, the modulator and demodulator are simultaneously enabled. This configuration allows a self‑test feature to verify functionality of the transmit and receive signal chains to improve system diagnostics. There are internal and external full-duplex modes. In internal full-duplex mode, the MOD_OUT pin is internally shorted to the RX_INF pin. Set MODEM_CFG.DUPLEX = 1 to enable an internal connection between the HART transmitter and receiver to verify communication. In external full-duplex mode, the HART modulator and demodulator are enabled, but the MOD_OUT pin is not internally shorted to the RX_IN or RX_INF pins. To enable the external full‑duplex mode, short MOD_OUT to RX_IN or RX_INF pins externally, and set MODEM_CFG.DUPLEX_EXT = 1. In full‑duplex mode, the modulator and demodulator are simultaneously enabled. This configuration allows a self‑test feature to verify functionality of the transmit and receive signal chains to improve system diagnostics. There are internal and external full-duplex modes.In internal full-duplex mode, the MOD_OUT pin is internally shorted to the RX_INF pin. Set MODEM_CFG.DUPLEX = 1 to enable an internal connection between the HART transmitter and receiver to verify communication.In external full-duplex mode, the HART modulator and demodulator are enabled, but the MOD_OUT pin is not internally shorted to the RX_IN or RX_INF pins. To enable the external full‑duplex mode, short MOD_OUT to RX_IN or RX_INF pins externally, and set MODEM_CFG.DUPLEX_EXT = 1. HART Modulation and Demodulation Arbitration In half‑duplex HART-protocol mode, the device arbitrates when the modulator and demodulator are active, based on activity on the HART bus. The system controller has various means of monitoring and interacting with the AFEx82H1. For the methods used in SPI mode, see . For the reporting method used in UART mode, see . In the default idle state, the RTS pin is high (inactive), and the CD pin is low. The demodulator is active and the modulator is inactive. HART Receive Mode When a carrier is detected, the CD pin toggles high, and data bytes received by the modem are automatically enqueued into FIFO_H2U. This mode is the highest priority, and the device continues to remain in this mode as long as a valid carrier is present. The system controller must timely dequeue the data from the FIFO_H2U as long as CD remains high and the demodulator enqueues new data into FIFO_H2U. CD is deasserted when the level of the incoming carrier is reduced to less than the HART specification. For receive operation timing details, see . HART Transmit Mode To transmit the HART data, issue a request to send (RTS) either by toggling the RTS pin low or asserting MODEM_CFG.RTS, depending on the selected communication setup. When the HART bus is available for transmission and no carrier is detected, the device deasserts the CD pin, disables the demodulator, asserts the CTS response by setting MODEM_STATUS.CTS_ASSERT = 1, and begins modulating the carrier. If the CD pin is used, wait for the CD pin to be deasserted. Otherwise, unmask CTS_ASSERT and set up the appropriate IRQs for the FIFO_U2H levels and CTS flags to enable the system controller to receive an IRQ when CTS is asserted. See also . When the CD pin and IRQ are not used, poll the MODEM_STATUS register regularly to detect when the CTS response is asserted. As long as the CD pin is asserted, the demodulator remains active and the RTS request is held pending by the arbiter. Any HART transmit data bytes received by the AFEx82H1 are enqueued into FIFO_U2H, but not transmitted immediately. The system controller must monitor the FIFO_U2H level to avoid buffer overflow in this condition. When the CTS response is asserted, the data enqueued into FIFO_U2H are dequeued and transmitted onto the MOD_OUT pin. If no data are enqueued into FIFO_U2H, the modulator starts transmitting the mark signal. The beginning of the bit stream must meet the minimum bit times requirement to make sure there is enough time for successful detection of the mark-to-space transition on the receiving side; see also . The system controller is then required to maintain adequate an FIFO_U2H buffer level to avoid gap errors and deassert the RTS at the end of bit stream with the correct timing delays; see also . HART Modulation and Demodulation Arbitration In half‑duplex HART-protocol mode, the device arbitrates when the modulator and demodulator are active, based on activity on the HART bus. The system controller has various means of monitoring and interacting with the AFEx82H1. For the methods used in SPI mode, see . For the reporting method used in UART mode, see . In the default idle state, the RTS pin is high (inactive), and the CD pin is low. The demodulator is active and the modulator is inactive. In half‑duplex HART-protocol mode, the device arbitrates when the modulator and demodulator are active, based on activity on the HART bus. The system controller has various means of monitoring and interacting with the AFEx82H1. For the methods used in SPI mode, see . For the reporting method used in UART mode, see . In the default idle state, the RTS pin is high (inactive), and the CD pin is low. The demodulator is active and the modulator is inactive. In half‑duplex HART-protocol mode, the device arbitrates when the modulator and demodulator are active, based on activity on the HART bus. The system controller has various means of monitoring and interacting with the AFEx82H1. For the methods used in SPI mode, see . For the reporting method used in UART mode, see .AFEx82H1In the default idle state, the RTS pin is high (inactive), and the CD pin is low. The demodulator is active and the modulator is inactive.RTS HART Receive Mode When a carrier is detected, the CD pin toggles high, and data bytes received by the modem are automatically enqueued into FIFO_H2U. This mode is the highest priority, and the device continues to remain in this mode as long as a valid carrier is present. The system controller must timely dequeue the data from the FIFO_H2U as long as CD remains high and the demodulator enqueues new data into FIFO_H2U. CD is deasserted when the level of the incoming carrier is reduced to less than the HART specification. For receive operation timing details, see . HART Receive Mode When a carrier is detected, the CD pin toggles high, and data bytes received by the modem are automatically enqueued into FIFO_H2U. This mode is the highest priority, and the device continues to remain in this mode as long as a valid carrier is present. The system controller must timely dequeue the data from the FIFO_H2U as long as CD remains high and the demodulator enqueues new data into FIFO_H2U. CD is deasserted when the level of the incoming carrier is reduced to less than the HART specification. For receive operation timing details, see . When a carrier is detected, the CD pin toggles high, and data bytes received by the modem are automatically enqueued into FIFO_H2U. This mode is the highest priority, and the device continues to remain in this mode as long as a valid carrier is present. The system controller must timely dequeue the data from the FIFO_H2U as long as CD remains high and the demodulator enqueues new data into FIFO_H2U. CD is deasserted when the level of the incoming carrier is reduced to less than the HART specification. For receive operation timing details, see . When a carrier is detected, the CD pin toggles high, and data bytes received by the modem are automatically enqueued into FIFO_H2U. This mode is the highest priority, and the device continues to remain in this mode as long as a valid carrier is present. The system controller must timely dequeue the data from the FIFO_H2U as long as CD remains high and the demodulator enqueues new data into FIFO_H2U. CD is deasserted when the level of the incoming carrier is reduced to less than the HART specification. For receive operation timing details, see . HART Transmit Mode To transmit the HART data, issue a request to send (RTS) either by toggling the RTS pin low or asserting MODEM_CFG.RTS, depending on the selected communication setup. When the HART bus is available for transmission and no carrier is detected, the device deasserts the CD pin, disables the demodulator, asserts the CTS response by setting MODEM_STATUS.CTS_ASSERT = 1, and begins modulating the carrier. If the CD pin is used, wait for the CD pin to be deasserted. Otherwise, unmask CTS_ASSERT and set up the appropriate IRQs for the FIFO_U2H levels and CTS flags to enable the system controller to receive an IRQ when CTS is asserted. See also . When the CD pin and IRQ are not used, poll the MODEM_STATUS register regularly to detect when the CTS response is asserted. As long as the CD pin is asserted, the demodulator remains active and the RTS request is held pending by the arbiter. Any HART transmit data bytes received by the AFEx82H1 are enqueued into FIFO_U2H, but not transmitted immediately. The system controller must monitor the FIFO_U2H level to avoid buffer overflow in this condition. When the CTS response is asserted, the data enqueued into FIFO_U2H are dequeued and transmitted onto the MOD_OUT pin. If no data are enqueued into FIFO_U2H, the modulator starts transmitting the mark signal. The beginning of the bit stream must meet the minimum bit times requirement to make sure there is enough time for successful detection of the mark-to-space transition on the receiving side; see also . The system controller is then required to maintain adequate an FIFO_U2H buffer level to avoid gap errors and deassert the RTS at the end of bit stream with the correct timing delays; see also . HART Transmit Mode To transmit the HART data, issue a request to send (RTS) either by toggling the RTS pin low or asserting MODEM_CFG.RTS, depending on the selected communication setup. When the HART bus is available for transmission and no carrier is detected, the device deasserts the CD pin, disables the demodulator, asserts the CTS response by setting MODEM_STATUS.CTS_ASSERT = 1, and begins modulating the carrier. If the CD pin is used, wait for the CD pin to be deasserted. Otherwise, unmask CTS_ASSERT and set up the appropriate IRQs for the FIFO_U2H levels and CTS flags to enable the system controller to receive an IRQ when CTS is asserted. See also . When the CD pin and IRQ are not used, poll the MODEM_STATUS register regularly to detect when the CTS response is asserted. As long as the CD pin is asserted, the demodulator remains active and the RTS request is held pending by the arbiter. Any HART transmit data bytes received by the AFEx82H1 are enqueued into FIFO_U2H, but not transmitted immediately. The system controller must monitor the FIFO_U2H level to avoid buffer overflow in this condition. When the CTS response is asserted, the data enqueued into FIFO_U2H are dequeued and transmitted onto the MOD_OUT pin. If no data are enqueued into FIFO_U2H, the modulator starts transmitting the mark signal. The beginning of the bit stream must meet the minimum bit times requirement to make sure there is enough time for successful detection of the mark-to-space transition on the receiving side; see also . The system controller is then required to maintain adequate an FIFO_U2H buffer level to avoid gap errors and deassert the RTS at the end of bit stream with the correct timing delays; see also . To transmit the HART data, issue a request to send (RTS) either by toggling the RTS pin low or asserting MODEM_CFG.RTS, depending on the selected communication setup. When the HART bus is available for transmission and no carrier is detected, the device deasserts the CD pin, disables the demodulator, asserts the CTS response by setting MODEM_STATUS.CTS_ASSERT = 1, and begins modulating the carrier. If the CD pin is used, wait for the CD pin to be deasserted. Otherwise, unmask CTS_ASSERT and set up the appropriate IRQs for the FIFO_U2H levels and CTS flags to enable the system controller to receive an IRQ when CTS is asserted. See also . When the CD pin and IRQ are not used, poll the MODEM_STATUS register regularly to detect when the CTS response is asserted. As long as the CD pin is asserted, the demodulator remains active and the RTS request is held pending by the arbiter. Any HART transmit data bytes received by the AFEx82H1 are enqueued into FIFO_U2H, but not transmitted immediately. The system controller must monitor the FIFO_U2H level to avoid buffer overflow in this condition. When the CTS response is asserted, the data enqueued into FIFO_U2H are dequeued and transmitted onto the MOD_OUT pin. If no data are enqueued into FIFO_U2H, the modulator starts transmitting the mark signal. The beginning of the bit stream must meet the minimum bit times requirement to make sure there is enough time for successful detection of the mark-to-space transition on the receiving side; see also . The system controller is then required to maintain adequate an FIFO_U2H buffer level to avoid gap errors and deassert the RTS at the end of bit stream with the correct timing delays; see also . To transmit the HART data, issue a request to send (RTS) either by toggling the RTS pin low or asserting MODEM_CFG.RTS, depending on the selected communication setup. When the HART bus is available for transmission and no carrier is detected, the device deasserts the CD pin, disables the demodulator, asserts the CTS response by setting MODEM_STATUS.CTS_ASSERT = 1, and begins modulating the carrier. If the CD pin is used, wait for the CD pin to be deasserted. Otherwise, unmask CTS_ASSERT and set up the appropriate IRQs for the FIFO_U2H levels and CTS flags to enable the system controller to receive an IRQ when CTS is asserted. See also . When the CD pin and IRQ are not used, poll the MODEM_STATUS register regularly to detect when the CTS response is asserted.RTSAs long as the CD pin is asserted, the demodulator remains active and the RTS request is held pending by the arbiter. Any HART transmit data bytes received by the AFEx82H1 are enqueued into FIFO_U2H, but not transmitted immediately. The system controller must monitor the FIFO_U2H level to avoid buffer overflow in this condition.AFEx82H1When the CTS response is asserted, the data enqueued into FIFO_U2H are dequeued and transmitted onto the MOD_OUT pin. If no data are enqueued into FIFO_U2H, the modulator starts transmitting the mark signal. The beginning of the bit stream must meet the minimum bit times requirement to make sure there is enough time for successful detection of the mark-to-space transition on the receiving side; see also .markmarkspaceThe system controller is then required to maintain adequate an FIFO_U2H buffer level to avoid gap errors and deassert the RTS at the end of bit stream with the correct timing delays; see also . HART Modulator Timing and Preamble Requirements The HART modulator starts modulating the carrier as soon as the CTS response is asserted. If data are enqueued into FIFO_U2H before the CTS is asserted, make sure to enqueue the required preamble bytes at the beginning of the data packet in accordance with . The first byte is used by the HART recipient receiver to recognize the carrier and properly detect the mark-to-space transition of the start bit in the second character. Alternatively, wait for CTS_ASSERT, and give an appropriate delay while the modulator is transmitting the mark signal. Then enqueue the preamble bytes followed by the data bytes into FIFO_U2H. Monitor the level of FIFO_U2H and timely enqueue the new data to avoid transmission gap errors. Carrier Detect and Preamble HART REQUIREMENT FIFO_U2H STATE AFEx82H1 BEHAVIOR RECOMMENDED USE CASE Transmit at least 6 bit times of HART signal of specified amplitude for the carrier to be detected by the receiver. FIFO_U2H is empty. HART modulator starts sending mark FSK signal as soon as CTS is asserted. Wait at least 6 bit times from CTS assert before transmitting first preamble byte. Calculate the time to enqueue the data into FIFO_U2H based on the interface mode used. FIFO_U2H is preloaded with data. HART modulator starts sending FIFO_U2H data as soon as CTS is asserted. Preload FIFO_U2H with one additional preamble byte. Depending on the interface mode, there is a latency from the UARTIN or CS pin to the MOD_OUT pin as a result of using FIFO_U2H in the data path. In the SPI plus UART and UBM modes, a delay of approximately 1.5 bit times (1.5 × tBAUDUART) occurs from the stop bit on the UARTIN pin until the data are enqueued into FIFO_U2H as a result of data decoding and synchronization. shows this timing. HART Transmit Start Timing Diagram (UART Mode) In SPI only mode, the HART transmit data are enqueued into FIFO_U2H using FIFO_U2H_WR register. Therefore, in this mode, take the standard SPI timing into consideration while calculating the latency of the HART transmit data from the CS pin to the MOD_OUT pin. shows the HART transmit start timing for SPI mode. HART Transmit Start Timing Diagram (SPI Mode) The HART character contains 11 bits; therefore, a delay of approximately 11 bit times (11 × tBAUDHART) occurs from the moment the data are dequeued from FIFO_U2H until the data are fully transmitted on the MOD_OUT pin (see ). Additional delay is accumulated when there is a frequency mismatch between the incoming UART_IN data and the HART data transmitted on MOD_OUT. If the UART_IN data frequency is 2% greater compared to the MOD_OUT data frequency, a delay of approximately 1 bit time is accumulated every five HART characters. Add a gap of at least 1 bit time between every five HART characters to account for this latency. Keep the request to send (RTS) asserted until the data are fully transmitted on MOD_OUT. HART Transmit End Timing Diagram (UBM, UART Plus SPI Modes) HART Modulator Timing and Preamble Requirements The HART modulator starts modulating the carrier as soon as the CTS response is asserted. If data are enqueued into FIFO_U2H before the CTS is asserted, make sure to enqueue the required preamble bytes at the beginning of the data packet in accordance with . The first byte is used by the HART recipient receiver to recognize the carrier and properly detect the mark-to-space transition of the start bit in the second character. Alternatively, wait for CTS_ASSERT, and give an appropriate delay while the modulator is transmitting the mark signal. Then enqueue the preamble bytes followed by the data bytes into FIFO_U2H. Monitor the level of FIFO_U2H and timely enqueue the new data to avoid transmission gap errors. Carrier Detect and Preamble HART REQUIREMENT FIFO_U2H STATE AFEx82H1 BEHAVIOR RECOMMENDED USE CASE Transmit at least 6 bit times of HART signal of specified amplitude for the carrier to be detected by the receiver. FIFO_U2H is empty. HART modulator starts sending mark FSK signal as soon as CTS is asserted. Wait at least 6 bit times from CTS assert before transmitting first preamble byte. Calculate the time to enqueue the data into FIFO_U2H based on the interface mode used. FIFO_U2H is preloaded with data. HART modulator starts sending FIFO_U2H data as soon as CTS is asserted. Preload FIFO_U2H with one additional preamble byte. Depending on the interface mode, there is a latency from the UARTIN or CS pin to the MOD_OUT pin as a result of using FIFO_U2H in the data path. In the SPI plus UART and UBM modes, a delay of approximately 1.5 bit times (1.5 × tBAUDUART) occurs from the stop bit on the UARTIN pin until the data are enqueued into FIFO_U2H as a result of data decoding and synchronization. shows this timing. HART Transmit Start Timing Diagram (UART Mode) In SPI only mode, the HART transmit data are enqueued into FIFO_U2H using FIFO_U2H_WR register. Therefore, in this mode, take the standard SPI timing into consideration while calculating the latency of the HART transmit data from the CS pin to the MOD_OUT pin. shows the HART transmit start timing for SPI mode. HART Transmit Start Timing Diagram (SPI Mode) The HART character contains 11 bits; therefore, a delay of approximately 11 bit times (11 × tBAUDHART) occurs from the moment the data are dequeued from FIFO_U2H until the data are fully transmitted on the MOD_OUT pin (see ). Additional delay is accumulated when there is a frequency mismatch between the incoming UART_IN data and the HART data transmitted on MOD_OUT. If the UART_IN data frequency is 2% greater compared to the MOD_OUT data frequency, a delay of approximately 1 bit time is accumulated every five HART characters. Add a gap of at least 1 bit time between every five HART characters to account for this latency. Keep the request to send (RTS) asserted until the data are fully transmitted on MOD_OUT. HART Transmit End Timing Diagram (UBM, UART Plus SPI Modes) The HART modulator starts modulating the carrier as soon as the CTS response is asserted. If data are enqueued into FIFO_U2H before the CTS is asserted, make sure to enqueue the required preamble bytes at the beginning of the data packet in accordance with . The first byte is used by the HART recipient receiver to recognize the carrier and properly detect the mark-to-space transition of the start bit in the second character. Alternatively, wait for CTS_ASSERT, and give an appropriate delay while the modulator is transmitting the mark signal. Then enqueue the preamble bytes followed by the data bytes into FIFO_U2H. Monitor the level of FIFO_U2H and timely enqueue the new data to avoid transmission gap errors. Carrier Detect and Preamble HART REQUIREMENT FIFO_U2H STATE AFEx82H1 BEHAVIOR RECOMMENDED USE CASE Transmit at least 6 bit times of HART signal of specified amplitude for the carrier to be detected by the receiver. FIFO_U2H is empty. HART modulator starts sending mark FSK signal as soon as CTS is asserted. Wait at least 6 bit times from CTS assert before transmitting first preamble byte. Calculate the time to enqueue the data into FIFO_U2H based on the interface mode used. FIFO_U2H is preloaded with data. HART modulator starts sending FIFO_U2H data as soon as CTS is asserted. Preload FIFO_U2H with one additional preamble byte. Depending on the interface mode, there is a latency from the UARTIN or CS pin to the MOD_OUT pin as a result of using FIFO_U2H in the data path. In the SPI plus UART and UBM modes, a delay of approximately 1.5 bit times (1.5 × tBAUDUART) occurs from the stop bit on the UARTIN pin until the data are enqueued into FIFO_U2H as a result of data decoding and synchronization. shows this timing. HART Transmit Start Timing Diagram (UART Mode) In SPI only mode, the HART transmit data are enqueued into FIFO_U2H using FIFO_U2H_WR register. Therefore, in this mode, take the standard SPI timing into consideration while calculating the latency of the HART transmit data from the CS pin to the MOD_OUT pin. shows the HART transmit start timing for SPI mode. HART Transmit Start Timing Diagram (SPI Mode) The HART character contains 11 bits; therefore, a delay of approximately 11 bit times (11 × tBAUDHART) occurs from the moment the data are dequeued from FIFO_U2H until the data are fully transmitted on the MOD_OUT pin (see ). Additional delay is accumulated when there is a frequency mismatch between the incoming UART_IN data and the HART data transmitted on MOD_OUT. If the UART_IN data frequency is 2% greater compared to the MOD_OUT data frequency, a delay of approximately 1 bit time is accumulated every five HART characters. Add a gap of at least 1 bit time between every five HART characters to account for this latency. Keep the request to send (RTS) asserted until the data are fully transmitted on MOD_OUT. HART Transmit End Timing Diagram (UBM, UART Plus SPI Modes) The HART modulator starts modulating the carrier as soon as the CTS response is asserted. If data are enqueued into FIFO_U2H before the CTS is asserted, make sure to enqueue the required preamble bytes at the beginning of the data packet in accordance with . The first byte is used by the HART recipient receiver to recognize the carrier and properly detect the mark-to-space transition of the start bit in the second character. Alternatively, wait for CTS_ASSERT, and give an appropriate delay while the modulator is transmitting the mark signal. Then enqueue the preamble bytes followed by the data bytes into FIFO_U2H. Monitor the level of FIFO_U2H and timely enqueue the new data to avoid transmission gap errors.markspacemark Carrier Detect and Preamble HART REQUIREMENT FIFO_U2H STATE AFEx82H1 BEHAVIOR RECOMMENDED USE CASE Transmit at least 6 bit times of HART signal of specified amplitude for the carrier to be detected by the receiver. FIFO_U2H is empty. HART modulator starts sending mark FSK signal as soon as CTS is asserted. Wait at least 6 bit times from CTS assert before transmitting first preamble byte. Calculate the time to enqueue the data into FIFO_U2H based on the interface mode used. FIFO_U2H is preloaded with data. HART modulator starts sending FIFO_U2H data as soon as CTS is asserted. Preload FIFO_U2H with one additional preamble byte. Carrier Detect and Preamble HART REQUIREMENT FIFO_U2H STATE AFEx82H1 BEHAVIOR RECOMMENDED USE CASE Transmit at least 6 bit times of HART signal of specified amplitude for the carrier to be detected by the receiver. FIFO_U2H is empty. HART modulator starts sending mark FSK signal as soon as CTS is asserted. Wait at least 6 bit times from CTS assert before transmitting first preamble byte. Calculate the time to enqueue the data into FIFO_U2H based on the interface mode used. FIFO_U2H is preloaded with data. HART modulator starts sending FIFO_U2H data as soon as CTS is asserted. Preload FIFO_U2H with one additional preamble byte. HART REQUIREMENT FIFO_U2H STATE AFEx82H1 BEHAVIOR RECOMMENDED USE CASE HART REQUIREMENT FIFO_U2H STATE AFEx82H1 BEHAVIOR RECOMMENDED USE CASE HART REQUIREMENTFIFO_U2H STATE AFEx82H1 BEHAVIORAFEx82H1RECOMMENDED USE CASE Transmit at least 6 bit times of HART signal of specified amplitude for the carrier to be detected by the receiver. FIFO_U2H is empty. HART modulator starts sending mark FSK signal as soon as CTS is asserted. Wait at least 6 bit times from CTS assert before transmitting first preamble byte. Calculate the time to enqueue the data into FIFO_U2H based on the interface mode used. FIFO_U2H is preloaded with data. HART modulator starts sending FIFO_U2H data as soon as CTS is asserted. Preload FIFO_U2H with one additional preamble byte. Transmit at least 6 bit times of HART signal of specified amplitude for the carrier to be detected by the receiver. FIFO_U2H is empty. HART modulator starts sending mark FSK signal as soon as CTS is asserted. Wait at least 6 bit times from CTS assert before transmitting first preamble byte. Calculate the time to enqueue the data into FIFO_U2H based on the interface mode used. Transmit at least 6 bit times of HART signal of specified amplitude for the carrier to be detected by the receiver.FIFO_U2H is empty.HART modulator starts sending mark FSK signal as soon as CTS is asserted.markWait at least 6 bit times from CTS assert before transmitting first preamble byte. Calculate the time to enqueue the data into FIFO_U2H based on the interface mode used. FIFO_U2H is preloaded with data. HART modulator starts sending FIFO_U2H data as soon as CTS is asserted. Preload FIFO_U2H with one additional preamble byte. FIFO_U2H is preloaded with data.HART modulator starts sending FIFO_U2H data as soon as CTS is asserted.Preload FIFO_U2H with one additional preamble byte.Depending on the interface mode, there is a latency from the UARTIN or CS pin to the MOD_OUT pin as a result of using FIFO_U2H in the data path.CSIn the SPI plus UART and UBM modes, a delay of approximately 1.5 bit times (1.5 × tBAUDUART) occurs from the stop bit on the UARTIN pin until the data are enqueued into FIFO_U2H as a result of data decoding and synchronization. shows this timing.BAUDUART HART Transmit Start Timing Diagram (UART Mode) HART Transmit Start Timing Diagram (UART Mode)In SPI only mode, the HART transmit data are enqueued into FIFO_U2H using FIFO_U2H_WR register. Therefore, in this mode, take the standard SPI timing into consideration while calculating the latency of the HART transmit data from the CS pin to the MOD_OUT pin. shows the HART transmit start timing for SPI mode.CS HART Transmit Start Timing Diagram (SPI Mode) HART Transmit Start Timing Diagram (SPI Mode)The HART character contains 11 bits; therefore, a delay of approximately 11 bit times (11 × tBAUDHART) occurs from the moment the data are dequeued from FIFO_U2H until the data are fully transmitted on the MOD_OUT pin (see ). BAUDHARTAdditional delay is accumulated when there is a frequency mismatch between the incoming UART_IN data and the HART data transmitted on MOD_OUT. If the UART_IN data frequency is 2% greater compared to the MOD_OUT data frequency, a delay of approximately 1 bit time is accumulated every five HART characters. Add a gap of at least 1 bit time between every five HART characters to account for this latency. Keep the request to send (RTS) asserted until the data are fully transmitted on MOD_OUT. HART Transmit End Timing Diagram (UBM, UART Plus SPI Modes) HART Transmit End Timing Diagram (UBM, UART Plus SPI Modes) HART Demodulator Timing and Preamble Requirements The RX_IN and RX_INF pins are continuously monitored by the HART demodulator when not transmitting. AFEx82H1 requires at least 3 mark bits (3 × tBAUDHART) of 1200 Hz for carrier detection. For UART-based communication setup, the HART data are automatically dequeued from FIFO_H2U and transmitted on the UARTOUT pin as UART characters. A delay of approximately 1.5 bit times (1.5 × tBAUDHART) occurs as a result of data decoding and synchronization from the end of the character on RX_IN or RX_INF pin until the data are enqueued into FIFO_H2U. Thus, when CD deasserts, there is typically still one UART character pending transfer to the system controller on UARTOUT (see ). FIFO latency is as low as a few microseconds when using the SPI to dequeue the data from FIFO_H2U by reading FIFO_H2U_RD register. and show the timing diagrams for the start and end of the HART receive character, respectively. HART Receive Start Timing Diagram (SPI and UART Modes) HART Receive End Timing Diagram (UART Mode) HART Demodulator Timing and Preamble Requirements The RX_IN and RX_INF pins are continuously monitored by the HART demodulator when not transmitting. AFEx82H1 requires at least 3 mark bits (3 × tBAUDHART) of 1200 Hz for carrier detection. For UART-based communication setup, the HART data are automatically dequeued from FIFO_H2U and transmitted on the UARTOUT pin as UART characters. A delay of approximately 1.5 bit times (1.5 × tBAUDHART) occurs as a result of data decoding and synchronization from the end of the character on RX_IN or RX_INF pin until the data are enqueued into FIFO_H2U. Thus, when CD deasserts, there is typically still one UART character pending transfer to the system controller on UARTOUT (see ). FIFO latency is as low as a few microseconds when using the SPI to dequeue the data from FIFO_H2U by reading FIFO_H2U_RD register. and show the timing diagrams for the start and end of the HART receive character, respectively. HART Receive Start Timing Diagram (SPI and UART Modes) HART Receive End Timing Diagram (UART Mode) The RX_IN and RX_INF pins are continuously monitored by the HART demodulator when not transmitting. AFEx82H1 requires at least 3 mark bits (3 × tBAUDHART) of 1200 Hz for carrier detection. For UART-based communication setup, the HART data are automatically dequeued from FIFO_H2U and transmitted on the UARTOUT pin as UART characters. A delay of approximately 1.5 bit times (1.5 × tBAUDHART) occurs as a result of data decoding and synchronization from the end of the character on RX_IN or RX_INF pin until the data are enqueued into FIFO_H2U. Thus, when CD deasserts, there is typically still one UART character pending transfer to the system controller on UARTOUT (see ). FIFO latency is as low as a few microseconds when using the SPI to dequeue the data from FIFO_H2U by reading FIFO_H2U_RD register. and show the timing diagrams for the start and end of the HART receive character, respectively. HART Receive Start Timing Diagram (SPI and UART Modes) HART Receive End Timing Diagram (UART Mode) The RX_IN and RX_INF pins are continuously monitored by the HART demodulator when not transmitting. AFEx82H1 requires at least 3 mark bits (3 × tBAUDHART) of 1200 Hz for carrier detection.AFEx82H1mark BAUDHARTFor UART-based communication setup, the HART data are automatically dequeued from FIFO_H2U and transmitted on the UARTOUT pin as UART characters. A delay of approximately 1.5 bit times (1.5 × tBAUDHART) occurs as a result of data decoding and synchronization from the end of the character on RX_IN or RX_INF pin until the data are enqueued into FIFO_H2U. Thus, when CD deasserts, there is typically still one UART character pending transfer to the system controller on UARTOUT (see ). BAUDHARTFIFO latency is as low as a few microseconds when using the SPI to dequeue the data from FIFO_H2U by reading FIFO_H2U_RD register. and show the timing diagrams for the start and end of the HART receive character, respectively. HART Receive Start Timing Diagram (SPI and UART Modes) HART Receive Start Timing Diagram (SPI and UART Modes) HART Receive End Timing Diagram (UART Mode) HART Receive End Timing Diagram (UART Mode) IRQ Configuration for HART Communication To enable robust and error-free communicate on the HART bus, the events listed in #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/TABLE_BCL_BCQ_PQB must be detected from the AFEx82H1 by the system controller in a timely manner. If the IRQ signal is not directly connected to the system controller, poll the corresponding status flags. In UART mode, the automatic dequeue of FIFO_H2U simplifies event management significantly, and not all events must be translated to IRQs. When using the HART modem with the IRQ, the IRQ features help control communication in both directions. Enable IRQ functionality by following these steps: Configure the IRQ to be either edge or level sensitive using CONFIG.IRQ_LVL. See also . Configure the IRQ polarity with CONFIG.IRQ_POL, as needed per the respective system. See also . For SPI only mode, set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the UARTOUT pin. Also, set CONFIG.UART_DIS = 1 to disable all UART functionality. For UBM, use one of the two following methods: Set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the SDO pin, or Set CONFIG.UBM_IRQ_EN = 1 to enable interrupts being sent UARTOUT using UBM. After IRQ functionality is enabled, unmask all the required interrupt signals in the MODEM_STATUS_MASK register (set each bit = 0). IRQ Sources and Uses AFEx82H1HART STATE EVENT MODEM_STATUS FLAG ASSERTION METHOD #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWB ACTION Receive RTS deasserted CTS_DEASSERT Toggle RTS pin high or set MODEM_CFG.RTS = 0. Demodulator enabled and ready to receive HART data. Carrier detect asserted CD_ASSERT Demodulator detects the HART carrier signal of valid amplitude. Expect to receive HART data. Set desired FIFO_H2U level trigger threshold. FIFO_H2U level threshold trigger FIFO_H2U_LEVEL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. Dequeue data from FIFO_H2U when level exceeds the set threshold. Prevent FIFO_H2U from being full to avoid the loss of incoming data. FIFO_H2U full FIFO_H2U_FULL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. System controller has not dequeued FIFO_H2U. Critical flag. Dequeue FIFO_H2U immediately to avoid the loss of incoming data. Carrier detect deasserted CD_DEASSERT Demodulator stops detecting the HART carrier signal of valid amplitude. Dequeue remaining data from FIFO_H2U. Monitor the empty flag to make sure that all data have been received. FIFO_H2U empty FIFO_H2U_EMPTY_FLAG Dequeue of FIFO_H2U by system controller. If using UART, wait to make sure the last character is received on UARTOUT. Transmit RTS asserted NA Toggle RTS pin low or write set MODEM_CFG.RTS = 1. Wait for clear-to-send confirmation flag. Clear to send (CTS) CTS_ASSERT RTS asserted and CD deasserted. Modulator enabled. Device starts modulating the carrier on MOD_OUT. Set desired FIFO_U2H level trigger threshold. Enqueue data into FIFO_U2H. Modulator automatically dequeues FIFO_U2H and transmits the HART data. FIFO_U2H level threshold trigger FIFO_U2H_LEVEL_FLAG Automatic dequeue of FIFO_U2H by HART modulator. Enqueue new data into FIFO_U2H when the level drops below the set threshold. Prevent FIFO_U2H from being empty to avoid a gap in transmission. FIFO_U2H full FIFO_U2H_FULL_FLAG System controller enqueue of the new data into FIFO_U2H. Critical flag.Stop enqueue of data into FIFO_U2H immediately to avoid loss of HART data. FIFO_U2H empty FIFO_U2H_EMPTY_FLAG Automatic dequeue of FIFO_U2H by HART modulator. System controller has not enqueued new data into FIFO_U2H. Critical flag in the middle of the data packet.Enqueue new data into FIFO_U2H immediately to avoid a gap in transmission. When the last character is dequeued from FIFO_U2H, wait until the character is fully transmitted on MOD_OUT before deasserting RTS. For CD, RTS, ALARM, and IRQ connection choices, see . IRQ Configuration for HART Communication To enable robust and error-free communicate on the HART bus, the events listed in #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/TABLE_BCL_BCQ_PQB must be detected from the AFEx82H1 by the system controller in a timely manner. If the IRQ signal is not directly connected to the system controller, poll the corresponding status flags. In UART mode, the automatic dequeue of FIFO_H2U simplifies event management significantly, and not all events must be translated to IRQs. When using the HART modem with the IRQ, the IRQ features help control communication in both directions. Enable IRQ functionality by following these steps: Configure the IRQ to be either edge or level sensitive using CONFIG.IRQ_LVL. See also . Configure the IRQ polarity with CONFIG.IRQ_POL, as needed per the respective system. See also . For SPI only mode, set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the UARTOUT pin. Also, set CONFIG.UART_DIS = 1 to disable all UART functionality. For UBM, use one of the two following methods: Set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the SDO pin, or Set CONFIG.UBM_IRQ_EN = 1 to enable interrupts being sent UARTOUT using UBM. After IRQ functionality is enabled, unmask all the required interrupt signals in the MODEM_STATUS_MASK register (set each bit = 0). IRQ Sources and Uses AFEx82H1HART STATE EVENT MODEM_STATUS FLAG ASSERTION METHOD #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWB ACTION Receive RTS deasserted CTS_DEASSERT Toggle RTS pin high or set MODEM_CFG.RTS = 0. Demodulator enabled and ready to receive HART data. Carrier detect asserted CD_ASSERT Demodulator detects the HART carrier signal of valid amplitude. Expect to receive HART data. Set desired FIFO_H2U level trigger threshold. FIFO_H2U level threshold trigger FIFO_H2U_LEVEL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. Dequeue data from FIFO_H2U when level exceeds the set threshold. Prevent FIFO_H2U from being full to avoid the loss of incoming data. FIFO_H2U full FIFO_H2U_FULL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. System controller has not dequeued FIFO_H2U. Critical flag. Dequeue FIFO_H2U immediately to avoid the loss of incoming data. Carrier detect deasserted CD_DEASSERT Demodulator stops detecting the HART carrier signal of valid amplitude. Dequeue remaining data from FIFO_H2U. Monitor the empty flag to make sure that all data have been received. FIFO_H2U empty FIFO_H2U_EMPTY_FLAG Dequeue of FIFO_H2U by system controller. If using UART, wait to make sure the last character is received on UARTOUT. Transmit RTS asserted NA Toggle RTS pin low or write set MODEM_CFG.RTS = 1. Wait for clear-to-send confirmation flag. Clear to send (CTS) CTS_ASSERT RTS asserted and CD deasserted. Modulator enabled. Device starts modulating the carrier on MOD_OUT. Set desired FIFO_U2H level trigger threshold. Enqueue data into FIFO_U2H. Modulator automatically dequeues FIFO_U2H and transmits the HART data. FIFO_U2H level threshold trigger FIFO_U2H_LEVEL_FLAG Automatic dequeue of FIFO_U2H by HART modulator. Enqueue new data into FIFO_U2H when the level drops below the set threshold. Prevent FIFO_U2H from being empty to avoid a gap in transmission. FIFO_U2H full FIFO_U2H_FULL_FLAG System controller enqueue of the new data into FIFO_U2H. Critical flag.Stop enqueue of data into FIFO_U2H immediately to avoid loss of HART data. FIFO_U2H empty FIFO_U2H_EMPTY_FLAG Automatic dequeue of FIFO_U2H by HART modulator. System controller has not enqueued new data into FIFO_U2H. Critical flag in the middle of the data packet.Enqueue new data into FIFO_U2H immediately to avoid a gap in transmission. When the last character is dequeued from FIFO_U2H, wait until the character is fully transmitted on MOD_OUT before deasserting RTS. For CD, RTS, ALARM, and IRQ connection choices, see . To enable robust and error-free communicate on the HART bus, the events listed in #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/TABLE_BCL_BCQ_PQB must be detected from the AFEx82H1 by the system controller in a timely manner. If the IRQ signal is not directly connected to the system controller, poll the corresponding status flags. In UART mode, the automatic dequeue of FIFO_H2U simplifies event management significantly, and not all events must be translated to IRQs. When using the HART modem with the IRQ, the IRQ features help control communication in both directions. Enable IRQ functionality by following these steps: Configure the IRQ to be either edge or level sensitive using CONFIG.IRQ_LVL. See also . Configure the IRQ polarity with CONFIG.IRQ_POL, as needed per the respective system. See also . For SPI only mode, set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the UARTOUT pin. Also, set CONFIG.UART_DIS = 1 to disable all UART functionality. For UBM, use one of the two following methods: Set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the SDO pin, or Set CONFIG.UBM_IRQ_EN = 1 to enable interrupts being sent UARTOUT using UBM. After IRQ functionality is enabled, unmask all the required interrupt signals in the MODEM_STATUS_MASK register (set each bit = 0). IRQ Sources and Uses AFEx82H1HART STATE EVENT MODEM_STATUS FLAG ASSERTION METHOD #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWB ACTION Receive RTS deasserted CTS_DEASSERT Toggle RTS pin high or set MODEM_CFG.RTS = 0. Demodulator enabled and ready to receive HART data. Carrier detect asserted CD_ASSERT Demodulator detects the HART carrier signal of valid amplitude. Expect to receive HART data. Set desired FIFO_H2U level trigger threshold. FIFO_H2U level threshold trigger FIFO_H2U_LEVEL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. Dequeue data from FIFO_H2U when level exceeds the set threshold. Prevent FIFO_H2U from being full to avoid the loss of incoming data. FIFO_H2U full FIFO_H2U_FULL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. System controller has not dequeued FIFO_H2U. Critical flag. Dequeue FIFO_H2U immediately to avoid the loss of incoming data. Carrier detect deasserted CD_DEASSERT Demodulator stops detecting the HART carrier signal of valid amplitude. Dequeue remaining data from FIFO_H2U. Monitor the empty flag to make sure that all data have been received. FIFO_H2U empty FIFO_H2U_EMPTY_FLAG Dequeue of FIFO_H2U by system controller. If using UART, wait to make sure the last character is received on UARTOUT. Transmit RTS asserted NA Toggle RTS pin low or write set MODEM_CFG.RTS = 1. Wait for clear-to-send confirmation flag. Clear to send (CTS) CTS_ASSERT RTS asserted and CD deasserted. Modulator enabled. Device starts modulating the carrier on MOD_OUT. Set desired FIFO_U2H level trigger threshold. Enqueue data into FIFO_U2H. Modulator automatically dequeues FIFO_U2H and transmits the HART data. FIFO_U2H level threshold trigger FIFO_U2H_LEVEL_FLAG Automatic dequeue of FIFO_U2H by HART modulator. Enqueue new data into FIFO_U2H when the level drops below the set threshold. Prevent FIFO_U2H from being empty to avoid a gap in transmission. FIFO_U2H full FIFO_U2H_FULL_FLAG System controller enqueue of the new data into FIFO_U2H. Critical flag.Stop enqueue of data into FIFO_U2H immediately to avoid loss of HART data. FIFO_U2H empty FIFO_U2H_EMPTY_FLAG Automatic dequeue of FIFO_U2H by HART modulator. System controller has not enqueued new data into FIFO_U2H. Critical flag in the middle of the data packet.Enqueue new data into FIFO_U2H immediately to avoid a gap in transmission. When the last character is dequeued from FIFO_U2H, wait until the character is fully transmitted on MOD_OUT before deasserting RTS. For CD, RTS, ALARM, and IRQ connection choices, see . To enable robust and error-free communicate on the HART bus, the events listed in #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/TABLE_BCL_BCQ_PQB must be detected from the AFEx82H1 by the system controller in a timely manner. If the IRQ signal is not directly connected to the system controller, poll the corresponding status flags. In UART mode, the automatic dequeue of FIFO_H2U simplifies event management significantly, and not all events must be translated to IRQs.#GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/TABLE_BCL_BCQ_PQBAFEx82H1When using the HART modem with the IRQ, the IRQ features help control communication in both directions. Enable IRQ functionality by following these steps: Configure the IRQ to be either edge or level sensitive using CONFIG.IRQ_LVL. See also . Configure the IRQ polarity with CONFIG.IRQ_POL, as needed per the respective system. See also . For SPI only mode, set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the UARTOUT pin. Also, set CONFIG.UART_DIS = 1 to disable all UART functionality. For UBM, use one of the two following methods: Set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the SDO pin, or Set CONFIG.UBM_IRQ_EN = 1 to enable interrupts being sent UARTOUT using UBM. After IRQ functionality is enabled, unmask all the required interrupt signals in the MODEM_STATUS_MASK register (set each bit = 0). Configure the IRQ to be either edge or level sensitive using CONFIG.IRQ_LVL. See also . Configure the IRQ polarity with CONFIG.IRQ_POL, as needed per the respective system. See also . For SPI only mode, set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the UARTOUT pin. Also, set CONFIG.UART_DIS = 1 to disable all UART functionality. For UBM, use one of the two following methods: Set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the SDO pin, or Set CONFIG.UBM_IRQ_EN = 1 to enable interrupts being sent UARTOUT using UBM. After IRQ functionality is enabled, unmask all the required interrupt signals in the MODEM_STATUS_MASK register (set each bit = 0). Configure the IRQ to be either edge or level sensitive using CONFIG.IRQ_LVL. See also .Configure the IRQ polarity with CONFIG.IRQ_POL, as needed per the respective system. See also . For SPI only mode, set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the UARTOUT pin. Also, set CONFIG.UART_DIS = 1 to disable all UART functionality.For UBM, use one of the two following methods: Set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the SDO pin, or Set CONFIG.UBM_IRQ_EN = 1 to enable interrupts being sent UARTOUT using UBM. Set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the SDO pin, or Set CONFIG.UBM_IRQ_EN = 1 to enable interrupts being sent UARTOUT using UBM. Set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the SDO pin, or Set CONFIG.UBM_IRQ_EN = 1 to enable interrupts being sent UARTOUT using UBM.After IRQ functionality is enabled, unmask all the required interrupt signals in the MODEM_STATUS_MASK register (set each bit = 0). IRQ Sources and Uses AFEx82H1HART STATE EVENT MODEM_STATUS FLAG ASSERTION METHOD #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWB ACTION Receive RTS deasserted CTS_DEASSERT Toggle RTS pin high or set MODEM_CFG.RTS = 0. Demodulator enabled and ready to receive HART data. Carrier detect asserted CD_ASSERT Demodulator detects the HART carrier signal of valid amplitude. Expect to receive HART data. Set desired FIFO_H2U level trigger threshold. FIFO_H2U level threshold trigger FIFO_H2U_LEVEL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. Dequeue data from FIFO_H2U when level exceeds the set threshold. Prevent FIFO_H2U from being full to avoid the loss of incoming data. FIFO_H2U full FIFO_H2U_FULL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. System controller has not dequeued FIFO_H2U. Critical flag. Dequeue FIFO_H2U immediately to avoid the loss of incoming data. Carrier detect deasserted CD_DEASSERT Demodulator stops detecting the HART carrier signal of valid amplitude. Dequeue remaining data from FIFO_H2U. Monitor the empty flag to make sure that all data have been received. FIFO_H2U empty FIFO_H2U_EMPTY_FLAG Dequeue of FIFO_H2U by system controller. If using UART, wait to make sure the last character is received on UARTOUT. Transmit RTS asserted NA Toggle RTS pin low or write set MODEM_CFG.RTS = 1. Wait for clear-to-send confirmation flag. Clear to send (CTS) CTS_ASSERT RTS asserted and CD deasserted. Modulator enabled. Device starts modulating the carrier on MOD_OUT. Set desired FIFO_U2H level trigger threshold. Enqueue data into FIFO_U2H. Modulator automatically dequeues FIFO_U2H and transmits the HART data. FIFO_U2H level threshold trigger FIFO_U2H_LEVEL_FLAG Automatic dequeue of FIFO_U2H by HART modulator. Enqueue new data into FIFO_U2H when the level drops below the set threshold. Prevent FIFO_U2H from being empty to avoid a gap in transmission. FIFO_U2H full FIFO_U2H_FULL_FLAG System controller enqueue of the new data into FIFO_U2H. Critical flag.Stop enqueue of data into FIFO_U2H immediately to avoid loss of HART data. FIFO_U2H empty FIFO_U2H_EMPTY_FLAG Automatic dequeue of FIFO_U2H by HART modulator. System controller has not enqueued new data into FIFO_U2H. Critical flag in the middle of the data packet.Enqueue new data into FIFO_U2H immediately to avoid a gap in transmission. When the last character is dequeued from FIFO_U2H, wait until the character is fully transmitted on MOD_OUT before deasserting RTS. IRQ Sources and Uses AFEx82H1HART STATE EVENT MODEM_STATUS FLAG ASSERTION METHOD #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWB ACTION Receive RTS deasserted CTS_DEASSERT Toggle RTS pin high or set MODEM_CFG.RTS = 0. Demodulator enabled and ready to receive HART data. Carrier detect asserted CD_ASSERT Demodulator detects the HART carrier signal of valid amplitude. Expect to receive HART data. Set desired FIFO_H2U level trigger threshold. FIFO_H2U level threshold trigger FIFO_H2U_LEVEL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. Dequeue data from FIFO_H2U when level exceeds the set threshold. Prevent FIFO_H2U from being full to avoid the loss of incoming data. FIFO_H2U full FIFO_H2U_FULL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. System controller has not dequeued FIFO_H2U. Critical flag. Dequeue FIFO_H2U immediately to avoid the loss of incoming data. Carrier detect deasserted CD_DEASSERT Demodulator stops detecting the HART carrier signal of valid amplitude. Dequeue remaining data from FIFO_H2U. Monitor the empty flag to make sure that all data have been received. FIFO_H2U empty FIFO_H2U_EMPTY_FLAG Dequeue of FIFO_H2U by system controller. If using UART, wait to make sure the last character is received on UARTOUT. Transmit RTS asserted NA Toggle RTS pin low or write set MODEM_CFG.RTS = 1. Wait for clear-to-send confirmation flag. Clear to send (CTS) CTS_ASSERT RTS asserted and CD deasserted. Modulator enabled. Device starts modulating the carrier on MOD_OUT. Set desired FIFO_U2H level trigger threshold. Enqueue data into FIFO_U2H. Modulator automatically dequeues FIFO_U2H and transmits the HART data. FIFO_U2H level threshold trigger FIFO_U2H_LEVEL_FLAG Automatic dequeue of FIFO_U2H by HART modulator. Enqueue new data into FIFO_U2H when the level drops below the set threshold. Prevent FIFO_U2H from being empty to avoid a gap in transmission. FIFO_U2H full FIFO_U2H_FULL_FLAG System controller enqueue of the new data into FIFO_U2H. Critical flag.Stop enqueue of data into FIFO_U2H immediately to avoid loss of HART data. FIFO_U2H empty FIFO_U2H_EMPTY_FLAG Automatic dequeue of FIFO_U2H by HART modulator. System controller has not enqueued new data into FIFO_U2H. Critical flag in the middle of the data packet.Enqueue new data into FIFO_U2H immediately to avoid a gap in transmission. When the last character is dequeued from FIFO_U2H, wait until the character is fully transmitted on MOD_OUT before deasserting RTS. AFEx82H1HART STATE EVENT MODEM_STATUS FLAG ASSERTION METHOD #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWB ACTION AFEx82H1HART STATE EVENT MODEM_STATUS FLAG ASSERTION METHOD #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWB ACTION AFEx82H1HART STATE AFEx82H1EVENTMODEM_STATUS FLAGASSERTION METHOD #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWB #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWB #GUID-7BD3B51C-2BC1-40AC-B6B4-0BBE95CF9F75/LI_KDK_53K_KWBACTION Receive RTS deasserted CTS_DEASSERT Toggle RTS pin high or set MODEM_CFG.RTS = 0. Demodulator enabled and ready to receive HART data. Carrier detect asserted CD_ASSERT Demodulator detects the HART carrier signal of valid amplitude. Expect to receive HART data. Set desired FIFO_H2U level trigger threshold. FIFO_H2U level threshold trigger FIFO_H2U_LEVEL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. Dequeue data from FIFO_H2U when level exceeds the set threshold. Prevent FIFO_H2U from being full to avoid the loss of incoming data. FIFO_H2U full FIFO_H2U_FULL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. System controller has not dequeued FIFO_H2U. Critical flag. Dequeue FIFO_H2U immediately to avoid the loss of incoming data. Carrier detect deasserted CD_DEASSERT Demodulator stops detecting the HART carrier signal of valid amplitude. Dequeue remaining data from FIFO_H2U. Monitor the empty flag to make sure that all data have been received. FIFO_H2U empty FIFO_H2U_EMPTY_FLAG Dequeue of FIFO_H2U by system controller. If using UART, wait to make sure the last character is received on UARTOUT. Transmit RTS asserted NA Toggle RTS pin low or write set MODEM_CFG.RTS = 1. Wait for clear-to-send confirmation flag. Clear to send (CTS) CTS_ASSERT RTS asserted and CD deasserted. Modulator enabled. Device starts modulating the carrier on MOD_OUT. Set desired FIFO_U2H level trigger threshold. Enqueue data into FIFO_U2H. Modulator automatically dequeues FIFO_U2H and transmits the HART data. FIFO_U2H level threshold trigger FIFO_U2H_LEVEL_FLAG Automatic dequeue of FIFO_U2H by HART modulator. Enqueue new data into FIFO_U2H when the level drops below the set threshold. Prevent FIFO_U2H from being empty to avoid a gap in transmission. FIFO_U2H full FIFO_U2H_FULL_FLAG System controller enqueue of the new data into FIFO_U2H. Critical flag.Stop enqueue of data into FIFO_U2H immediately to avoid loss of HART data. FIFO_U2H empty FIFO_U2H_EMPTY_FLAG Automatic dequeue of FIFO_U2H by HART modulator. System controller has not enqueued new data into FIFO_U2H. Critical flag in the middle of the data packet.Enqueue new data into FIFO_U2H immediately to avoid a gap in transmission. When the last character is dequeued from FIFO_U2H, wait until the character is fully transmitted on MOD_OUT before deasserting RTS. Receive RTS deasserted CTS_DEASSERT Toggle RTS pin high or set MODEM_CFG.RTS = 0. Demodulator enabled and ready to receive HART data. ReceiveRTS deassertedCTS_DEASSERT Toggle RTS pin high or set MODEM_CFG.RTS = 0.RTSDemodulator enabled and ready to receive HART data. Carrier detect asserted CD_ASSERT Demodulator detects the HART carrier signal of valid amplitude. Expect to receive HART data. Set desired FIFO_H2U level trigger threshold. Carrier detect assertedCD_ASSERT Demodulator detects the HART carrier signal of valid amplitude.Expect to receive HART data. Set desired FIFO_H2U level trigger threshold. FIFO_H2U level threshold trigger FIFO_H2U_LEVEL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. Dequeue data from FIFO_H2U when level exceeds the set threshold. Prevent FIFO_H2U from being full to avoid the loss of incoming data. FIFO_H2U level threshold triggerFIFO_H2U_LEVEL_FLAGAutomatic enqueue of FIFO_H2U by HART demodulator. Dequeue data from FIFO_H2U when level exceeds the set threshold. Prevent FIFO_H2U from being full to avoid the loss of incoming data. FIFO_H2U full FIFO_H2U_FULL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. System controller has not dequeued FIFO_H2U. Critical flag. Dequeue FIFO_H2U immediately to avoid the loss of incoming data. FIFO_H2U fullFIFO_H2U_FULL_FLAGAutomatic enqueue of FIFO_H2U by HART demodulator. System controller has not dequeued FIFO_H2U.Critical flag. Dequeue FIFO_H2U immediately to avoid the loss of incoming data. Carrier detect deasserted CD_DEASSERT Demodulator stops detecting the HART carrier signal of valid amplitude. Dequeue remaining data from FIFO_H2U. Monitor the empty flag to make sure that all data have been received. Carrier detect deassertedCD_DEASSERTDemodulator stops detecting the HART carrier signal of valid amplitude.Dequeue remaining data from FIFO_H2U. Monitor the empty flag to make sure that all data have been received. FIFO_H2U empty FIFO_H2U_EMPTY_FLAG Dequeue of FIFO_H2U by system controller. If using UART, wait to make sure the last character is received on UARTOUT. FIFO_H2U emptyFIFO_H2U_EMPTY_FLAGDequeue of FIFO_H2U by system controller.If using UART, wait to make sure the last character is received on UARTOUT. Transmit RTS asserted NA Toggle RTS pin low or write set MODEM_CFG.RTS = 1. Wait for clear-to-send confirmation flag. Transmit RTS assertedNAToggle RTS pin low or write set MODEM_CFG.RTS = 1.RTS Wait for clear-to-send confirmation flag. Wait for clear-to-send confirmation flag. Clear to send (CTS) CTS_ASSERT RTS asserted and CD deasserted. Modulator enabled. Device starts modulating the carrier on MOD_OUT. Set desired FIFO_U2H level trigger threshold. Enqueue data into FIFO_U2H. Modulator automatically dequeues FIFO_U2H and transmits the HART data. Clear to send (CTS)CTS_ASSERTRTS asserted and CD deasserted.Modulator enabled. Device starts modulating the carrier on MOD_OUT. Set desired FIFO_U2H level trigger threshold. Enqueue data into FIFO_U2H. Modulator automatically dequeues FIFO_U2H and transmits the HART data. FIFO_U2H level threshold trigger FIFO_U2H_LEVEL_FLAG Automatic dequeue of FIFO_U2H by HART modulator. Enqueue new data into FIFO_U2H when the level drops below the set threshold. Prevent FIFO_U2H from being empty to avoid a gap in transmission. FIFO_U2H level threshold triggerFIFO_U2H_LEVEL_FLAGAutomatic dequeue of FIFO_U2H by HART modulator. Enqueue new data into FIFO_U2H when the level drops below the set threshold. Prevent FIFO_U2H from being empty to avoid a gap in transmission. FIFO_U2H full FIFO_U2H_FULL_FLAG System controller enqueue of the new data into FIFO_U2H. Critical flag.Stop enqueue of data into FIFO_U2H immediately to avoid loss of HART data. FIFO_U2H fullFIFO_U2H_FULL_FLAGSystem controller enqueue of the new data into FIFO_U2H.Critical flag.Stop enqueue of data into FIFO_U2H immediately to avoid loss of HART data. FIFO_U2H empty FIFO_U2H_EMPTY_FLAG Automatic dequeue of FIFO_U2H by HART modulator. System controller has not enqueued new data into FIFO_U2H. Critical flag in the middle of the data packet.Enqueue new data into FIFO_U2H immediately to avoid a gap in transmission. When the last character is dequeued from FIFO_U2H, wait until the character is fully transmitted on MOD_OUT before deasserting RTS. FIFO_U2H emptyFIFO_U2H_EMPTY_FLAGAutomatic dequeue of FIFO_U2H by HART modulator. System controller has not enqueued new data into FIFO_U2H.Critical flag in the middle of the data packet.Enqueue new data into FIFO_U2H immediately to avoid a gap in transmission. When the last character is dequeued from FIFO_U2H, wait until the character is fully transmitted on MOD_OUT before deasserting RTS. For CD, RTS, ALARM, and IRQ connection choices, see . For CD, RTS, ALARM, and IRQ connection choices, see .RTSALARM HART Communication Using the SPI HART bus communication activity is reported to the host controller through the IRQ signal routed to the UARTOUT pin and MODEM_STATUS register. Read the MODEM_STATUS register to determine the source of the IRQ when an IRQ is received. If the UARTOUT pin is not connected, poll the status registers regularly through the SPI. To transmit data, set up the desired FIFO_U2H level thresholds using FIFO_CFG.U2H_LEVEL_SET. Assert the RTS. After CTS_ASSERT is set, begin to fill FIFO_U2H. Enqueue enough data into FIFO_U2H to fill the FIFO above the set threshold level. The HART modulator automatically dequeues the data from FIFO_U2H and transmits the data on MOD_OUT. When FIFO_U2H level drops below the set threshold, an IRQ triggers, indicating that new data bytes can be enqueued without losing any data. After the last set of data have been enqueued into FIFO_U2H, an IRQ event triggered by the level flag can be ignored. Wait for the IRQ event triggered by FIFO_U2H_EMPTY_FLAG. Deassert the RTS after required delay; see also . When the RTS is deasserted, the CTS_DEASSERT bit is set. CTS_DEASSERT is an informational bit. To receive data, set up an IRQ event based on CD_ASSERT to know when the carrier is detected and the new data bytes are expected. Also, set up the additional IRQ events to trigger each time FIFO_H2U_LEVEL_FLAG is set. Select the desired level of FIFO_H2U. Dequeue the data from FIFO_H2U every time the level exceeds the set threshold. Also, set up IRQ event trigger based on CD_DEASSERT to know when all the data have been received. At this point, monitor FIFO_H2U.EMPTY_FLAG when dequeuing each character to know when FIFO_H2U is empty and all the data bytes have been dequeued and transmitted to the microcontroller. Alternatively, the CD pin can be directly connected to the microcontroller to monitor the status of the HART bus. In this configuration, mask CD_ASSERT flag by setting MODEM_STATUS_MASK.CD_ASSERT bit = 1 to prevent CD_ASSERT from generating an IRQ event. HART Communication Using the SPI HART bus communication activity is reported to the host controller through the IRQ signal routed to the UARTOUT pin and MODEM_STATUS register. Read the MODEM_STATUS register to determine the source of the IRQ when an IRQ is received. If the UARTOUT pin is not connected, poll the status registers regularly through the SPI. To transmit data, set up the desired FIFO_U2H level thresholds using FIFO_CFG.U2H_LEVEL_SET. Assert the RTS. After CTS_ASSERT is set, begin to fill FIFO_U2H. Enqueue enough data into FIFO_U2H to fill the FIFO above the set threshold level. The HART modulator automatically dequeues the data from FIFO_U2H and transmits the data on MOD_OUT. When FIFO_U2H level drops below the set threshold, an IRQ triggers, indicating that new data bytes can be enqueued without losing any data. After the last set of data have been enqueued into FIFO_U2H, an IRQ event triggered by the level flag can be ignored. Wait for the IRQ event triggered by FIFO_U2H_EMPTY_FLAG. Deassert the RTS after required delay; see also . When the RTS is deasserted, the CTS_DEASSERT bit is set. CTS_DEASSERT is an informational bit. To receive data, set up an IRQ event based on CD_ASSERT to know when the carrier is detected and the new data bytes are expected. Also, set up the additional IRQ events to trigger each time FIFO_H2U_LEVEL_FLAG is set. Select the desired level of FIFO_H2U. Dequeue the data from FIFO_H2U every time the level exceeds the set threshold. Also, set up IRQ event trigger based on CD_DEASSERT to know when all the data have been received. At this point, monitor FIFO_H2U.EMPTY_FLAG when dequeuing each character to know when FIFO_H2U is empty and all the data bytes have been dequeued and transmitted to the microcontroller. Alternatively, the CD pin can be directly connected to the microcontroller to monitor the status of the HART bus. In this configuration, mask CD_ASSERT flag by setting MODEM_STATUS_MASK.CD_ASSERT bit = 1 to prevent CD_ASSERT from generating an IRQ event. HART bus communication activity is reported to the host controller through the IRQ signal routed to the UARTOUT pin and MODEM_STATUS register. Read the MODEM_STATUS register to determine the source of the IRQ when an IRQ is received. If the UARTOUT pin is not connected, poll the status registers regularly through the SPI. To transmit data, set up the desired FIFO_U2H level thresholds using FIFO_CFG.U2H_LEVEL_SET. Assert the RTS. After CTS_ASSERT is set, begin to fill FIFO_U2H. Enqueue enough data into FIFO_U2H to fill the FIFO above the set threshold level. The HART modulator automatically dequeues the data from FIFO_U2H and transmits the data on MOD_OUT. When FIFO_U2H level drops below the set threshold, an IRQ triggers, indicating that new data bytes can be enqueued without losing any data. After the last set of data have been enqueued into FIFO_U2H, an IRQ event triggered by the level flag can be ignored. Wait for the IRQ event triggered by FIFO_U2H_EMPTY_FLAG. Deassert the RTS after required delay; see also . When the RTS is deasserted, the CTS_DEASSERT bit is set. CTS_DEASSERT is an informational bit. To receive data, set up an IRQ event based on CD_ASSERT to know when the carrier is detected and the new data bytes are expected. Also, set up the additional IRQ events to trigger each time FIFO_H2U_LEVEL_FLAG is set. Select the desired level of FIFO_H2U. Dequeue the data from FIFO_H2U every time the level exceeds the set threshold. Also, set up IRQ event trigger based on CD_DEASSERT to know when all the data have been received. At this point, monitor FIFO_H2U.EMPTY_FLAG when dequeuing each character to know when FIFO_H2U is empty and all the data bytes have been dequeued and transmitted to the microcontroller. Alternatively, the CD pin can be directly connected to the microcontroller to monitor the status of the HART bus. In this configuration, mask CD_ASSERT flag by setting MODEM_STATUS_MASK.CD_ASSERT bit = 1 to prevent CD_ASSERT from generating an IRQ event. HART bus communication activity is reported to the host controller through the IRQ signal routed to the UARTOUT pin and MODEM_STATUS register. Read the MODEM_STATUS register to determine the source of the IRQ when an IRQ is received. If the UARTOUT pin is not connected, poll the status registers regularly through the SPI.To transmit data, set up the desired FIFO_U2H level thresholds using FIFO_CFG.U2H_LEVEL_SET. Assert the RTS. After CTS_ASSERT is set, begin to fill FIFO_U2H. Enqueue enough data into FIFO_U2H to fill the FIFO above the set threshold level. The HART modulator automatically dequeues the data from FIFO_U2H and transmits the data on MOD_OUT. When FIFO_U2H level drops below the set threshold, an IRQ triggers, indicating that new data bytes can be enqueued without losing any data. After the last set of data have been enqueued into FIFO_U2H, an IRQ event triggered by the level flag can be ignored. Wait for the IRQ event triggered by FIFO_U2H_EMPTY_FLAG. Deassert the RTS after required delay; see also . When the RTS is deasserted, the CTS_DEASSERT bit is set. CTS_DEASSERT is an informational bit.To receive data, set up an IRQ event based on CD_ASSERT to know when the carrier is detected and the new data bytes are expected. Also, set up the additional IRQ events to trigger each time FIFO_H2U_LEVEL_FLAG is set. Select the desired level of FIFO_H2U. Dequeue the data from FIFO_H2U every time the level exceeds the set threshold. Also, set up IRQ event trigger based on CD_DEASSERT to know when all the data have been received. At this point, monitor FIFO_H2U.EMPTY_FLAG when dequeuing each character to know when FIFO_H2U is empty and all the data bytes have been dequeued and transmitted to the microcontroller. Alternatively, the CD pin can be directly connected to the microcontroller to monitor the status of the HART bus. In this configuration, mask CD_ASSERT flag by setting MODEM_STATUS_MASK.CD_ASSERT bit = 1 to prevent CD_ASSERT from generating an IRQ event. HART Communication Using UART In SPI plus UART mode, the UART data are transmitted and received at 1200 baud, which is matched to the HART FSK input and output signals. Both SDO and UARTOUT pins are used; therefore, the IRQ functionality is not available in SPI plus UART mode. FIFO_H2U level monitoring is not required because any HART data received by the demodulator and enqueued into FIFO_H2U are automatically dequeued and transmitted on UARTOUT. FIFO_U2H level monitoring is also not required if HART bus communication activity is interfaced to the host controller through the CD and RTS pins. The host controller can properly time the RTS pin to transmit the HART data when no carrier is detected on the bus. If the CD and RTS pins are not used in SPI plus UART mode, the host controller can periodically poll the MODEM_STATUS register through the SPI to detect when the carrier is not present on the HART bus, and assert the request to send by setting MODEM_CFG.RTS bit = 1. In UBM, the UART data are transmitted and received at 9600 baud. The HART data characters are interleaved with break commands for register map access or interrupt reporting; see also . Similar to SPI plus UART mode, monitoring of FIFO_H2U and FIFO_U2H levels is not required. The CD and RTS pins are available to interface the HART bus activity with the microcontroller. IRQ functionality is also available on the SDO pin. If the SDO pin is connected to the microcontroller, the IRQ event based on CD_ASSERT can be set to report when the carrier is detected. In this case, CD pin connection to the microcontroller is not required. Similarly, RTS pin connection is not required if MODEM_CFG.RTS is used to issue a request to send. The SDO pin connection to the microcontroller is also not required if the microcontroller can periodically poll the MODEM_STATUS register using break commands, and monitor all the required flags. HART Communication Using UART In SPI plus UART mode, the UART data are transmitted and received at 1200 baud, which is matched to the HART FSK input and output signals. Both SDO and UARTOUT pins are used; therefore, the IRQ functionality is not available in SPI plus UART mode. FIFO_H2U level monitoring is not required because any HART data received by the demodulator and enqueued into FIFO_H2U are automatically dequeued and transmitted on UARTOUT. FIFO_U2H level monitoring is also not required if HART bus communication activity is interfaced to the host controller through the CD and RTS pins. The host controller can properly time the RTS pin to transmit the HART data when no carrier is detected on the bus. If the CD and RTS pins are not used in SPI plus UART mode, the host controller can periodically poll the MODEM_STATUS register through the SPI to detect when the carrier is not present on the HART bus, and assert the request to send by setting MODEM_CFG.RTS bit = 1. In UBM, the UART data are transmitted and received at 9600 baud. The HART data characters are interleaved with break commands for register map access or interrupt reporting; see also . Similar to SPI plus UART mode, monitoring of FIFO_H2U and FIFO_U2H levels is not required. The CD and RTS pins are available to interface the HART bus activity with the microcontroller. IRQ functionality is also available on the SDO pin. If the SDO pin is connected to the microcontroller, the IRQ event based on CD_ASSERT can be set to report when the carrier is detected. In this case, CD pin connection to the microcontroller is not required. Similarly, RTS pin connection is not required if MODEM_CFG.RTS is used to issue a request to send. The SDO pin connection to the microcontroller is also not required if the microcontroller can periodically poll the MODEM_STATUS register using break commands, and monitor all the required flags. In SPI plus UART mode, the UART data are transmitted and received at 1200 baud, which is matched to the HART FSK input and output signals. Both SDO and UARTOUT pins are used; therefore, the IRQ functionality is not available in SPI plus UART mode. FIFO_H2U level monitoring is not required because any HART data received by the demodulator and enqueued into FIFO_H2U are automatically dequeued and transmitted on UARTOUT. FIFO_U2H level monitoring is also not required if HART bus communication activity is interfaced to the host controller through the CD and RTS pins. The host controller can properly time the RTS pin to transmit the HART data when no carrier is detected on the bus. If the CD and RTS pins are not used in SPI plus UART mode, the host controller can periodically poll the MODEM_STATUS register through the SPI to detect when the carrier is not present on the HART bus, and assert the request to send by setting MODEM_CFG.RTS bit = 1. In UBM, the UART data are transmitted and received at 9600 baud. The HART data characters are interleaved with break commands for register map access or interrupt reporting; see also . Similar to SPI plus UART mode, monitoring of FIFO_H2U and FIFO_U2H levels is not required. The CD and RTS pins are available to interface the HART bus activity with the microcontroller. IRQ functionality is also available on the SDO pin. If the SDO pin is connected to the microcontroller, the IRQ event based on CD_ASSERT can be set to report when the carrier is detected. In this case, CD pin connection to the microcontroller is not required. Similarly, RTS pin connection is not required if MODEM_CFG.RTS is used to issue a request to send. The SDO pin connection to the microcontroller is also not required if the microcontroller can periodically poll the MODEM_STATUS register using break commands, and monitor all the required flags. In SPI plus UART mode, the UART data are transmitted and received at 1200 baud, which is matched to the HART FSK input and output signals. Both SDO and UARTOUT pins are used; therefore, the IRQ functionality is not available in SPI plus UART mode. FIFO_H2U level monitoring is not required because any HART data received by the demodulator and enqueued into FIFO_H2U are automatically dequeued and transmitted on UARTOUT. FIFO_U2H level monitoring is also not required if HART bus communication activity is interfaced to the host controller through the CD and RTS pins. The host controller can properly time the RTS pin to transmit the HART data when no carrier is detected on the bus. If the CD and RTS pins are not used in SPI plus UART mode, the host controller can periodically poll the MODEM_STATUS register through the SPI to detect when the carrier is not present on the HART bus, and assert the request to send by setting MODEM_CFG.RTS bit = 1.RTSRTSRTSIn UBM, the UART data are transmitted and received at 9600 baud. The HART data characters are interleaved with break commands for register map access or interrupt reporting; see also . Similar to SPI plus UART mode, monitoring of FIFO_H2U and FIFO_U2H levels is not required. The CD and RTS pins are available to interface the HART bus activity with the microcontroller. IRQ functionality is also available on the SDO pin. If the SDO pin is connected to the microcontroller, the IRQ event based on CD_ASSERT can be set to report when the carrier is detected. In this case, CD pin connection to the microcontroller is not required. Similarly, RTS pin connection is not required if MODEM_CFG.RTS is used to issue a request to send. The SDO pin connection to the microcontroller is also not required if the microcontroller can periodically poll the MODEM_STATUS register using break commands, and monitor all the required flags.RTSRTS Memory Built-In Self-Test (MBIST) Memory built-in self-test (MBIST) verifies the validity of the static random-access memory (SRAM) used for the FIFO buffers. When initiated, the MBIST takes control of the SRAM module until completion. Disable HART communication while the MBIST is running. Communication with the FIFO buffers during the MBIST produces unreliable results. Two status bits, GEN_STATUS.MBIST_DONE and GEN_STATUS.MBIST_FAIL, can be monitored for completion or failure, or used to create IRQ events. Do not try to read back the GEN_STATUS register while the MBIST is running. The MBIST control logic generates narrow pulses for the MBIST_DONE and MBIST_FAIL status flags. The status flags can be missed if these pulses occur during the readback of the GEN_STATUS register. To avoid missing the MBIST_DONE flag, mask all the status bits except GEN_STATUS_MASK.MBIST_DONE and then either: monitor for an IRQ event, or periodically send a NOP and check the GEN_IRQ status bit. Wait until MBIST_DONE is reported, verify the status of the MBIST_FAIL flag, and then resume normal operation. Memory Built-In Self-Test (MBIST) Memory built-in self-test (MBIST) verifies the validity of the static random-access memory (SRAM) used for the FIFO buffers. When initiated, the MBIST takes control of the SRAM module until completion. Disable HART communication while the MBIST is running. Communication with the FIFO buffers during the MBIST produces unreliable results. Two status bits, GEN_STATUS.MBIST_DONE and GEN_STATUS.MBIST_FAIL, can be monitored for completion or failure, or used to create IRQ events. Do not try to read back the GEN_STATUS register while the MBIST is running. The MBIST control logic generates narrow pulses for the MBIST_DONE and MBIST_FAIL status flags. The status flags can be missed if these pulses occur during the readback of the GEN_STATUS register. To avoid missing the MBIST_DONE flag, mask all the status bits except GEN_STATUS_MASK.MBIST_DONE and then either: monitor for an IRQ event, or periodically send a NOP and check the GEN_IRQ status bit. Wait until MBIST_DONE is reported, verify the status of the MBIST_FAIL flag, and then resume normal operation. Memory built-in self-test (MBIST) verifies the validity of the static random-access memory (SRAM) used for the FIFO buffers. When initiated, the MBIST takes control of the SRAM module until completion. Disable HART communication while the MBIST is running. Communication with the FIFO buffers during the MBIST produces unreliable results. Two status bits, GEN_STATUS.MBIST_DONE and GEN_STATUS.MBIST_FAIL, can be monitored for completion or failure, or used to create IRQ events. Do not try to read back the GEN_STATUS register while the MBIST is running. The MBIST control logic generates narrow pulses for the MBIST_DONE and MBIST_FAIL status flags. The status flags can be missed if these pulses occur during the readback of the GEN_STATUS register. To avoid missing the MBIST_DONE flag, mask all the status bits except GEN_STATUS_MASK.MBIST_DONE and then either: monitor for an IRQ event, or periodically send a NOP and check the GEN_IRQ status bit. Wait until MBIST_DONE is reported, verify the status of the MBIST_FAIL flag, and then resume normal operation. Memory built-in self-test (MBIST) verifies the validity of the static random-access memory (SRAM) used for the FIFO buffers. When initiated, the MBIST takes control of the SRAM module until completion.Disable HART communication while the MBIST is running. Communication with the FIFO buffers during the MBIST produces unreliable results. Two status bits, GEN_STATUS.MBIST_DONE and GEN_STATUS.MBIST_FAIL, can be monitored for completion or failure, or used to create IRQ events.Do not try to read back the GEN_STATUS register while the MBIST is running. The MBIST control logic generates narrow pulses for the MBIST_DONE and MBIST_FAIL status flags. The status flags can be missed if these pulses occur during the readback of the GEN_STATUS register. To avoid missing the MBIST_DONE flag, mask all the status bits except GEN_STATUS_MASK.MBIST_DONE and then either: monitor for an IRQ event, or periodically send a NOP and check the GEN_IRQ status bit. monitor for an IRQ event, orperiodically send a NOP and check the GEN_IRQ status bit.Wait until MBIST_DONE is reported, verify the status of the MBIST_FAIL flag, and then resume normal operation. Internal Reference The AFEx82H1 family of devices includes a 1.25-V precision band-gap reference. The internal reference is externally available at the VREFIO pin and sources up to 2.5 mA. For noise filtering, use a 100-nF capacitor between the reference output and GND. The internal reference circuit is enabled or disabled by using the REF_EN pin. A logic high on this pin enables the internal reference, and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal reference, and the device expects to have 1.25 V from external VREF at the VREFIO pin. An invalid reference voltage asserts an alarm condition. The DAC response depends on the VREF_FLT setting in the ALARM_ACT register (10h). Internal Reference The AFEx82H1 family of devices includes a 1.25-V precision band-gap reference. The internal reference is externally available at the VREFIO pin and sources up to 2.5 mA. For noise filtering, use a 100-nF capacitor between the reference output and GND. The internal reference circuit is enabled or disabled by using the REF_EN pin. A logic high on this pin enables the internal reference, and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal reference, and the device expects to have 1.25 V from external VREF at the VREFIO pin. An invalid reference voltage asserts an alarm condition. The DAC response depends on the VREF_FLT setting in the ALARM_ACT register (10h). The AFEx82H1 family of devices includes a 1.25-V precision band-gap reference. The internal reference is externally available at the VREFIO pin and sources up to 2.5 mA. For noise filtering, use a 100-nF capacitor between the reference output and GND. The internal reference circuit is enabled or disabled by using the REF_EN pin. A logic high on this pin enables the internal reference, and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal reference, and the device expects to have 1.25 V from external VREF at the VREFIO pin. An invalid reference voltage asserts an alarm condition. The DAC response depends on the VREF_FLT setting in the ALARM_ACT register (10h). The AFEx82H1 family of devices includes a 1.25-V precision band-gap reference. The internal reference is externally available at the VREFIO pin and sources up to 2.5 mA. For noise filtering, use a 100-nF capacitor between the reference output and GND. AFEx82H1The internal reference circuit is enabled or disabled by using the REF_EN pin. A logic high on this pin enables the internal reference, and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal reference, and the device expects to have 1.25 V from external VREF at the VREFIO pin.An invalid reference voltage asserts an alarm condition. The DAC response depends on the VREF_FLT setting in the ALARM_ACT register (10h). Integrated Precision Oscillator The internal time base of the device is provided by an internal oscillator that is trimmed to less than 0.5% tolerance at room temperature. The precision oscillator is the timing source for ADC conversions. At power up, the internal oscillator and ADC take roughly 300 µs to reach < 1% error stability. After the clock stabilizes, the ADC data output is accurate to the electrical specifications provided in . Integrated Precision Oscillator The internal time base of the device is provided by an internal oscillator that is trimmed to less than 0.5% tolerance at room temperature. The precision oscillator is the timing source for ADC conversions. At power up, the internal oscillator and ADC take roughly 300 µs to reach < 1% error stability. After the clock stabilizes, the ADC data output is accurate to the electrical specifications provided in . The internal time base of the device is provided by an internal oscillator that is trimmed to less than 0.5% tolerance at room temperature. The precision oscillator is the timing source for ADC conversions. At power up, the internal oscillator and ADC take roughly 300 µs to reach < 1% error stability. After the clock stabilizes, the ADC data output is accurate to the electrical specifications provided in . The internal time base of the device is provided by an internal oscillator that is trimmed to less than 0.5% tolerance at room temperature. The precision oscillator is the timing source for ADC conversions. At power up, the internal oscillator and ADC take roughly 300 µs to reach < 1% error stability. After the clock stabilizes, the ADC data output is accurate to the electrical specifications provided in . Precision Oscillator Diagnostics The AFEx82H1 features two methods to continuously detect the functional status of the internal precision oscillator. The first method requires a connection from the AFEx82H1 to the system controller. To use the first method, program the AFEx82H1 to output a subdivided internal oscillator clock signal on the CLK_OUT pin. Write to the CONFIG.CLKO register field (see ) to enable the output with the chosen divider or to disable the output. The output digital signal is compliant to the . The CLK_OUT pin is also a shared GPIO pin. For details on connecting CLK_OUT and CLK_OUT interoperability as a GPIO pin , see . The second method does not require a connection from the AFEx82H1 and is a polled-communication-based method to determine the functionality of the internal oscillator using SPI communication. See and for SPI communication details and SDO status bits details, respectively. The OSC_DIV_2 bit reports the logical value of a subdivided internal oscillator signal (divided by 2) sampled at the CS falling edge. Use an appropriate SCLK frequency and interval between SPI frames to capture bit changes from frame to frame as a method of verifying the continued proper operation of the clock. Similar status reports of the logical value of a subdivided internal oscillator signal (divided by 1024) are available in UBM as the OSC_DIV_1024 bit. For details on UBM frames and timing, see . Precision Oscillator Diagnostics The AFEx82H1 features two methods to continuously detect the functional status of the internal precision oscillator. The first method requires a connection from the AFEx82H1 to the system controller. To use the first method, program the AFEx82H1 to output a subdivided internal oscillator clock signal on the CLK_OUT pin. Write to the CONFIG.CLKO register field (see ) to enable the output with the chosen divider or to disable the output. The output digital signal is compliant to the . The CLK_OUT pin is also a shared GPIO pin. For details on connecting CLK_OUT and CLK_OUT interoperability as a GPIO pin , see . The second method does not require a connection from the AFEx82H1 and is a polled-communication-based method to determine the functionality of the internal oscillator using SPI communication. See and for SPI communication details and SDO status bits details, respectively. The OSC_DIV_2 bit reports the logical value of a subdivided internal oscillator signal (divided by 2) sampled at the CS falling edge. Use an appropriate SCLK frequency and interval between SPI frames to capture bit changes from frame to frame as a method of verifying the continued proper operation of the clock. Similar status reports of the logical value of a subdivided internal oscillator signal (divided by 1024) are available in UBM as the OSC_DIV_1024 bit. For details on UBM frames and timing, see . The AFEx82H1 features two methods to continuously detect the functional status of the internal precision oscillator. The first method requires a connection from the AFEx82H1 to the system controller. To use the first method, program the AFEx82H1 to output a subdivided internal oscillator clock signal on the CLK_OUT pin. Write to the CONFIG.CLKO register field (see ) to enable the output with the chosen divider or to disable the output. The output digital signal is compliant to the . The CLK_OUT pin is also a shared GPIO pin. For details on connecting CLK_OUT and CLK_OUT interoperability as a GPIO pin , see . The second method does not require a connection from the AFEx82H1 and is a polled-communication-based method to determine the functionality of the internal oscillator using SPI communication. See and for SPI communication details and SDO status bits details, respectively. The OSC_DIV_2 bit reports the logical value of a subdivided internal oscillator signal (divided by 2) sampled at the CS falling edge. Use an appropriate SCLK frequency and interval between SPI frames to capture bit changes from frame to frame as a method of verifying the continued proper operation of the clock. Similar status reports of the logical value of a subdivided internal oscillator signal (divided by 1024) are available in UBM as the OSC_DIV_1024 bit. For details on UBM frames and timing, see . The AFEx82H1 features two methods to continuously detect the functional status of the internal precision oscillator.AFEx82H1The first method requires a connection from the AFEx82H1 to the system controller. To use the first method, program the AFEx82H1 to output a subdivided internal oscillator clock signal on the CLK_OUT pin. Write to the CONFIG.CLKO register field (see ) to enable the output with the chosen divider or to disable the output. The output digital signal is compliant to the . The CLK_OUT pin is also a shared GPIO pin. For details on connecting CLK_OUT and CLK_OUT interoperability as a GPIO pin , see .AFEx82H1AFEx82H1 The CLK_OUT pin is also a shared GPIO pin. and CLK_OUT interoperability as a GPIO pin The second method does not require a connection from the AFEx82H1 and is a polled-communication-based method to determine the functionality of the internal oscillator using SPI communication. See and for SPI communication details and SDO status bits details, respectively. The OSC_DIV_2 bit reports the logical value of a subdivided internal oscillator signal (divided by 2) sampled at the CS falling edge. Use an appropriate SCLK frequency and interval between SPI frames to capture bit changes from frame to frame as a method of verifying the continued proper operation of the clock. Similar status reports of the logical value of a subdivided internal oscillator signal (divided by 1024) are available in UBM as the OSC_DIV_1024 bit. For details on UBM frames and timing, see .AFEx82H1CS One-Time Programmable (OTP) Memory One-time programmable (OTP) memory in the device is used to store the device trim settings and is not accessible to users. The OTP memory data are loaded to the memory (OTP shadow load) at power up. The OTP memory CRC is performed to verify the correct data are loaded. The TRIGGER.SHADOWLOAD bit is available to initiate a reload of the OTP memory data if a CRC error is detected. The SPECIAL_CFG.OTP_LOAD_SW_RST bit controls whether the OTP memory data are reloaded with a software reset. One-Time Programmable (OTP) Memory One-time programmable (OTP) memory in the device is used to store the device trim settings and is not accessible to users. The OTP memory data are loaded to the memory (OTP shadow load) at power up. The OTP memory CRC is performed to verify the correct data are loaded. The TRIGGER.SHADOWLOAD bit is available to initiate a reload of the OTP memory data if a CRC error is detected. The SPECIAL_CFG.OTP_LOAD_SW_RST bit controls whether the OTP memory data are reloaded with a software reset. One-time programmable (OTP) memory in the device is used to store the device trim settings and is not accessible to users. The OTP memory data are loaded to the memory (OTP shadow load) at power up. The OTP memory CRC is performed to verify the correct data are loaded. The TRIGGER.SHADOWLOAD bit is available to initiate a reload of the OTP memory data if a CRC error is detected. The SPECIAL_CFG.OTP_LOAD_SW_RST bit controls whether the OTP memory data are reloaded with a software reset. One-time programmable (OTP) memory in the device is used to store the device trim settings and is not accessible to users. The OTP memory data are loaded to the memory (OTP shadow load) at power up. The OTP memory CRC is performed to verify the correct data are loaded. The TRIGGER.SHADOWLOAD bit is available to initiate a reload of the OTP memory data if a CRC error is detected. The SPECIAL_CFG.OTP_LOAD_SW_RST bit controls whether the OTP memory data are reloaded with a software reset. GPIO AFEx82H1 feature multiple GPIO pins, each independently configurable in either input only or output only or input-ouput mode through GPIO_CFG and GPIO registers. Select either push-pull or pseudo open drain sub modes supported when the GPIO is in output mode. No dedicated GPIO pins are present since the same pins are also configurable for communication interfaces. Based on the selection of the interface protocol and how many pins are used for communication purposes, the AFEx82H1 have up to four available GPIOs. Refer to for detailed diagrams of available GPIOs in each communication mode. If a GPIO pin is unused or undriven, the pin must be tied resistively to either IOVDD or GND according to the connection diagrams in . Unconnected floating input pins lead to unknown states for the communication interfaces and varying supply currents for the AFEx82H1. When functioning as an output, each GPIO pin is capable of sourcing and sinking current and when functioning as an input the register address 0x1C reflects the digital state of the GPIO pins (for details of source and sink capabilities and input thresholds, see ). The minimum pulse width for transition detection is tPULSE_GPIO. When a state transition occurs on a GPIO input, the new state must be held for a minimum of tPULSE_GPIO for detection by the AFEx82H1. GPIO AFEx82H1 feature multiple GPIO pins, each independently configurable in either input only or output only or input-ouput mode through GPIO_CFG and GPIO registers. Select either push-pull or pseudo open drain sub modes supported when the GPIO is in output mode. No dedicated GPIO pins are present since the same pins are also configurable for communication interfaces. Based on the selection of the interface protocol and how many pins are used for communication purposes, the AFEx82H1 have up to four available GPIOs. Refer to for detailed diagrams of available GPIOs in each communication mode. If a GPIO pin is unused or undriven, the pin must be tied resistively to either IOVDD or GND according to the connection diagrams in . Unconnected floating input pins lead to unknown states for the communication interfaces and varying supply currents for the AFEx82H1. When functioning as an output, each GPIO pin is capable of sourcing and sinking current and when functioning as an input the register address 0x1C reflects the digital state of the GPIO pins (for details of source and sink capabilities and input thresholds, see ). The minimum pulse width for transition detection is tPULSE_GPIO. When a state transition occurs on a GPIO input, the new state must be held for a minimum of tPULSE_GPIO for detection by the AFEx82H1. AFEx82H1 feature multiple GPIO pins, each independently configurable in either input only or output only or input-ouput mode through GPIO_CFG and GPIO registers. Select either push-pull or pseudo open drain sub modes supported when the GPIO is in output mode. No dedicated GPIO pins are present since the same pins are also configurable for communication interfaces. Based on the selection of the interface protocol and how many pins are used for communication purposes, the AFEx82H1 have up to four available GPIOs. Refer to for detailed diagrams of available GPIOs in each communication mode. If a GPIO pin is unused or undriven, the pin must be tied resistively to either IOVDD or GND according to the connection diagrams in . Unconnected floating input pins lead to unknown states for the communication interfaces and varying supply currents for the AFEx82H1. When functioning as an output, each GPIO pin is capable of sourcing and sinking current and when functioning as an input the register address 0x1C reflects the digital state of the GPIO pins (for details of source and sink capabilities and input thresholds, see ). The minimum pulse width for transition detection is tPULSE_GPIO. When a state transition occurs on a GPIO input, the new state must be held for a minimum of tPULSE_GPIO for detection by the AFEx82H1. AFEx82H1 feature multiple GPIO pins, each independently configurable in either input only or output only or input-ouput mode through GPIO_CFG and GPIO registers. Select either push-pull or pseudo open drain sub modes supported when the GPIO is in output mode. No dedicated GPIO pins are present since the same pins are also configurable for communication interfaces. Based on the selection of the interface protocol and how many pins are used for communication purposes, the AFEx82H1 have up to four available GPIOs. Refer to for detailed diagrams of available GPIOs in each communication mode. If a GPIO pin is unused or undriven, the pin must be tied resistively to either IOVDD or GND according to the connection diagrams in . Unconnected floating input pins lead to unknown states for the communication interfaces and varying supply currents for the AFEx82H1. When functioning as an output, each GPIO pin is capable of sourcing and sinking current and when functioning as an input the register address 0x1C reflects the digital state of the GPIO pins (for details of source and sink capabilities and input thresholds, see ). The minimum pulse width for transition detection is tPULSE_GPIO. When a state transition occurs on a GPIO input, the new state must be held for a minimum of tPULSE_GPIO for detection by the AFEx82H1. AFEx82H1AFEx82H1AFEx82H1PULSE_GPIOPULSE_GPIOAFEx82H1 Timer The AFEx82H1 have an integrated timer for generating accurate time delays, pulse width modulation or oscillation. The devices have the ability to have timing parameters from the microseconds range to hours. The timer is brought out on the CLK_OUT pin by setting CONFIG.CLKO = Fh. The timer is controlled with three registers; TIMER_CFG_0, TIMER_CFG_1, and TIMER_CFG_2. In the first of the three registers, TIMER_CFG_0.ENABLE turns the timer function on and off. If the timer is off, then the output defaults to 0. TIMER_CFG_0.INVERT inverts the output of the timer. If the INVERT bit is set, the output defaults to 1. TIMER_CFG_0.CLK_SEL selects the clock frequency according to #GUID-D4148F6E-8502-48B6-8064-9DF2FCCD8009/TABLE_ADN_CZD_PVB. If 2'b00 is selected, and no clock is applied, then the timer pauses if the timer has previously been enabled and counting. Timer Select Range CLK_SEL Clock Frequency Resolution Range 00 No clock - - 01 1.2288 MHz 814 ns 53.3 ms 10 1.200 kHz 833 μs 54.6 s 11 1.171 Hz 853 ms 55,923 s The second timer register, TIMER_CFG_1.PERIOD sets the period of the timer. The period of the timer is PERIOD + 1 cycles of the clock period. The last timer register, TIMER_CFG_2.SET_TIME determines when the timer output goes to 1 (INVERT = 0). This effectively defines the duty cycle of the timer. The duty cycle can be calculated as (PERIOD – SET_TIME) × clock period. Timer The AFEx82H1 have an integrated timer for generating accurate time delays, pulse width modulation or oscillation. The devices have the ability to have timing parameters from the microseconds range to hours. The timer is brought out on the CLK_OUT pin by setting CONFIG.CLKO = Fh. The timer is controlled with three registers; TIMER_CFG_0, TIMER_CFG_1, and TIMER_CFG_2. In the first of the three registers, TIMER_CFG_0.ENABLE turns the timer function on and off. If the timer is off, then the output defaults to 0. TIMER_CFG_0.INVERT inverts the output of the timer. If the INVERT bit is set, the output defaults to 1. TIMER_CFG_0.CLK_SEL selects the clock frequency according to #GUID-D4148F6E-8502-48B6-8064-9DF2FCCD8009/TABLE_ADN_CZD_PVB. If 2'b00 is selected, and no clock is applied, then the timer pauses if the timer has previously been enabled and counting. Timer Select Range CLK_SEL Clock Frequency Resolution Range 00 No clock - - 01 1.2288 MHz 814 ns 53.3 ms 10 1.200 kHz 833 μs 54.6 s 11 1.171 Hz 853 ms 55,923 s The second timer register, TIMER_CFG_1.PERIOD sets the period of the timer. The period of the timer is PERIOD + 1 cycles of the clock period. The last timer register, TIMER_CFG_2.SET_TIME determines when the timer output goes to 1 (INVERT = 0). This effectively defines the duty cycle of the timer. The duty cycle can be calculated as (PERIOD – SET_TIME) × clock period. The AFEx82H1 have an integrated timer for generating accurate time delays, pulse width modulation or oscillation. The devices have the ability to have timing parameters from the microseconds range to hours. The timer is brought out on the CLK_OUT pin by setting CONFIG.CLKO = Fh. The timer is controlled with three registers; TIMER_CFG_0, TIMER_CFG_1, and TIMER_CFG_2. In the first of the three registers, TIMER_CFG_0.ENABLE turns the timer function on and off. If the timer is off, then the output defaults to 0. TIMER_CFG_0.INVERT inverts the output of the timer. If the INVERT bit is set, the output defaults to 1. TIMER_CFG_0.CLK_SEL selects the clock frequency according to #GUID-D4148F6E-8502-48B6-8064-9DF2FCCD8009/TABLE_ADN_CZD_PVB. If 2'b00 is selected, and no clock is applied, then the timer pauses if the timer has previously been enabled and counting. Timer Select Range CLK_SEL Clock Frequency Resolution Range 00 No clock - - 01 1.2288 MHz 814 ns 53.3 ms 10 1.200 kHz 833 μs 54.6 s 11 1.171 Hz 853 ms 55,923 s The second timer register, TIMER_CFG_1.PERIOD sets the period of the timer. The period of the timer is PERIOD + 1 cycles of the clock period. The last timer register, TIMER_CFG_2.SET_TIME determines when the timer output goes to 1 (INVERT = 0). This effectively defines the duty cycle of the timer. The duty cycle can be calculated as (PERIOD – SET_TIME) × clock period. The AFEx82H1 have an integrated timer for generating accurate time delays, pulse width modulation or oscillation. The devices have the ability to have timing parameters from the microseconds range to hours. The timer is brought out on the CLK_OUT pin by setting CONFIG.CLKO = Fh. The timer is controlled with three registers; TIMER_CFG_0, TIMER_CFG_1, and TIMER_CFG_2.AFEx82H1In the first of the three registers, TIMER_CFG_0.ENABLE turns the timer function on and off. If the timer is off, then the output defaults to 0. TIMER_CFG_0.INVERT inverts the output of the timer. If the INVERT bit is set, the output defaults to 1. TIMER_CFG_0.CLK_SEL selects the clock frequency according to #GUID-D4148F6E-8502-48B6-8064-9DF2FCCD8009/TABLE_ADN_CZD_PVB. If 2'b00 is selected, and no clock is applied, then the timer pauses if the timer has previously been enabled and counting.#GUID-D4148F6E-8502-48B6-8064-9DF2FCCD8009/TABLE_ADN_CZD_PVB Timer Select Range CLK_SEL Clock Frequency Resolution Range 00 No clock - - 01 1.2288 MHz 814 ns 53.3 ms 10 1.200 kHz 833 μs 54.6 s 11 1.171 Hz 853 ms 55,923 s Timer Select Range CLK_SEL Clock Frequency Resolution Range 00 No clock - - 01 1.2288 MHz 814 ns 53.3 ms 10 1.200 kHz 833 μs 54.6 s 11 1.171 Hz 853 ms 55,923 s CLK_SEL Clock Frequency Resolution Range CLK_SEL Clock Frequency Resolution Range CLK_SELClock FrequencyResolutionRange 00 No clock - - 01 1.2288 MHz 814 ns 53.3 ms 10 1.200 kHz 833 μs 54.6 s 11 1.171 Hz 853 ms 55,923 s 00 No clock - - 00No clock-- 01 1.2288 MHz 814 ns 53.3 ms 011.2288 MHz814 ns53.3 ms 10 1.200 kHz 833 μs 54.6 s 101.200 kHz833 μs54.6 s 11 1.171 Hz 853 ms 55,923 s 111.171 Hz853 ms55,923 sThe second timer register, TIMER_CFG_1.PERIOD sets the period of the timer. The period of the timer is PERIOD + 1 cycles of the clock period. The last timer register, TIMER_CFG_2.SET_TIME determines when the timer output goes to 1 (INVERT = 0). This effectively defines the duty cycle of the timer. The duty cycle can be calculated as (PERIOD – SET_TIME) × clock period. Unique Chip Identifier (ID) AFEx82H1 include two read only registers: CHIP_ID_MSB (1Ah) and CHIP_ID_LSB (19h) where unique chip ID is stored. The 16-bit CHIP_ID_MSB register stores the encoded lot identification number while the CHIP_ID_LSB register stores the unique part number within each lot. Unique Chip Identifier (ID) AFEx82H1 include two read only registers: CHIP_ID_MSB (1Ah) and CHIP_ID_LSB (19h) where unique chip ID is stored. The 16-bit CHIP_ID_MSB register stores the encoded lot identification number while the CHIP_ID_LSB register stores the unique part number within each lot. AFEx82H1 include two read only registers: CHIP_ID_MSB (1Ah) and CHIP_ID_LSB (19h) where unique chip ID is stored. The 16-bit CHIP_ID_MSB register stores the encoded lot identification number while the CHIP_ID_LSB register stores the unique part number within each lot. AFEx82H1 include two read only registers: CHIP_ID_MSB (1Ah) and CHIP_ID_LSB (19h) where unique chip ID is stored. The 16-bit CHIP_ID_MSB register stores the encoded lot identification number while the CHIP_ID_LSB register stores the unique part number within each lot.AFEx82H1 Scratch Pad Register AFEx82H1 feature a 16-bit Scratch Pad register to enable interface debug and verification without affecting the part functionality. This register is located at the address 18h. The readback value of the Scratch Pad register is the inverted code of the value stored in the register (for example, writing 0xAAAA results in 0x5555 while reading back ). Scratch Pad Register AFEx82H1 feature a 16-bit Scratch Pad register to enable interface debug and verification without affecting the part functionality. This register is located at the address 18h. The readback value of the Scratch Pad register is the inverted code of the value stored in the register (for example, writing 0xAAAA results in 0x5555 while reading back ). AFEx82H1 feature a 16-bit Scratch Pad register to enable interface debug and verification without affecting the part functionality. This register is located at the address 18h. The readback value of the Scratch Pad register is the inverted code of the value stored in the register (for example, writing 0xAAAA results in 0x5555 while reading back ). AFEx82H1 feature a 16-bit Scratch Pad register to enable interface debug and verification without affecting the part functionality. This register is located at the address 18h. The readback value of the Scratch Pad register is the inverted code of the value stored in the register (for example, writing 0xAAAA results in 0x5555 while reading back ).AFEx82H1 Device Functional Modes DAC Power-Down Mode Power-down mode facilitates rapid turn-off of the voltage at the DAC output. The DAC can be set to enter and exit power-down mode through hardware, software, or automatically in response to an alarm event. The DAC output is specified for glitch-free performance when going into and out of power-down mode. Power-down mode is also be enabled by setting DAC_CFG.PD to 1. In power-down mode, the DAC output amplifier powers down and the DAC output pin is put into the Hi-Z configuration. The DAC output remains in power-down mode until the DAC output is re-enabled. Alarm control of the power-down mode is enabled by setting the alarm events as DAC power-down sources. The alarm events that trigger the DAC output power-down state must be specified in the ALARM_ACT register. After the alarm bit is cleared, the DAC returns to normal operation, as long as no other power-down controlling alarm event has been triggered. The DAC register does not change when the DAC enters power-down mode, which enables the device to return to the original operating point after return from the power-down mode. Additionally, the DAC register can be updated while the DAC is in power-down mode, thus allowing the DAC to output a new value upon return to normal operation. Register Built-In Self-Test (RBIST) The AFEx82H1 feature a register built-in self-test (RBIST) that runs on all the registers listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB through a CRC calculation in the order the registers are listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB. If a register is reserved, the reset value is used in the calculation of the RBIST. If the final CRC value is zero, then no error is present in the configuration of the registers. If a non-zero value is present at the end of the calculation, then there is a configuration error. The polynomial used has a Hamming distance (HD) of 4 for data packets up to 2048 bits. With HD = 4, the CRC detects any combination of 4-bit errors within the stored data. Independently calculate the expected CRC polynomial and store the output in the RBIST_CRC register at 3Fh. The final value of the CRC is read in the CRC_RD register at address 3Eh. This value is updated while either an RBIST or shadow load is running. Both the RBIST and OTP memory use the same CRC calculation engine and polynomial. The value in the CRC_RD register remains constant until another RBIST or SHADOWLOAD in TRIGGER register (0Ah) is triggered. Set TRIGGER.RBIST to 1 to initiate an RBIST. The TRIGGER.RBIST bit stays high as long as the RBIST is running and clears when the self-test is complete. While the RBIST is running, the registers cannot be written to or read. Send NOP commands and monitor the RBIST SDO status bit to determine if the RBIST has completed.In UBM, the RBIST does not interfere with register communication. UBM communication is slow enough that the RBIST completes before any following read or write command. The GEN_STATUS.BIST_DONE and GEN_STATUS.BIST_FAIL bits have the same functionality for both MBIST and RBIST. GEN_STATUS.BIST_MODE is used to select between two tests (1 = RBIST and 0 = MBIST). This bit is sticky until the GEN_STATUS register is read. The FIFO_CFG.FIFO_H2U_FLUSH and FIFO_CFG.FIFO_U2H_FLUSH bits are write-self-clear (WSC) and considered 0 by the CRC module. The 16-bit CRC used to generate the RBIST is compliant to the openSAFETY (0x755B) standard with the following polynomial: x16 + x14 + x13 + x12 + x10 + x8 + x6 + x4 + x3 + x1 + 1. The list of registers covered by the RBIST is listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB. Not all registers feature the RBIST. List of Registers Covered by RBIST ADDR (HEX) REGISTER RESET (HEX) 01h DAC_DATA 0000h 02h CONFIG 0036h 03h DAC_CFG 0B00h 04h DAC_GAIN 8000h 05h DAC_OFFSET 0000h 06h DAC_CLR_CODE 0000h 08h ADC_CFG 8810h 09h ADC_INDEX_CFG 0080h 0Bh SPECIAL_CFG 0000h 0Dh RESERVED 0100h 0Eh MODEM_CFG 0040h 0Fh FIFO_CFG 00F0h 10h ALARM_ACT 8020h 11h WDT 0018h 12h AIN0_THRESHOLD FF00h 13h AIN1_THRESHOLD FF00h 14h TEMP_THRESHOLD FF00h 1Bh GPIO_CFG 00FFh 1Dh ALARM_STATUS_MASK EFDFh 1Eh GEN_STATUS_MASK FFFFh 1Fh MODEM_STATUS_MASK FFFFh 3Fh RBIST_CRC 0000h Reset There are three reset mechanisms in the device: a power-on reset (POR), a RESET pin, and the SW_RST command that can be sent through the either the SPI or by UBM. When power is first applied to the device, a POR circuit holds the device in reset until all supplies reach the specified operating voltages. The power-on reset returns the device to a known operating state in case a brownout event occurs (when the supplies have dipped below the minimum operating voltages). The POR starts all digital circuits in reset as the supply settles, and releases them to make sure that the device starts in the default condition and loads the OTP memory. After the OTP memory has been loaded, the ALARM pin is released. At this time, communication with the device is safe. This tPOR time is less than 100 µs. The devices also have a RESET pin that is used as a hardware reset to the device. Send the RESET pin low for a minimum of 100 ns (tRESET) to reset the device. A delay time of 10 μs (tRESETWAIT) is required before sending the first serial interface command as the device latches and releases the reset. The release of the internal reset state is synchronized to the internal clock. The RESET pin resets the SPI and the UART interfaces, the HART FIFO buffer, the watchdog timer, the internal oscillator, and the device registers. RESET does not reload the OTP memory. The command to RESET.SW_RST = 0xAD resets the device as a software reset. The command is decoded at the rising edge of CS with an SPI command or during the stop bit of the last character of a UBM frame. Set UBM.REG_MODE again to put the device back into UBM when resetting the device in UBM. After sending the RESET command, no delay time is required before sending the first serial interface command as the device latches and releases the reset. The reset is synchronized to the falling edge of the internal clock and is released well before the next rising edge. The ALARM pin pulses low for the width of the internal reset. This pulse duration is less than 20 ns. This command resets the SPI and the UART interface, the HART FIFO, and the watchdog timer, but does not reset the internal oscillator. The software reset also reloads internal factory trim registers if properly configured in the SPECIAL_CFG register. The SPECIAL_CFG register is only reset with a POR. The POR and hardware reset place the internal oscillator into a reset condition, which holds the clock low. When these two signals are released, there is a delay of a few microseconds before the first rising edge of the clock. The hardware reset, RESET, pulse width must be at least 100 ns to allow the oscillator to properly reset. The SW_RST command is a short pulse. This pulse is not long enough to adequately reset the oscillator. The SW_RST is asserted with a falling edge of the clock. As a result of the long oscillator period, the design architecture provides that all devices are out of reset by the next rising edge. shows the reset tree. Reset Conditions Device Functional Modes DAC Power-Down Mode Power-down mode facilitates rapid turn-off of the voltage at the DAC output. The DAC can be set to enter and exit power-down mode through hardware, software, or automatically in response to an alarm event. The DAC output is specified for glitch-free performance when going into and out of power-down mode. Power-down mode is also be enabled by setting DAC_CFG.PD to 1. In power-down mode, the DAC output amplifier powers down and the DAC output pin is put into the Hi-Z configuration. The DAC output remains in power-down mode until the DAC output is re-enabled. Alarm control of the power-down mode is enabled by setting the alarm events as DAC power-down sources. The alarm events that trigger the DAC output power-down state must be specified in the ALARM_ACT register. After the alarm bit is cleared, the DAC returns to normal operation, as long as no other power-down controlling alarm event has been triggered. The DAC register does not change when the DAC enters power-down mode, which enables the device to return to the original operating point after return from the power-down mode. Additionally, the DAC register can be updated while the DAC is in power-down mode, thus allowing the DAC to output a new value upon return to normal operation. DAC Power-Down Mode Power-down mode facilitates rapid turn-off of the voltage at the DAC output. The DAC can be set to enter and exit power-down mode through hardware, software, or automatically in response to an alarm event. The DAC output is specified for glitch-free performance when going into and out of power-down mode. Power-down mode is also be enabled by setting DAC_CFG.PD to 1. In power-down mode, the DAC output amplifier powers down and the DAC output pin is put into the Hi-Z configuration. The DAC output remains in power-down mode until the DAC output is re-enabled. Alarm control of the power-down mode is enabled by setting the alarm events as DAC power-down sources. The alarm events that trigger the DAC output power-down state must be specified in the ALARM_ACT register. After the alarm bit is cleared, the DAC returns to normal operation, as long as no other power-down controlling alarm event has been triggered. The DAC register does not change when the DAC enters power-down mode, which enables the device to return to the original operating point after return from the power-down mode. Additionally, the DAC register can be updated while the DAC is in power-down mode, thus allowing the DAC to output a new value upon return to normal operation. Power-down mode facilitates rapid turn-off of the voltage at the DAC output. The DAC can be set to enter and exit power-down mode through hardware, software, or automatically in response to an alarm event. The DAC output is specified for glitch-free performance when going into and out of power-down mode. Power-down mode is also be enabled by setting DAC_CFG.PD to 1. In power-down mode, the DAC output amplifier powers down and the DAC output pin is put into the Hi-Z configuration. The DAC output remains in power-down mode until the DAC output is re-enabled. Alarm control of the power-down mode is enabled by setting the alarm events as DAC power-down sources. The alarm events that trigger the DAC output power-down state must be specified in the ALARM_ACT register. After the alarm bit is cleared, the DAC returns to normal operation, as long as no other power-down controlling alarm event has been triggered. The DAC register does not change when the DAC enters power-down mode, which enables the device to return to the original operating point after return from the power-down mode. Additionally, the DAC register can be updated while the DAC is in power-down mode, thus allowing the DAC to output a new value upon return to normal operation. Power-down mode facilitates rapid turn-off of the voltage at the DAC output. The DAC can be set to enter and exit power-down mode through hardware, software, or automatically in response to an alarm event. The DAC output is specified for glitch-free performance when going into and out of power-down mode.Power-down mode is also be enabled by setting DAC_CFG.PD to 1. In power-down mode, the DAC output amplifier powers down and the DAC output pin is put into the Hi-Z configuration. The DAC output remains in power-down mode until the DAC output is re-enabled.Alarm control of the power-down mode is enabled by setting the alarm events as DAC power-down sources. The alarm events that trigger the DAC output power-down state must be specified in the ALARM_ACT register. After the alarm bit is cleared, the DAC returns to normal operation, as long as no other power-down controlling alarm event has been triggered.The DAC register does not change when the DAC enters power-down mode, which enables the device to return to the original operating point after return from the power-down mode. Additionally, the DAC register can be updated while the DAC is in power-down mode, thus allowing the DAC to output a new value upon return to normal operation. Register Built-In Self-Test (RBIST) The AFEx82H1 feature a register built-in self-test (RBIST) that runs on all the registers listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB through a CRC calculation in the order the registers are listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB. If a register is reserved, the reset value is used in the calculation of the RBIST. If the final CRC value is zero, then no error is present in the configuration of the registers. If a non-zero value is present at the end of the calculation, then there is a configuration error. The polynomial used has a Hamming distance (HD) of 4 for data packets up to 2048 bits. With HD = 4, the CRC detects any combination of 4-bit errors within the stored data. Independently calculate the expected CRC polynomial and store the output in the RBIST_CRC register at 3Fh. The final value of the CRC is read in the CRC_RD register at address 3Eh. This value is updated while either an RBIST or shadow load is running. Both the RBIST and OTP memory use the same CRC calculation engine and polynomial. The value in the CRC_RD register remains constant until another RBIST or SHADOWLOAD in TRIGGER register (0Ah) is triggered. Set TRIGGER.RBIST to 1 to initiate an RBIST. The TRIGGER.RBIST bit stays high as long as the RBIST is running and clears when the self-test is complete. While the RBIST is running, the registers cannot be written to or read. Send NOP commands and monitor the RBIST SDO status bit to determine if the RBIST has completed.In UBM, the RBIST does not interfere with register communication. UBM communication is slow enough that the RBIST completes before any following read or write command. The GEN_STATUS.BIST_DONE and GEN_STATUS.BIST_FAIL bits have the same functionality for both MBIST and RBIST. GEN_STATUS.BIST_MODE is used to select between two tests (1 = RBIST and 0 = MBIST). This bit is sticky until the GEN_STATUS register is read. The FIFO_CFG.FIFO_H2U_FLUSH and FIFO_CFG.FIFO_U2H_FLUSH bits are write-self-clear (WSC) and considered 0 by the CRC module. The 16-bit CRC used to generate the RBIST is compliant to the openSAFETY (0x755B) standard with the following polynomial: x16 + x14 + x13 + x12 + x10 + x8 + x6 + x4 + x3 + x1 + 1. The list of registers covered by the RBIST is listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB. Not all registers feature the RBIST. List of Registers Covered by RBIST ADDR (HEX) REGISTER RESET (HEX) 01h DAC_DATA 0000h 02h CONFIG 0036h 03h DAC_CFG 0B00h 04h DAC_GAIN 8000h 05h DAC_OFFSET 0000h 06h DAC_CLR_CODE 0000h 08h ADC_CFG 8810h 09h ADC_INDEX_CFG 0080h 0Bh SPECIAL_CFG 0000h 0Dh RESERVED 0100h 0Eh MODEM_CFG 0040h 0Fh FIFO_CFG 00F0h 10h ALARM_ACT 8020h 11h WDT 0018h 12h AIN0_THRESHOLD FF00h 13h AIN1_THRESHOLD FF00h 14h TEMP_THRESHOLD FF00h 1Bh GPIO_CFG 00FFh 1Dh ALARM_STATUS_MASK EFDFh 1Eh GEN_STATUS_MASK FFFFh 1Fh MODEM_STATUS_MASK FFFFh 3Fh RBIST_CRC 0000h Register Built-In Self-Test (RBIST) The AFEx82H1 feature a register built-in self-test (RBIST) that runs on all the registers listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB through a CRC calculation in the order the registers are listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB. If a register is reserved, the reset value is used in the calculation of the RBIST. If the final CRC value is zero, then no error is present in the configuration of the registers. If a non-zero value is present at the end of the calculation, then there is a configuration error. The polynomial used has a Hamming distance (HD) of 4 for data packets up to 2048 bits. With HD = 4, the CRC detects any combination of 4-bit errors within the stored data. Independently calculate the expected CRC polynomial and store the output in the RBIST_CRC register at 3Fh. The final value of the CRC is read in the CRC_RD register at address 3Eh. This value is updated while either an RBIST or shadow load is running. Both the RBIST and OTP memory use the same CRC calculation engine and polynomial. The value in the CRC_RD register remains constant until another RBIST or SHADOWLOAD in TRIGGER register (0Ah) is triggered. Set TRIGGER.RBIST to 1 to initiate an RBIST. The TRIGGER.RBIST bit stays high as long as the RBIST is running and clears when the self-test is complete. While the RBIST is running, the registers cannot be written to or read. Send NOP commands and monitor the RBIST SDO status bit to determine if the RBIST has completed.In UBM, the RBIST does not interfere with register communication. UBM communication is slow enough that the RBIST completes before any following read or write command. The GEN_STATUS.BIST_DONE and GEN_STATUS.BIST_FAIL bits have the same functionality for both MBIST and RBIST. GEN_STATUS.BIST_MODE is used to select between two tests (1 = RBIST and 0 = MBIST). This bit is sticky until the GEN_STATUS register is read. The FIFO_CFG.FIFO_H2U_FLUSH and FIFO_CFG.FIFO_U2H_FLUSH bits are write-self-clear (WSC) and considered 0 by the CRC module. The 16-bit CRC used to generate the RBIST is compliant to the openSAFETY (0x755B) standard with the following polynomial: x16 + x14 + x13 + x12 + x10 + x8 + x6 + x4 + x3 + x1 + 1. The list of registers covered by the RBIST is listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB. Not all registers feature the RBIST. List of Registers Covered by RBIST ADDR (HEX) REGISTER RESET (HEX) 01h DAC_DATA 0000h 02h CONFIG 0036h 03h DAC_CFG 0B00h 04h DAC_GAIN 8000h 05h DAC_OFFSET 0000h 06h DAC_CLR_CODE 0000h 08h ADC_CFG 8810h 09h ADC_INDEX_CFG 0080h 0Bh SPECIAL_CFG 0000h 0Dh RESERVED 0100h 0Eh MODEM_CFG 0040h 0Fh FIFO_CFG 00F0h 10h ALARM_ACT 8020h 11h WDT 0018h 12h AIN0_THRESHOLD FF00h 13h AIN1_THRESHOLD FF00h 14h TEMP_THRESHOLD FF00h 1Bh GPIO_CFG 00FFh 1Dh ALARM_STATUS_MASK EFDFh 1Eh GEN_STATUS_MASK FFFFh 1Fh MODEM_STATUS_MASK FFFFh 3Fh RBIST_CRC 0000h The AFEx82H1 feature a register built-in self-test (RBIST) that runs on all the registers listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB through a CRC calculation in the order the registers are listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB. If a register is reserved, the reset value is used in the calculation of the RBIST. If the final CRC value is zero, then no error is present in the configuration of the registers. If a non-zero value is present at the end of the calculation, then there is a configuration error. The polynomial used has a Hamming distance (HD) of 4 for data packets up to 2048 bits. With HD = 4, the CRC detects any combination of 4-bit errors within the stored data. Independently calculate the expected CRC polynomial and store the output in the RBIST_CRC register at 3Fh. The final value of the CRC is read in the CRC_RD register at address 3Eh. This value is updated while either an RBIST or shadow load is running. Both the RBIST and OTP memory use the same CRC calculation engine and polynomial. The value in the CRC_RD register remains constant until another RBIST or SHADOWLOAD in TRIGGER register (0Ah) is triggered. Set TRIGGER.RBIST to 1 to initiate an RBIST. The TRIGGER.RBIST bit stays high as long as the RBIST is running and clears when the self-test is complete. While the RBIST is running, the registers cannot be written to or read. Send NOP commands and monitor the RBIST SDO status bit to determine if the RBIST has completed.In UBM, the RBIST does not interfere with register communication. UBM communication is slow enough that the RBIST completes before any following read or write command. The GEN_STATUS.BIST_DONE and GEN_STATUS.BIST_FAIL bits have the same functionality for both MBIST and RBIST. GEN_STATUS.BIST_MODE is used to select between two tests (1 = RBIST and 0 = MBIST). This bit is sticky until the GEN_STATUS register is read. The FIFO_CFG.FIFO_H2U_FLUSH and FIFO_CFG.FIFO_U2H_FLUSH bits are write-self-clear (WSC) and considered 0 by the CRC module. The 16-bit CRC used to generate the RBIST is compliant to the openSAFETY (0x755B) standard with the following polynomial: x16 + x14 + x13 + x12 + x10 + x8 + x6 + x4 + x3 + x1 + 1. The list of registers covered by the RBIST is listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB. Not all registers feature the RBIST. List of Registers Covered by RBIST ADDR (HEX) REGISTER RESET (HEX) 01h DAC_DATA 0000h 02h CONFIG 0036h 03h DAC_CFG 0B00h 04h DAC_GAIN 8000h 05h DAC_OFFSET 0000h 06h DAC_CLR_CODE 0000h 08h ADC_CFG 8810h 09h ADC_INDEX_CFG 0080h 0Bh SPECIAL_CFG 0000h 0Dh RESERVED 0100h 0Eh MODEM_CFG 0040h 0Fh FIFO_CFG 00F0h 10h ALARM_ACT 8020h 11h WDT 0018h 12h AIN0_THRESHOLD FF00h 13h AIN1_THRESHOLD FF00h 14h TEMP_THRESHOLD FF00h 1Bh GPIO_CFG 00FFh 1Dh ALARM_STATUS_MASK EFDFh 1Eh GEN_STATUS_MASK FFFFh 1Fh MODEM_STATUS_MASK FFFFh 3Fh RBIST_CRC 0000h The AFEx82H1 feature a register built-in self-test (RBIST) that runs on all the registers listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB through a CRC calculation in the order the registers are listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB. If a register is reserved, the reset value is used in the calculation of the RBIST. If the final CRC value is zero, then no error is present in the configuration of the registers. If a non-zero value is present at the end of the calculation, then there is a configuration error. The polynomial used has a Hamming distance (HD) of 4 for data packets up to 2048 bits. With HD = 4, the CRC detects any combination of 4-bit errors within the stored data. Independently calculate the expected CRC polynomial and store the output in the RBIST_CRC register at 3Fh.AFEx82H1#GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB#GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPBThe final value of the CRC is read in the CRC_RD register at address 3Eh. This value is updated while either an RBIST or shadow load is running. Both the RBIST and OTP memory use the same CRC calculation engine and polynomial. The value in the CRC_RD register remains constant until another RBIST or SHADOWLOAD in TRIGGER register (0Ah) is triggered.Set TRIGGER.RBIST to 1 to initiate an RBIST. The TRIGGER.RBIST bit stays high as long as the RBIST is running and clears when the self-test is complete. While the RBIST is running, the registers cannot be written to or read. Send NOP commands and monitor the RBIST SDO status bit to determine if the RBIST has completed.The GEN_STATUS.BIST_DONE and GEN_STATUS.BIST_FAIL bits have the same functionality for both MBIST and RBIST. GEN_STATUS.BIST_MODE is used to select between two tests (1 = RBIST and 0 = MBIST). This bit is sticky until the GEN_STATUS register is read.The FIFO_CFG.FIFO_H2U_FLUSH and FIFO_CFG.FIFO_U2H_FLUSH bits are write-self-clear (WSC) and considered 0 by the CRC module.The 16-bit CRC used to generate the RBIST is compliant to the openSAFETY (0x755B) standard with the following polynomial: x16 + x14 + x13 + x12 + x10 + x8 + x6 + x4 + x3 + x1 + 1.x16 + x14 + x13 + x12 + x10 + x8 + x6 + x4 + x3 + x1 + 1161413121086431The list of registers covered by the RBIST is listed in #GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB. Not all registers feature the RBIST.#GUID-6F0BBA45-B646-49F0-950C-BAB5E301959E/TABLE_ILZ_TX1_TPB List of Registers Covered by RBIST ADDR (HEX) REGISTER RESET (HEX) 01h DAC_DATA 0000h 02h CONFIG 0036h 03h DAC_CFG 0B00h 04h DAC_GAIN 8000h 05h DAC_OFFSET 0000h 06h DAC_CLR_CODE 0000h 08h ADC_CFG 8810h 09h ADC_INDEX_CFG 0080h 0Bh SPECIAL_CFG 0000h 0Dh RESERVED 0100h 0Eh MODEM_CFG 0040h 0Fh FIFO_CFG 00F0h 10h ALARM_ACT 8020h 11h WDT 0018h 12h AIN0_THRESHOLD FF00h 13h AIN1_THRESHOLD FF00h 14h TEMP_THRESHOLD FF00h 1Bh GPIO_CFG 00FFh 1Dh ALARM_STATUS_MASK EFDFh 1Eh GEN_STATUS_MASK FFFFh 1Fh MODEM_STATUS_MASK FFFFh 3Fh RBIST_CRC 0000h List of Registers Covered by RBIST ADDR (HEX) REGISTER RESET (HEX) 01h DAC_DATA 0000h 02h CONFIG 0036h 03h DAC_CFG 0B00h 04h DAC_GAIN 8000h 05h DAC_OFFSET 0000h 06h DAC_CLR_CODE 0000h 08h ADC_CFG 8810h 09h ADC_INDEX_CFG 0080h 0Bh SPECIAL_CFG 0000h 0Dh RESERVED 0100h 0Eh MODEM_CFG 0040h 0Fh FIFO_CFG 00F0h 10h ALARM_ACT 8020h 11h WDT 0018h 12h AIN0_THRESHOLD FF00h 13h AIN1_THRESHOLD FF00h 14h TEMP_THRESHOLD FF00h 1Bh GPIO_CFG 00FFh 1Dh ALARM_STATUS_MASK EFDFh 1Eh GEN_STATUS_MASK FFFFh 1Fh MODEM_STATUS_MASK FFFFh 3Fh RBIST_CRC 0000h ADDR (HEX) REGISTER RESET (HEX) ADDR (HEX) REGISTER RESET (HEX) ADDR (HEX)REGISTERRESET (HEX) 01h DAC_DATA 0000h 02h CONFIG 0036h 03h DAC_CFG 0B00h 04h DAC_GAIN 8000h 05h DAC_OFFSET 0000h 06h DAC_CLR_CODE 0000h 08h ADC_CFG 8810h 09h ADC_INDEX_CFG 0080h 0Bh SPECIAL_CFG 0000h 0Dh RESERVED 0100h 0Eh MODEM_CFG 0040h 0Fh FIFO_CFG 00F0h 10h ALARM_ACT 8020h 11h WDT 0018h 12h AIN0_THRESHOLD FF00h 13h AIN1_THRESHOLD FF00h 14h TEMP_THRESHOLD FF00h 1Bh GPIO_CFG 00FFh 1Dh ALARM_STATUS_MASK EFDFh 1Eh GEN_STATUS_MASK FFFFh 1Fh MODEM_STATUS_MASK FFFFh 3Fh RBIST_CRC 0000h 01h DAC_DATA 0000h 01h DAC_DATA DAC_DATA0000h 02h CONFIG 0036h 02h CONFIG CONFIG0036h 03h DAC_CFG 0B00h 03h DAC_CFG DAC_CFG0B00h 04h DAC_GAIN 8000h 04h DAC_GAIN DAC_GAIN8000h 05h DAC_OFFSET 0000h 05h DAC_OFFSET DAC_OFFSET0000h 06h DAC_CLR_CODE 0000h 06h DAC_CLR_CODE DAC_CLR_CODE0000h 08h ADC_CFG 8810h 08h ADC_CFG ADC_CFG8810h 09h ADC_INDEX_CFG 0080h 09h ADC_INDEX_CFG ADC_INDEX_CFG0080h 0Bh SPECIAL_CFG 0000h 0Bh SPECIAL_CFG SPECIAL_CFG0000h 0Dh RESERVED 0100h 0Dh RESERVED0100h 0Eh MODEM_CFG 0040h 0Eh MODEM_CFG MODEM_CFG0040h 0Fh FIFO_CFG 00F0h 0Fh FIFO_CFG FIFO_CFG00F0h 10h ALARM_ACT 8020h 10h ALARM_ACT ALARM_ACT8020h 11h WDT 0018h 11h WDT WDT0018h 12h AIN0_THRESHOLD FF00h 12h AIN0_THRESHOLD AIN0_THRESHOLDFF00h 13h AIN1_THRESHOLD FF00h 13h AIN1_THRESHOLD AIN1_THRESHOLDFF00h 14h TEMP_THRESHOLD FF00h 14h TEMP_THRESHOLD TEMP_THRESHOLDFF00h 1Bh GPIO_CFG 00FFh 1Bh GPIO_CFG GPIO_CFG00FFh 1Dh ALARM_STATUS_MASK EFDFh 1Dh ALARM_STATUS_MASK ALARM_STATUS_MASKEFDFh 1Eh GEN_STATUS_MASK FFFFh 1Eh GEN_STATUS_MASK GEN_STATUS_MASKFFFFh 1Fh MODEM_STATUS_MASK FFFFh 1Fh MODEM_STATUS_MASK MODEM_STATUS_MASKFFFFh 3Fh RBIST_CRC 0000h 3Fh RBIST_CRC RBIST_CRC0000h Reset There are three reset mechanisms in the device: a power-on reset (POR), a RESET pin, and the SW_RST command that can be sent through the either the SPI or by UBM. When power is first applied to the device, a POR circuit holds the device in reset until all supplies reach the specified operating voltages. The power-on reset returns the device to a known operating state in case a brownout event occurs (when the supplies have dipped below the minimum operating voltages). The POR starts all digital circuits in reset as the supply settles, and releases them to make sure that the device starts in the default condition and loads the OTP memory. After the OTP memory has been loaded, the ALARM pin is released. At this time, communication with the device is safe. This tPOR time is less than 100 µs. The devices also have a RESET pin that is used as a hardware reset to the device. Send the RESET pin low for a minimum of 100 ns (tRESET) to reset the device. A delay time of 10 μs (tRESETWAIT) is required before sending the first serial interface command as the device latches and releases the reset. The release of the internal reset state is synchronized to the internal clock. The RESET pin resets the SPI and the UART interfaces, the HART FIFO buffer, the watchdog timer, the internal oscillator, and the device registers. RESET does not reload the OTP memory. The command to RESET.SW_RST = 0xAD resets the device as a software reset. The command is decoded at the rising edge of CS with an SPI command or during the stop bit of the last character of a UBM frame. Set UBM.REG_MODE again to put the device back into UBM when resetting the device in UBM. After sending the RESET command, no delay time is required before sending the first serial interface command as the device latches and releases the reset. The reset is synchronized to the falling edge of the internal clock and is released well before the next rising edge. The ALARM pin pulses low for the width of the internal reset. This pulse duration is less than 20 ns. This command resets the SPI and the UART interface, the HART FIFO, and the watchdog timer, but does not reset the internal oscillator. The software reset also reloads internal factory trim registers if properly configured in the SPECIAL_CFG register. The SPECIAL_CFG register is only reset with a POR. The POR and hardware reset place the internal oscillator into a reset condition, which holds the clock low. When these two signals are released, there is a delay of a few microseconds before the first rising edge of the clock. The hardware reset, RESET, pulse width must be at least 100 ns to allow the oscillator to properly reset. The SW_RST command is a short pulse. This pulse is not long enough to adequately reset the oscillator. The SW_RST is asserted with a falling edge of the clock. As a result of the long oscillator period, the design architecture provides that all devices are out of reset by the next rising edge. shows the reset tree. Reset Conditions Reset There are three reset mechanisms in the device: a power-on reset (POR), a RESET pin, and the SW_RST command that can be sent through the either the SPI or by UBM. When power is first applied to the device, a POR circuit holds the device in reset until all supplies reach the specified operating voltages. The power-on reset returns the device to a known operating state in case a brownout event occurs (when the supplies have dipped below the minimum operating voltages). The POR starts all digital circuits in reset as the supply settles, and releases them to make sure that the device starts in the default condition and loads the OTP memory. After the OTP memory has been loaded, the ALARM pin is released. At this time, communication with the device is safe. This tPOR time is less than 100 µs. The devices also have a RESET pin that is used as a hardware reset to the device. Send the RESET pin low for a minimum of 100 ns (tRESET) to reset the device. A delay time of 10 μs (tRESETWAIT) is required before sending the first serial interface command as the device latches and releases the reset. The release of the internal reset state is synchronized to the internal clock. The RESET pin resets the SPI and the UART interfaces, the HART FIFO buffer, the watchdog timer, the internal oscillator, and the device registers. RESET does not reload the OTP memory. The command to RESET.SW_RST = 0xAD resets the device as a software reset. The command is decoded at the rising edge of CS with an SPI command or during the stop bit of the last character of a UBM frame. Set UBM.REG_MODE again to put the device back into UBM when resetting the device in UBM. After sending the RESET command, no delay time is required before sending the first serial interface command as the device latches and releases the reset. The reset is synchronized to the falling edge of the internal clock and is released well before the next rising edge. The ALARM pin pulses low for the width of the internal reset. This pulse duration is less than 20 ns. This command resets the SPI and the UART interface, the HART FIFO, and the watchdog timer, but does not reset the internal oscillator. The software reset also reloads internal factory trim registers if properly configured in the SPECIAL_CFG register. The SPECIAL_CFG register is only reset with a POR. The POR and hardware reset place the internal oscillator into a reset condition, which holds the clock low. When these two signals are released, there is a delay of a few microseconds before the first rising edge of the clock. The hardware reset, RESET, pulse width must be at least 100 ns to allow the oscillator to properly reset. The SW_RST command is a short pulse. This pulse is not long enough to adequately reset the oscillator. The SW_RST is asserted with a falling edge of the clock. As a result of the long oscillator period, the design architecture provides that all devices are out of reset by the next rising edge. shows the reset tree. Reset Conditions There are three reset mechanisms in the device: a power-on reset (POR), a RESET pin, and the SW_RST command that can be sent through the either the SPI or by UBM. When power is first applied to the device, a POR circuit holds the device in reset until all supplies reach the specified operating voltages. The power-on reset returns the device to a known operating state in case a brownout event occurs (when the supplies have dipped below the minimum operating voltages). The POR starts all digital circuits in reset as the supply settles, and releases them to make sure that the device starts in the default condition and loads the OTP memory. After the OTP memory has been loaded, the ALARM pin is released. At this time, communication with the device is safe. This tPOR time is less than 100 µs. The devices also have a RESET pin that is used as a hardware reset to the device. Send the RESET pin low for a minimum of 100 ns (tRESET) to reset the device. A delay time of 10 μs (tRESETWAIT) is required before sending the first serial interface command as the device latches and releases the reset. The release of the internal reset state is synchronized to the internal clock. The RESET pin resets the SPI and the UART interfaces, the HART FIFO buffer, the watchdog timer, the internal oscillator, and the device registers. RESET does not reload the OTP memory. The command to RESET.SW_RST = 0xAD resets the device as a software reset. The command is decoded at the rising edge of CS with an SPI command or during the stop bit of the last character of a UBM frame. Set UBM.REG_MODE again to put the device back into UBM when resetting the device in UBM. After sending the RESET command, no delay time is required before sending the first serial interface command as the device latches and releases the reset. The reset is synchronized to the falling edge of the internal clock and is released well before the next rising edge. The ALARM pin pulses low for the width of the internal reset. This pulse duration is less than 20 ns. This command resets the SPI and the UART interface, the HART FIFO, and the watchdog timer, but does not reset the internal oscillator. The software reset also reloads internal factory trim registers if properly configured in the SPECIAL_CFG register. The SPECIAL_CFG register is only reset with a POR. The POR and hardware reset place the internal oscillator into a reset condition, which holds the clock low. When these two signals are released, there is a delay of a few microseconds before the first rising edge of the clock. The hardware reset, RESET, pulse width must be at least 100 ns to allow the oscillator to properly reset. The SW_RST command is a short pulse. This pulse is not long enough to adequately reset the oscillator. The SW_RST is asserted with a falling edge of the clock. As a result of the long oscillator period, the design architecture provides that all devices are out of reset by the next rising edge. shows the reset tree. Reset Conditions There are three reset mechanisms in the device: a power-on reset (POR), a RESET pin, and the SW_RST command that can be sent through the either the SPI or by UBM.RESETWhen power is first applied to the device, a POR circuit holds the device in reset until all supplies reach the specified operating voltages. The power-on reset returns the device to a known operating state in case a brownout event occurs (when the supplies have dipped below the minimum operating voltages). The POR starts all digital circuits in reset as the supply settles, and releases them to make sure that the device starts in the default condition and loads the OTP memory. After the OTP memory has been loaded, the ALARM pin is released. At this time, communication with the device is safe. This tPOR time is less than 100 µs.ALARMPORThe devices also have a RESET pin that is used as a hardware reset to the device. Send the RESET pin low for a minimum of 100 ns (tRESET) to reset the device. A delay time of 10 μs (tRESETWAIT) is required before sending the first serial interface command as the device latches and releases the reset. The release of the internal reset state is synchronized to the internal clock. The RESET pin resets the SPI and the UART interfaces, the HART FIFO buffer, the watchdog timer, the internal oscillator, and the device registers. RESET does not reload the OTP memory.RESETRESETRESETRESETWAITRESET the HART FIFO buffer,RESETThe command to RESET.SW_RST = 0xAD resets the device as a software reset. The command is decoded at the rising edge of CS with an SPI command or during the stop bit of the last character of a UBM frame. Set UBM.REG_MODE again to put the device back into UBM when resetting the device in UBM. After sending the RESET command, no delay time is required before sending the first serial interface command as the device latches and releases the reset. The reset is synchronized to the falling edge of the internal clock and is released well before the next rising edge. The ALARM pin pulses low for the width of the internal reset. This pulse duration is less than 20 ns. This command resets the SPI and the UART interface, the HART FIFO, and the watchdog timer, but does not reset the internal oscillator. The software reset also reloads internal factory trim registers if properly configured in the SPECIAL_CFG register. The SPECIAL_CFG register is only reset with a POR.CSALARMthe HART FIFO, The POR and hardware reset place the internal oscillator into a reset condition, which holds the clock low. When these two signals are released, there is a delay of a few microseconds before the first rising edge of the clock. The hardware reset, RESET, pulse width must be at least 100 ns to allow the oscillator to properly reset. The SW_RST command is a short pulse. This pulse is not long enough to adequately reset the oscillator. The SW_RST is asserted with a falling edge of the clock. As a result of the long oscillator period, the design architecture provides that all devices are out of reset by the next rising edge.RESET shows the reset tree. Reset Conditions Reset Conditions Programming The AFEx82H1 communicate with the system controller through a serial interface that supports either a UART-compatible two-wire bus or an SPI-compatible bus. Based on the hardware configuration, either interface can be enabled. and show the configurations to enable SPI mode and UART break mode (UBM), respectively. The SPI supports an 8-bit frame-by-frame CRC that is enabled by default, but can be disabled by the user. UBM does not support CRC, but does support the UART protocol parity bit. The AFEx82H1 are designed to leverage the existing firmware for communication with DACs or HART modems. A special SPI- and UART-capable dual mode of communication that is available to enable firmware reuse from discrete HART architecture is shown in . See for more details. Communication Setup After any reset or power up, the AFEx82H1 wake up able to use the SPI or UART break mode (UBM). The devices include a robust mechanism that configures the interface between either an SPI-compatible or UART-compatible protocol based system, thus preventing protocol change during normal operation. The selection is based on initial conditions from the respective hardware configurations (see and ) and any subsequent user configuration. In SPI plus UART mode, all communication pins on the system microcontroller are connected to the AFEx82H1, as shown in . SPI Mode By default, the AFEx82H1 can be fully accessed with the SPI (except UBM.REG_MODE). To set up the device in SPI mode: Set CONFIG.UART_DIS = 1 (disables the UART communication). Optionally, set CONFIG.DSDO, CONFIG.FSDO, and CONFIG.IRQ_PIN_EN. For details, see . SPI Mode Connections shows the SPI mode logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the UARTOUT pin functions as the IRQ output. In SPI mode, set CONFIG.SDO_DSDO = 0 to enable the readback function. This function is disabled by default to save power. If the readback function not enabled, SDO remains in Hi-Z mode even during the subsequent frame after a read request. Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tied the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor as indicated to avoid floating IOs. UART Mode At power up, the UART interface is set to 9600 baud with UBM enabled. Any reset clears the UBM register, and the register must be set again to use UBM. To set up the device in UBM: Using UBM, set UBM.REG_MODE = 1 at 9600 baud. This setting blocks the SPI from accessing the device and enables the UART interface access to the entire register map. Optionally, set CONFIG.CLR_PIN_EN and CONFIG.IRQ_PIN_EN (See for details). shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the SDO pin functions as the IRQ output. If CONFIG.CLR_PIN_EN = 1 is set, then the SDI pin controls the clear pin function. Enable each GPIO pin for use through proper register configuration. If a GPIO pin remains unused, tie the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor to avoid floating I/Os. UBM (UART Interface) Connections SPI Plus UART Mode In this mode, communicate with the integrated HART modem using the UART while communicating with the DAC using the SPI. Many discrete DACs use SPI communication, whereas HART modems use UART communication, but this special communication interface enables easy transition from discrete to integrated HART architecture. shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tie the pin to either IOVDD using a pullup or to GND using a pulldown as indicated to avoid floating I/Os. To setup the device in SPI plus UART mode using the SPI, set CONFIG.UART_BAUD = 0 to set the baud rate to 1200 for the UART, and to track the HART baud rate of 1200. The UART also works at a 9600 baud, but the 1200 baud rate of HART must be considered, and the FIFO STATUS must be monitored through the SPI. SPI Plus UART Mode Connections HART Functionality Setup Options #GUID-6C44E4D3-BE4F-4FC5-BC78-8E09FD6B576E/SLVSBY77695 shows the various options to set up HART functionality based on communication options by connected pin. HART Function Setup Options by Communication Pins Used FUNCTION INTERFACE MODE 1 PIN NAME HARDWARE METHOD (PIN CONNECTED) ALTERNATE METHOD (PIN NOT CONNECTED) Request to send (RTS) Any RTS (input) L: RTS asserted. H: RTS deasserted. Write to MODEM_CFG.RTS bit 1: RTS asserted. 0: RTS deasserted. Carrier detect (CD) Any CD (output) L: CD deasserted. H: CD asserted. Connect and setup interrupt request orPoll CD_ASSERT / CD_DEASSERT Clear to send (CTS) Any None Not available Connect and setup interrupt request or Poll CTS_ASSERT Alarm Any ALARM (output) Multiple alarm based interrupt sources for system controller; see also . Connect and setup interrupt request or Poll ALARM_STATUS register Interrupt request (IRQ) 2 UART SDO (output) Level- and polarity-configurable interrupt pin (see ). Multiple interrupt sources for system controller; see also . Set CONFIG.UBM_IRQ_EN = 1 to generate soft IRQ as break command followed by data on UARTOUT. See for details. SPI only UARTOUT (Output) Poll status registers SPI plus UART None Not available Poll status registers For option details, see . For IRQ configuration details, see . GPIO Programming Seven physical pins are interoperable as GPIOs in the AFEx82H1 when not used for communication. The state of these pins is set after the communication interface mode is determined (see for power-up conditions and connection-diagram options for each communication mode supported by the AFEx82H1). Configure any unused communication pins as GPIO, and resistively tie the pins to IOVDD or GND, respectively, as described in . #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/TABLE_A3S_QDJ_MSB shows the pins and pin functions in UBM, SPI Mode, or SPI plus UART mode and lists the register configuration conditions to enable GPIO functionality for each pin. In addition to these register configurations, to use an available pin as GPIO, set the corresponding GPIO_CFG.EN bit. For a GPIO pin to be configured as an input, the following conditions must be met: GPIO_CFG.ODE for the pin must = 1 GPIO.DATA for the pin must = 1 After initialization, the pin state is Hi-Z. Reading the GPIO.DATA register reads the pin value. If the previous conditions are not met, the pin is an output. In this case, the output drive type is determined by the GPIO_CFG.ODE bits to be push-pull or pseudo open drain. The GPIO output is driven by the GPIO.DATA bits. All reads of GPIO.DATA reports the values of the pins, regardless if the pins are configured as GPIO or not. Data written to the GPIO.DATA bits cannot be read directly. If a pin is available for use as GPIO, then the corresponding GPIO_CFG.EN bit must be set to enable GPIO functionality. Pin Configuration in Each Interface Mode PIN UBM SPI SPI PLUS UART REGISTER CONFIGURATION TO ENABLE GPIO #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/LI_PW1_PQF_VVB FUNCTION DIRECTION FUNCTION DIRECTION FUNCTION DIRECTION GPIO6/CS GPIO Input/Output CS Input CS Input (UBM.REG_MODE = 1) GPIO5/SDI CLR/GPIO Input/Output SDI Input SDI Input (UBM.REG_MODE = 1) AND (CONFIG.CLR_PIN_EN = 0) GPIO4/SDO IRQ/GPIO Input/Output SDO Output SDO Output (UBM.REG_MODE = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO3/UARTIN UARTIN Input GPIO Input/Output UARTIN Input (CONFIG.UART_DIS = 1) GPIO2/UARTOUT UARTOUT Output IRQ/GPIO Input/Output UARTOUT Output (CONFIG.UART_DIS = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO1/CD CD Output CD/GPIO Input/Output CD Output (CONFIG.UART_DIS = 1) GPIO0/CLK_OUT CLKO/GPIO Input/Output CLKO/GPIO Input/Output CLKO/GPIO Input/Output (CONFIG.CLKO = 0) AND ((UBM.REGMODE = 1) OR (CONFIG.UART_DIS = 1)) Required by pin in addition to the corresponding GPIO_CFG.EN bit. Serial Peripheral Interface (SPI) The AFEx82H1 are controlled over a versatile four-wire serial interface (SDIN, SDO, SCLK, and CS). The interface operates at clock rates of up to 12.5 MHz and is compatible with SPI, QSPI, Microwire, and digital signal processing (DSP) standards. The SPI communication command consists of a read or write address, a data word, and an optional CRC byte. The SPI can access all register addresses except for the UBM register. Read-only and read-write capability is defined by register (see ). The SPI supports both SPI Mode 1 (CPOL = 0, CPHA = 1) and SPI Mode 2 (CPOL = 1, CPHA = 0). The default SCLK value is low for SPI Mode 1 and high for SPI Mode 2. See for timing diagrams in each mode. The serial clock, SCLK, can be continuous or gated. SPI Frame Definition Subject to the timing requirements listed in the Timing Requirements , the first SCLK falling edge immediately following the falling edge of CS captures the first frame bit. Subject to the same requirements, the last SCLK falling edge before the rising edge of CS captures the last bit of the frame. shows that the SPI shift register frame is 32-bits wide, and consists of an R/W bit, followed by a 7-bit address, and a 16-bit data word. The 8-bit CRC is optional (enabled by default) and is disabled by setting CONFIG.CRC_EN = 0 (see also ). shows that when the CRC is disabled, the frame is 24-bits wide. SPI Frame Details (Default, CRC Enabled) SPI Frame Details (CRC Disabled) For a valid frame, a full frame length of data (24 bits if CRC is disabled or 32 bits if CRC is enabled) must be transmitted before CS is brought high. If CS is brought high before the last falling SCLK edge of a full frame, then the data word is not transferred into the internal registers. If more than a full frame length of falling SCLK edges are applied before CS is brought high, then the last full frame length number of bits are used. In other words, if the number of falling SCLK edges while CS = 0 is 34, then the last 32 SCLK cycles (or 24 if CRC is disabled) are treated as the valid frame. The device internal registers are updated from the SPI shift register on the rising edge of CS. To start another serial transfer, bring CS low again. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is high impedance. SPI Read and Write The SDI input bit is latched on the SCLK falling edge. The SDI pin receives right-justified data. At the rising edge of CS, the right-most (last) bits are evaluated as a frame. Extra clock cycles (exceeding frame length) during the frame begin to output on SDO the SDI data delayed by one frame length. A read operation is started when R/W bit is 1. The data word input for SDI is ignored in the read command frame. Send the subsequent read or write command frame into SDI to clock out the data of the addressed register on SDO. If no other read or write commands are needed, then issue a NOP command to retrieve the requested data. The read register value is output most significant bit first on SDO on successive edges (rising or falling based on CONFIG.FSDO setting) of SCLK. A write operation starts when R/W bit is 0. The SDO output to a write command, delivered in the next frame, contains status bits, data described in , and if the CRC is enabled, an 8-bit CRC for the output frame. Command Functions COMMAND BIT SDI INPUT DATA WORD SDO RESPONSE DATA WORD Write (R/W = 0) Data to be written (16b) 0x0000 Read (R/W = 1) Ignored Register output data (16b) Response data portion in next frame output. The input bits are included in the calculation for CRC, if enabled (see ). Valid SDO output is driven only when CS = 0 and CONFIG.DSDO = 0; otherwise, the SDO pin remains Hi-Z to save power. The SDO data bits are left-justified within the frame, meaning the most significant bit is produced on the line (subject to timing details) when CS is asserted low (bit is driven by falling edge of CS). The subsequent bits in the frame are driven by the rising SCLK edge when CONFIG.FSDO = 0 (default). To drive the SDO data on the falling edge of SCLK, set CONFIG.FSDO = 1. This setting effectively gives the SDO data an additional ½ clock period for setup time, but at the expense of hold time. The frame output on SDO contains the command bit of the input that generated the frame (previous input frame), followed by seven status bits (see ). When an input frame CRC error is detected, the status bit CRC_ERR = 1. If there is no input frame CRC error, then CRC_ERR = 0. See for details. Frame Error Checking If the AFEx82H1 are used in a noisy environment, use the CRC to check the integrity of the SPI data communication between the device and the system controller. This feature is enabled by default and is controlled by the CONFIG.CRC_EN bit. If the CRC is not required in the system, disable frame error checking through the CRC_EN bit, and switch from the default 32-bit frame to the 24-bit frame. Frame error checking is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (9'b100000111). For the output register readback, the AFEx82H1 supply the calculated 8-bit CRC for the 24 bits of data provided, as part of the 32-bit frame. The AFEx82H1 decodes 24-bits of the input frame data and the 8-bit CRC to compute the CRC remainder. If no error exists in the frame, the CRC remainder is zero. When the remainder is nonzero (that is, the input frame has single-bit or multiple-bit errors) the ALARM_STATUS.CRC_ERR_CNT bits are incremented. A bad CRC value prevents execution of commands to the device, which prevents FIFO data from being lost as a result of an invalid read command. When the CRC error counter reaches the limit programmed in CONFIG.CRC_ERR_CNT, the CRC_FLT status bit is set in the ALARM_STATUS register. The fault is reported (as long as the corresponding mask is not set) as an ALARM_IRQ on SDO during the next frame. The ALARM pin asserts low if enabled by the alarm action configuration (see ). The CRC_ERR status bit (see ) in the SDO frame is not sticky and is only reported for the previous frame. The ALARM_STATUS.CRC_FLT bit is sticky and is only cleared after a successful read of the ALARM_STATUS register. Read the GEN_STATUS, MODEM_STATUS or ALARM_STATUS registers to clear any sticky bits that are set. The sticky status bits are cleared at the start of the readback frame and are latched again at the end of the readback frame. Therefore, if the fault condition previously reported in the status register is no longer present at the end of the readback frame, and the data are received by the microcontroller with the CRC error, the fault information is lost. If a robust monitoring of the status bits is required in a noisy environment, use the IRQ pin in combination with the status mask bits to find out the status of each fault before clearing the status bits. Set the CONFIG.IRQ_LVL bit to monitor the signal level on the IRQ pin, and unmask each status bit one at a time to retrieve the information from the status registers. Synchronization The AFEx82H1 register map runs on the internal clock domain. Both the SPI and UBM packets are synchronized to this domain. This synchronization adds a latency of 0.4 µs to 1.22 µs (1.5 internal clocks), with respect to the rising edge of CS or the STOP bit of the last byte of the UBM packet. The effect of clock synchronization on UBM communication is not evident because of the lower speed and asynchronous nature of UBM communication. In SPI mode, if changing register bits CONFIG.DSDO, CONFIG.FSDO, or CONFIG.CRC_EN, keep CS high for at least two clock cycles before issuing the next frame. Frame data corruption can occur if the two extra cycles are not used. The following are examples of frame corruption: Setting CONFIG.DSDO = 0: SDO begins to drive in the middle of the next frame. Changing CONFIG.FSDO: The launching edge of SDO changes in the middle of the next frame. Setting CONFIG.CRC_EN = 1: The next frame has a CRC error because the CRC is enabled in the middle of the frame. Send a NOP command (SDI = 0x00_0000) after setting the DSDO, FSDO, and CRC_EN bits to prevent the corrupted frames from impacting communication. Sending a NOP after CONFIG.CRC_EN is set still generates a CRC error, and is reported in the STATUS portion of SDO. To avoid false errors, wait approximately 2 µs after setting CONFIG.CRC_EN before sending the next frame. UART Interface In UART mode, the device expects 1 start bit, 8 data bits, 1 odd parity bit, and 1 stop bit, or an 8O1 UART character format. When using SPI to communicate with the registers, and only using UART for HART communication, use 1200 baud. The baud must have ±1% accuracy. UART Break Mode (UBM) In UART break mode (UBM), the microcontroller issues a UART break to start communication. The device interprets the UART break as the start to receive commands from the UART. A communication UART character consists of one start bit, eight data bits, one odd parity bit, and at least one stop bit. A UART break character is all 11 bits (including start, data, parity and stop bit) held low by the microcontroller on the UARTIN pin and by the AFEx82H1 on the UARTOUT pin. When a valid break character is detected on UARTIN by the AFEx82H1, no parity (even though parity is odd) or stop bit errors are flagged for this character. The parity and stop bit differences between valid UBM break and communication characters must be managed by the system microcontroller when receiving these characters from the UARTOUT pin of the AFEx82H1. See for UBM break character, communication timing details, and bit order. Two baud rates are supported for UART communication: 9600 and 1200. The 9600 baud rate is default for UBM. The 1200 baud rate is supported to maintain backward compatibility and requires the use of SPI to communicate with the register map; whereas, the UART pins are used only for HART communication. The baud rates are selected by register bit CONFIG.UART_BAUD. When CONFIG.UART_BAUD = 1 (default), the UART operates at 9600 baud. When CONFIG.UART_BAUD = 0, the UART operates at 1200 baud. The break function of the UART protocol is enabled only for 9600 baud. This configuration allows interleaving of HART data with register communication and enables the access to all registers of the device, when configured correctly. Set UBM.REG_MODE = 1 to enable register map access through the UART. By default, this bit is set to 0. The entire register map can only be accessed with SPI, except for the UBM register. The UBM register can only be accessed with UBM. After UBM.REG_MODE is set to 1, the SPI does not have access to the register map, and the full register map is accessible by UBM. A UBM data output packet is initiated by AFEx82H1 on UARTOUT in two cases. See for packet structure details. If the R/IRQn status bit is 0 an IRQ event initiated the break command. If the R/IRQn status bit is 1, the break command is a response to the prior read request. For details on HART data see . To enable IRQ events, set CONFIG.UBM_IRQ_EN = 1. When IRQ is enabled, the AFEx82H1 triggers a break command followed by data on UARTOUT (see ). The contents of the data are listed in order of priority below. If ALARM_IRQ bit is set, then the contents of the ALARM_STATUS register are output. If GEN_IRQ is set, then the contents of the GEN_STATUS register are output. If MODEM_IRQ bit is set, then the contents of the MODEM_STATUS register are output. If none of the previous bits are set, then an IRQ is not generated. A break byte is followed by three bytes. These three bytes have information identical to the SPI frame without the CRC (see ). The CRC cannot be enabled for UBM. All communication characters on the UART bus are transmitted least significant data bit (D0) first. shows the data structure of the UBM write command, and shows the data structure of the UBM read command. UARTIN Break Write Data Format UARTIN Break Read Data Format shows the UARTOUT data frame with details of the status bits produced by the AFEx82H1. See for details. UARTOUT Break Data Format Interface With FIFO Buffers and Register Map In UBM, the HART data characters are interleaved with break commands for register map access or interrupt reporting. The device reports parity and frame errors received on UARTIN. These status bits can be found in the GEN_STATUS register and are maskable to create IRQ events. Avoid the large gaps between the HART bytes. The HART standard has a gap specification of 11 bit times (11 × tBAUDHART ms); therefore, gaps longer than 10.5 HART bit times (10.5 × tBAUDHART ms) can cause a gap error in the HART modem. The following timing diagrams illustrate examples of microcontroller communication with the device registers, as well as HART transmit and receive data transfers. Interleaved HART Transmit With UBM Register Writes Packed HART Transmit With UBM Register Writes Interleaved HART Transmit With UBM Register Read Requests and Responses Packed HART Transmit With UBM Register Write and Read Requests and Responses Interleaved HART Receive With UBM Register Write and Read Requests and Responses Status Bits In SPI mode and UBM, every response from the AFEx82H1 includes a set of status bits. For SPI mode bit order, see . For UBM bit order, . Status Bits STATUS BIT DESCRIPTION NOTES / REFERENCE ALARM_IRQ 1h = ALARM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . CRC_ERR(CRC enabled SPI only) 1h = CRC error detect in input frame 0h = No CRC error detected Generated by the SPI on a frame by frame basis. See . GEN_IRQ 1h = GEN_IRQ asserted 0h = Normal Operation From the ALARM_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . MODEM_IRQ 1h = MODEM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . OSC_DIV_1024 (UBM mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 1024) sampled at the falling edge of the status byte start bit. See also . OSC_DIV_2 (SPI mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 2) sampled at CS falling edge. See also . R/IRQn (UBM only) 1h = Read request 0h = IRQ event Generated by the UART interface on a frame by frame basis. See for details. RBIST 1h = RBIST busy (registers not readable) 0h = RBIST done (registers readable) RBIST running status. See for details. RESET 1h = First readback after RESET0h = All other readbacks From the GEN_STATUS register (). See also . ALARM_STATUS, MODEM_STATUS, and GEN_STATUS registers contain cross-readable IRQ flags for the other registers. The ALARM_STATUS register has the GEN_IRQ and MODEM_IRQ bits. MODEM_STATUS has the GEN_IRQ and ALARM_IRQ bits. GEN_STATUS has the ALARM_IRQ and MODEM_IRQ bits. This functionality enables the system microcontroller to always get full status information by reading only one register, and thus save power. Watchdog Timer The AFEx82H1 include a watchdog timer (WDT) that is used to make sure that communication between the system controller and the device is not lost. The WDT checks that the device received a communication from the system controller within a programmable period of time. To enable this feature, set WDT.WDT_EN to 1. The WDT monitors both SPI and UBM communications. The WDT has two limit fields: WDT.WDT_UP and WDT.WDT_LO. The WDT_UP field sets the upper time limit for the WDT. The WDT_LO field sets the lower time limit. If the WDT_LO is set to a value other than 2’b00, then the WDT acts as a window comparator. If the write occurs too quickly (less than the WDT_LO time), or too slowly (greater than the WDT_UP time), then a WDT error is asserted. When acting as a window comparator, in the event of a WDT error, the WDT resets only when a write to the WDT register occurs. If the WDT_LO is set to 2'b00, then a write to any register resets the WDT time counter. In this mode, the WDT error is asserted when the timer expires. If enabled, the chip must have any SPI or UBM write to the device within the programmed timeout window. Otherwise, the ALARM pin asserts low, and the ALARM_STATUS.WD_FLT bit is set to 1. The WD_FLT bit is sticky. After a WD_FLT has been asserted, WDT.WDT_EN must be set to 0 to clear the WDT condition. Then the WDT can be re-enabled. The WDT condition is also cleared by issuing a software or hardware reset. After the WDT condition is clear, WD_FLT is cleared by reading the ALARM_STATUS register. When using multiple AFEx82H1 devices in a daisy-chain configuration, connect the open-drain ALARM pins of all devices together to form a wired-OR network. The watchdog timer can be enabled in any number of the devices in the chain; although, enabling the watchdog timer in one device in the chain is usually sufficient. The wired-OR ALARM pin can be pulled low in response to the simultaneous presence of different trigger conditions in the devices in the daisy-chain. The host processor must read the ALARM_STATUS register of each device to know all the fault conditions present in the chain. The watchdog timeout period is based on a 1200-Hz clock (1.2288 MHz / 1024). Programming The AFEx82H1 communicate with the system controller through a serial interface that supports either a UART-compatible two-wire bus or an SPI-compatible bus. Based on the hardware configuration, either interface can be enabled. and show the configurations to enable SPI mode and UART break mode (UBM), respectively. The SPI supports an 8-bit frame-by-frame CRC that is enabled by default, but can be disabled by the user. UBM does not support CRC, but does support the UART protocol parity bit. The AFEx82H1 are designed to leverage the existing firmware for communication with DACs or HART modems. A special SPI- and UART-capable dual mode of communication that is available to enable firmware reuse from discrete HART architecture is shown in . See for more details. The AFEx82H1 communicate with the system controller through a serial interface that supports either a UART-compatible two-wire bus or an SPI-compatible bus. Based on the hardware configuration, either interface can be enabled. and show the configurations to enable SPI mode and UART break mode (UBM), respectively. The SPI supports an 8-bit frame-by-frame CRC that is enabled by default, but can be disabled by the user. UBM does not support CRC, but does support the UART protocol parity bit. The AFEx82H1 are designed to leverage the existing firmware for communication with DACs or HART modems. A special SPI- and UART-capable dual mode of communication that is available to enable firmware reuse from discrete HART architecture is shown in . See for more details. The AFEx82H1 communicate with the system controller through a serial interface that supports either a UART-compatible two-wire bus or an SPI-compatible bus. Based on the hardware configuration, either interface can be enabled. and show the configurations to enable SPI mode and UART break mode (UBM), respectively. The SPI supports an 8-bit frame-by-frame CRC that is enabled by default, but can be disabled by the user. UBM does not support CRC, but does support the UART protocol parity bit. AFEx82H1The AFEx82H1 are designed to leverage the existing firmware for communication with DACs or HART modems. A special SPI- and UART-capable dual mode of communication that is available to enable firmware reuse from discrete HART architecture is shown in . See for more details.AFEx82H1 Communication Setup After any reset or power up, the AFEx82H1 wake up able to use the SPI or UART break mode (UBM). The devices include a robust mechanism that configures the interface between either an SPI-compatible or UART-compatible protocol based system, thus preventing protocol change during normal operation. The selection is based on initial conditions from the respective hardware configurations (see and ) and any subsequent user configuration. In SPI plus UART mode, all communication pins on the system microcontroller are connected to the AFEx82H1, as shown in . SPI Mode By default, the AFEx82H1 can be fully accessed with the SPI (except UBM.REG_MODE). To set up the device in SPI mode: Set CONFIG.UART_DIS = 1 (disables the UART communication). Optionally, set CONFIG.DSDO, CONFIG.FSDO, and CONFIG.IRQ_PIN_EN. For details, see . SPI Mode Connections shows the SPI mode logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the UARTOUT pin functions as the IRQ output. In SPI mode, set CONFIG.SDO_DSDO = 0 to enable the readback function. This function is disabled by default to save power. If the readback function not enabled, SDO remains in Hi-Z mode even during the subsequent frame after a read request. Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tied the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor as indicated to avoid floating IOs. UART Mode At power up, the UART interface is set to 9600 baud with UBM enabled. Any reset clears the UBM register, and the register must be set again to use UBM. To set up the device in UBM: Using UBM, set UBM.REG_MODE = 1 at 9600 baud. This setting blocks the SPI from accessing the device and enables the UART interface access to the entire register map. Optionally, set CONFIG.CLR_PIN_EN and CONFIG.IRQ_PIN_EN (See for details). shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the SDO pin functions as the IRQ output. If CONFIG.CLR_PIN_EN = 1 is set, then the SDI pin controls the clear pin function. Enable each GPIO pin for use through proper register configuration. If a GPIO pin remains unused, tie the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor to avoid floating I/Os. UBM (UART Interface) Connections SPI Plus UART Mode In this mode, communicate with the integrated HART modem using the UART while communicating with the DAC using the SPI. Many discrete DACs use SPI communication, whereas HART modems use UART communication, but this special communication interface enables easy transition from discrete to integrated HART architecture. shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tie the pin to either IOVDD using a pullup or to GND using a pulldown as indicated to avoid floating I/Os. To setup the device in SPI plus UART mode using the SPI, set CONFIG.UART_BAUD = 0 to set the baud rate to 1200 for the UART, and to track the HART baud rate of 1200. The UART also works at a 9600 baud, but the 1200 baud rate of HART must be considered, and the FIFO STATUS must be monitored through the SPI. SPI Plus UART Mode Connections HART Functionality Setup Options #GUID-6C44E4D3-BE4F-4FC5-BC78-8E09FD6B576E/SLVSBY77695 shows the various options to set up HART functionality based on communication options by connected pin. HART Function Setup Options by Communication Pins Used FUNCTION INTERFACE MODE 1 PIN NAME HARDWARE METHOD (PIN CONNECTED) ALTERNATE METHOD (PIN NOT CONNECTED) Request to send (RTS) Any RTS (input) L: RTS asserted. H: RTS deasserted. Write to MODEM_CFG.RTS bit 1: RTS asserted. 0: RTS deasserted. Carrier detect (CD) Any CD (output) L: CD deasserted. H: CD asserted. Connect and setup interrupt request orPoll CD_ASSERT / CD_DEASSERT Clear to send (CTS) Any None Not available Connect and setup interrupt request or Poll CTS_ASSERT Alarm Any ALARM (output) Multiple alarm based interrupt sources for system controller; see also . Connect and setup interrupt request or Poll ALARM_STATUS register Interrupt request (IRQ) 2 UART SDO (output) Level- and polarity-configurable interrupt pin (see ). Multiple interrupt sources for system controller; see also . Set CONFIG.UBM_IRQ_EN = 1 to generate soft IRQ as break command followed by data on UARTOUT. See for details. SPI only UARTOUT (Output) Poll status registers SPI plus UART None Not available Poll status registers For option details, see . For IRQ configuration details, see . Communication Setup After any reset or power up, the AFEx82H1 wake up able to use the SPI or UART break mode (UBM). The devices include a robust mechanism that configures the interface between either an SPI-compatible or UART-compatible protocol based system, thus preventing protocol change during normal operation. The selection is based on initial conditions from the respective hardware configurations (see and ) and any subsequent user configuration. In SPI plus UART mode, all communication pins on the system microcontroller are connected to the AFEx82H1, as shown in . After any reset or power up, the AFEx82H1 wake up able to use the SPI or UART break mode (UBM). The devices include a robust mechanism that configures the interface between either an SPI-compatible or UART-compatible protocol based system, thus preventing protocol change during normal operation. The selection is based on initial conditions from the respective hardware configurations (see and ) and any subsequent user configuration. In SPI plus UART mode, all communication pins on the system microcontroller are connected to the AFEx82H1, as shown in . After any reset or power up, the AFEx82H1 wake up able to use the SPI or UART break mode (UBM). The devices include a robust mechanism that configures the interface between either an SPI-compatible or UART-compatible protocol based system, thus preventing protocol change during normal operation. The selection is based on initial conditions from the respective hardware configurations (see and ) and any subsequent user configuration. AFEx82H1 In SPI plus UART mode, all communication pins on the system microcontroller are connected to the AFEx82H1, as shown in . In SPI plus UART mode, all communication pins on the system microcontroller are connected to the AFEx82H1, as shown in .AFEx82H1 SPI Mode By default, the AFEx82H1 can be fully accessed with the SPI (except UBM.REG_MODE). To set up the device in SPI mode: Set CONFIG.UART_DIS = 1 (disables the UART communication). Optionally, set CONFIG.DSDO, CONFIG.FSDO, and CONFIG.IRQ_PIN_EN. For details, see . SPI Mode Connections shows the SPI mode logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the UARTOUT pin functions as the IRQ output. In SPI mode, set CONFIG.SDO_DSDO = 0 to enable the readback function. This function is disabled by default to save power. If the readback function not enabled, SDO remains in Hi-Z mode even during the subsequent frame after a read request. Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tied the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor as indicated to avoid floating IOs. SPI Mode By default, the AFEx82H1 can be fully accessed with the SPI (except UBM.REG_MODE). To set up the device in SPI mode: Set CONFIG.UART_DIS = 1 (disables the UART communication). Optionally, set CONFIG.DSDO, CONFIG.FSDO, and CONFIG.IRQ_PIN_EN. For details, see . SPI Mode Connections shows the SPI mode logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the UARTOUT pin functions as the IRQ output. In SPI mode, set CONFIG.SDO_DSDO = 0 to enable the readback function. This function is disabled by default to save power. If the readback function not enabled, SDO remains in Hi-Z mode even during the subsequent frame after a read request. Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tied the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor as indicated to avoid floating IOs. By default, the AFEx82H1 can be fully accessed with the SPI (except UBM.REG_MODE). To set up the device in SPI mode: Set CONFIG.UART_DIS = 1 (disables the UART communication). Optionally, set CONFIG.DSDO, CONFIG.FSDO, and CONFIG.IRQ_PIN_EN. For details, see . SPI Mode Connections shows the SPI mode logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the UARTOUT pin functions as the IRQ output. In SPI mode, set CONFIG.SDO_DSDO = 0 to enable the readback function. This function is disabled by default to save power. If the readback function not enabled, SDO remains in Hi-Z mode even during the subsequent frame after a read request. Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tied the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor as indicated to avoid floating IOs. By default, the AFEx82H1 can be fully accessed with the SPI (except UBM.REG_MODE). To set up the device in SPI mode:AFEx82H1 Set CONFIG.UART_DIS = 1 (disables the UART communication). Optionally, set CONFIG.DSDO, CONFIG.FSDO, and CONFIG.IRQ_PIN_EN. For details, see . Set CONFIG.UART_DIS = 1 (disables the UART communication).Optionally, set CONFIG.DSDO, CONFIG.FSDO, and CONFIG.IRQ_PIN_EN. For details, see . SPI Mode Connections SPI Mode Connections shows the SPI mode logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the UARTOUT pin functions as the IRQ output. In SPI mode, set CONFIG.SDO_DSDO = 0 to enable the readback function. This function is disabled by default to save power. If the readback function not enabled, SDO remains in Hi-Z mode even during the subsequent frame after a read request. Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tied the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor as indicated to avoid floating IOs. communication communication , most GPIO pins available showncommunication communication , least GPIO pins available shown Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tied the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor as indicated to avoid floating IOs. UART Mode At power up, the UART interface is set to 9600 baud with UBM enabled. Any reset clears the UBM register, and the register must be set again to use UBM. To set up the device in UBM: Using UBM, set UBM.REG_MODE = 1 at 9600 baud. This setting blocks the SPI from accessing the device and enables the UART interface access to the entire register map. Optionally, set CONFIG.CLR_PIN_EN and CONFIG.IRQ_PIN_EN (See for details). shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the SDO pin functions as the IRQ output. If CONFIG.CLR_PIN_EN = 1 is set, then the SDI pin controls the clear pin function. Enable each GPIO pin for use through proper register configuration. If a GPIO pin remains unused, tie the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor to avoid floating I/Os. UBM (UART Interface) Connections UART Mode At power up, the UART interface is set to 9600 baud with UBM enabled. Any reset clears the UBM register, and the register must be set again to use UBM. To set up the device in UBM: Using UBM, set UBM.REG_MODE = 1 at 9600 baud. This setting blocks the SPI from accessing the device and enables the UART interface access to the entire register map. Optionally, set CONFIG.CLR_PIN_EN and CONFIG.IRQ_PIN_EN (See for details). shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the SDO pin functions as the IRQ output. If CONFIG.CLR_PIN_EN = 1 is set, then the SDI pin controls the clear pin function. Enable each GPIO pin for use through proper register configuration. If a GPIO pin remains unused, tie the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor to avoid floating I/Os. UBM (UART Interface) Connections At power up, the UART interface is set to 9600 baud with UBM enabled. Any reset clears the UBM register, and the register must be set again to use UBM. To set up the device in UBM: Using UBM, set UBM.REG_MODE = 1 at 9600 baud. This setting blocks the SPI from accessing the device and enables the UART interface access to the entire register map. Optionally, set CONFIG.CLR_PIN_EN and CONFIG.IRQ_PIN_EN (See for details). shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the SDO pin functions as the IRQ output. If CONFIG.CLR_PIN_EN = 1 is set, then the SDI pin controls the clear pin function. Enable each GPIO pin for use through proper register configuration. If a GPIO pin remains unused, tie the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor to avoid floating I/Os. UBM (UART Interface) Connections At power up, the UART interface is set to 9600 baud with UBM enabled. Any reset clears the UBM register, and the register must be set again to use UBM. To set up the device in UBM: Using UBM, set UBM.REG_MODE = 1 at 9600 baud. This setting blocks the SPI from accessing the device and enables the UART interface access to the entire register map. Optionally, set CONFIG.CLR_PIN_EN and CONFIG.IRQ_PIN_EN (See for details). Using UBM, set UBM.REG_MODE = 1 at 9600 baud. This setting blocks the SPI from accessing the device and enables the UART interface access to the entire register map.Optionally, set CONFIG.CLR_PIN_EN and CONFIG.IRQ_PIN_EN (See for details). shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the SDO pin functions as the IRQ output. If CONFIG.CLR_PIN_EN = 1 is set, then the SDI pin controls the clear pin function. Enable each GPIO pin for use through proper register configuration. If a GPIO pin remains unused, tie the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor to avoid floating I/Os. communication communication , most GPIO pins available showncommunication communication , least GPIO pins available shownEnable each GPIO pin for use through proper register configuration. If a GPIO pin remains unused, tie the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor to avoid floating I/Os. UBM (UART Interface) Connections UBM (UART Interface) Connections SPI Plus UART Mode In this mode, communicate with the integrated HART modem using the UART while communicating with the DAC using the SPI. Many discrete DACs use SPI communication, whereas HART modems use UART communication, but this special communication interface enables easy transition from discrete to integrated HART architecture. shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tie the pin to either IOVDD using a pullup or to GND using a pulldown as indicated to avoid floating I/Os. To setup the device in SPI plus UART mode using the SPI, set CONFIG.UART_BAUD = 0 to set the baud rate to 1200 for the UART, and to track the HART baud rate of 1200. The UART also works at a 9600 baud, but the 1200 baud rate of HART must be considered, and the FIFO STATUS must be monitored through the SPI. SPI Plus UART Mode Connections SPI Plus UART Mode In this mode, communicate with the integrated HART modem using the UART while communicating with the DAC using the SPI. Many discrete DACs use SPI communication, whereas HART modems use UART communication, but this special communication interface enables easy transition from discrete to integrated HART architecture. shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tie the pin to either IOVDD using a pullup or to GND using a pulldown as indicated to avoid floating I/Os. To setup the device in SPI plus UART mode using the SPI, set CONFIG.UART_BAUD = 0 to set the baud rate to 1200 for the UART, and to track the HART baud rate of 1200. The UART also works at a 9600 baud, but the 1200 baud rate of HART must be considered, and the FIFO STATUS must be monitored through the SPI. SPI Plus UART Mode Connections In this mode, communicate with the integrated HART modem using the UART while communicating with the DAC using the SPI. Many discrete DACs use SPI communication, whereas HART modems use UART communication, but this special communication interface enables easy transition from discrete to integrated HART architecture. shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tie the pin to either IOVDD using a pullup or to GND using a pulldown as indicated to avoid floating I/Os. To setup the device in SPI plus UART mode using the SPI, set CONFIG.UART_BAUD = 0 to set the baud rate to 1200 for the UART, and to track the HART baud rate of 1200. The UART also works at a 9600 baud, but the 1200 baud rate of HART must be considered, and the FIFO STATUS must be monitored through the SPI. SPI Plus UART Mode Connections In this mode, communicate with the integrated HART modem using the UART while communicating with the DAC using the SPI. Many discrete DACs use SPI communication, whereas HART modems use UART communication, but this special communication interface enables easy transition from discrete to integrated HART architecture. shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected, most GPIO pins available shown) and maximum communication functionality (all communication pins connected, least GPIO pins available shown). Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tie the pin to either IOVDD using a pullup or to GND using a pulldown as indicated to avoid floating I/Os. communication communication , most GPIO pins available showncommunication communication , least GPIO pins available shown Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tie the pin to either IOVDD using a pullup or to GND using a pulldown as indicated to avoid floating I/Os.To setup the device in SPI plus UART mode using the SPI, set CONFIG.UART_BAUD = 0 to set the baud rate to 1200 for the UART, and to track the HART baud rate of 1200. The UART also works at a 9600 baud, but the 1200 baud rate of HART must be considered, and the FIFO STATUS must be monitored through the SPI. SPI Plus UART Mode Connections SPI Plus UART Mode Connections HART Functionality Setup Options #GUID-6C44E4D3-BE4F-4FC5-BC78-8E09FD6B576E/SLVSBY77695 shows the various options to set up HART functionality based on communication options by connected pin. HART Function Setup Options by Communication Pins Used FUNCTION INTERFACE MODE 1 PIN NAME HARDWARE METHOD (PIN CONNECTED) ALTERNATE METHOD (PIN NOT CONNECTED) Request to send (RTS) Any RTS (input) L: RTS asserted. H: RTS deasserted. Write to MODEM_CFG.RTS bit 1: RTS asserted. 0: RTS deasserted. Carrier detect (CD) Any CD (output) L: CD deasserted. H: CD asserted. Connect and setup interrupt request orPoll CD_ASSERT / CD_DEASSERT Clear to send (CTS) Any None Not available Connect and setup interrupt request or Poll CTS_ASSERT Alarm Any ALARM (output) Multiple alarm based interrupt sources for system controller; see also . Connect and setup interrupt request or Poll ALARM_STATUS register Interrupt request (IRQ) 2 UART SDO (output) Level- and polarity-configurable interrupt pin (see ). Multiple interrupt sources for system controller; see also . Set CONFIG.UBM_IRQ_EN = 1 to generate soft IRQ as break command followed by data on UARTOUT. See for details. SPI only UARTOUT (Output) Poll status registers SPI plus UART None Not available Poll status registers For option details, see . For IRQ configuration details, see . HART Functionality Setup Options #GUID-6C44E4D3-BE4F-4FC5-BC78-8E09FD6B576E/SLVSBY77695 shows the various options to set up HART functionality based on communication options by connected pin. HART Function Setup Options by Communication Pins Used FUNCTION INTERFACE MODE 1 PIN NAME HARDWARE METHOD (PIN CONNECTED) ALTERNATE METHOD (PIN NOT CONNECTED) Request to send (RTS) Any RTS (input) L: RTS asserted. H: RTS deasserted. Write to MODEM_CFG.RTS bit 1: RTS asserted. 0: RTS deasserted. Carrier detect (CD) Any CD (output) L: CD deasserted. H: CD asserted. Connect and setup interrupt request orPoll CD_ASSERT / CD_DEASSERT Clear to send (CTS) Any None Not available Connect and setup interrupt request or Poll CTS_ASSERT Alarm Any ALARM (output) Multiple alarm based interrupt sources for system controller; see also . Connect and setup interrupt request or Poll ALARM_STATUS register Interrupt request (IRQ) 2 UART SDO (output) Level- and polarity-configurable interrupt pin (see ). Multiple interrupt sources for system controller; see also . Set CONFIG.UBM_IRQ_EN = 1 to generate soft IRQ as break command followed by data on UARTOUT. See for details. SPI only UARTOUT (Output) Poll status registers SPI plus UART None Not available Poll status registers For option details, see . For IRQ configuration details, see . #GUID-6C44E4D3-BE4F-4FC5-BC78-8E09FD6B576E/SLVSBY77695 shows the various options to set up HART functionality based on communication options by connected pin. HART Function Setup Options by Communication Pins Used FUNCTION INTERFACE MODE 1 PIN NAME HARDWARE METHOD (PIN CONNECTED) ALTERNATE METHOD (PIN NOT CONNECTED) Request to send (RTS) Any RTS (input) L: RTS asserted. H: RTS deasserted. Write to MODEM_CFG.RTS bit 1: RTS asserted. 0: RTS deasserted. Carrier detect (CD) Any CD (output) L: CD deasserted. H: CD asserted. Connect and setup interrupt request orPoll CD_ASSERT / CD_DEASSERT Clear to send (CTS) Any None Not available Connect and setup interrupt request or Poll CTS_ASSERT Alarm Any ALARM (output) Multiple alarm based interrupt sources for system controller; see also . Connect and setup interrupt request or Poll ALARM_STATUS register Interrupt request (IRQ) 2 UART SDO (output) Level- and polarity-configurable interrupt pin (see ). Multiple interrupt sources for system controller; see also . Set CONFIG.UBM_IRQ_EN = 1 to generate soft IRQ as break command followed by data on UARTOUT. See for details. SPI only UARTOUT (Output) Poll status registers SPI plus UART None Not available Poll status registers For option details, see . For IRQ configuration details, see . #GUID-6C44E4D3-BE4F-4FC5-BC78-8E09FD6B576E/SLVSBY77695 shows the various options to set up HART functionality based on communication options by connected pin.#GUID-6C44E4D3-BE4F-4FC5-BC78-8E09FD6B576E/SLVSBY77695 HART Function Setup Options by Communication Pins Used FUNCTION INTERFACE MODE 1 PIN NAME HARDWARE METHOD (PIN CONNECTED) ALTERNATE METHOD (PIN NOT CONNECTED) Request to send (RTS) Any RTS (input) L: RTS asserted. H: RTS deasserted. Write to MODEM_CFG.RTS bit 1: RTS asserted. 0: RTS deasserted. Carrier detect (CD) Any CD (output) L: CD deasserted. H: CD asserted. Connect and setup interrupt request orPoll CD_ASSERT / CD_DEASSERT Clear to send (CTS) Any None Not available Connect and setup interrupt request or Poll CTS_ASSERT Alarm Any ALARM (output) Multiple alarm based interrupt sources for system controller; see also . Connect and setup interrupt request or Poll ALARM_STATUS register Interrupt request (IRQ) 2 UART SDO (output) Level- and polarity-configurable interrupt pin (see ). Multiple interrupt sources for system controller; see also . Set CONFIG.UBM_IRQ_EN = 1 to generate soft IRQ as break command followed by data on UARTOUT. See for details. SPI only UARTOUT (Output) Poll status registers SPI plus UART None Not available Poll status registers HART Function Setup Options by Communication Pins Used FUNCTION INTERFACE MODE 1 PIN NAME HARDWARE METHOD (PIN CONNECTED) ALTERNATE METHOD (PIN NOT CONNECTED) Request to send (RTS) Any RTS (input) L: RTS asserted. H: RTS deasserted. Write to MODEM_CFG.RTS bit 1: RTS asserted. 0: RTS deasserted. Carrier detect (CD) Any CD (output) L: CD deasserted. H: CD asserted. Connect and setup interrupt request orPoll CD_ASSERT / CD_DEASSERT Clear to send (CTS) Any None Not available Connect and setup interrupt request or Poll CTS_ASSERT Alarm Any ALARM (output) Multiple alarm based interrupt sources for system controller; see also . Connect and setup interrupt request or Poll ALARM_STATUS register Interrupt request (IRQ) 2 UART SDO (output) Level- and polarity-configurable interrupt pin (see ). Multiple interrupt sources for system controller; see also . Set CONFIG.UBM_IRQ_EN = 1 to generate soft IRQ as break command followed by data on UARTOUT. See for details. SPI only UARTOUT (Output) Poll status registers SPI plus UART None Not available Poll status registers FUNCTION INTERFACE MODE 1 PIN NAME HARDWARE METHOD (PIN CONNECTED) ALTERNATE METHOD (PIN NOT CONNECTED) FUNCTION INTERFACE MODE 1 PIN NAME HARDWARE METHOD (PIN CONNECTED) ALTERNATE METHOD (PIN NOT CONNECTED) FUNCTIONINTERFACE MODE 1 1 1PIN NAMEHARDWARE METHOD (PIN CONNECTED)ALTERNATE METHOD (PIN NOT CONNECTED) Request to send (RTS) Any RTS (input) L: RTS asserted. H: RTS deasserted. Write to MODEM_CFG.RTS bit 1: RTS asserted. 0: RTS deasserted. Carrier detect (CD) Any CD (output) L: CD deasserted. H: CD asserted. Connect and setup interrupt request orPoll CD_ASSERT / CD_DEASSERT Clear to send (CTS) Any None Not available Connect and setup interrupt request or Poll CTS_ASSERT Alarm Any ALARM (output) Multiple alarm based interrupt sources for system controller; see also . Connect and setup interrupt request or Poll ALARM_STATUS register Interrupt request (IRQ) 2 UART SDO (output) Level- and polarity-configurable interrupt pin (see ). Multiple interrupt sources for system controller; see also . Set CONFIG.UBM_IRQ_EN = 1 to generate soft IRQ as break command followed by data on UARTOUT. See for details. SPI only UARTOUT (Output) Poll status registers SPI plus UART None Not available Poll status registers Request to send (RTS) Any RTS (input) L: RTS asserted. H: RTS deasserted. Write to MODEM_CFG.RTS bit 1: RTS asserted. 0: RTS deasserted. Request to send (RTS)Any RTS (input)RTS L: RTS asserted. H: RTS deasserted. L: RTS asserted. H: RTS deasserted. Write to MODEM_CFG.RTS bit 1: RTS asserted. 0: RTS deasserted. Write to MODEM_CFG.RTS bit1: RTS asserted. 0: RTS deasserted. Carrier detect (CD) Any CD (output) L: CD deasserted. H: CD asserted. Connect and setup interrupt request orPoll CD_ASSERT / CD_DEASSERT Carrier detect (CD)AnyCD (output) L: CD deasserted. H: CD asserted. L: CD deasserted. H: CD asserted.Connect and setup interrupt request orPoll CD_ASSERT / CD_DEASSERT Clear to send (CTS) Any None Not available Connect and setup interrupt request or Poll CTS_ASSERT Clear to send (CTS)AnyNoneNot availableConnect and setup interrupt request or Poll CTS_ASSERT Alarm Any ALARM (output) Multiple alarm based interrupt sources for system controller; see also . Connect and setup interrupt request or Poll ALARM_STATUS register Alarm Any ALARM (output)ALARM Multiple alarm based interrupt sources for system controller; see also .Connect and setup interrupt request or Poll ALARM_STATUS register Interrupt request (IRQ) 2 UART SDO (output) Level- and polarity-configurable interrupt pin (see ). Multiple interrupt sources for system controller; see also . Set CONFIG.UBM_IRQ_EN = 1 to generate soft IRQ as break command followed by data on UARTOUT. See for details. Interrupt request (IRQ) 2 2 2UARTSDO (output)Level- and polarity-configurable interrupt pin (see ). Multiple interrupt sources for system controller; see also . Set CONFIG.UBM_IRQ_EN = 1 to generate soft IRQ as break command followed by data on UARTOUT. See for details. SPI only UARTOUT (Output) Poll status registers SPI onlyUARTOUT (Output)Poll status registers SPI plus UART None Not available Poll status registers SPI plus UARTNoneNot availablePoll status registers For option details, see . For IRQ configuration details, see . For option details, see .For IRQ configuration details, see . GPIO Programming Seven physical pins are interoperable as GPIOs in the AFEx82H1 when not used for communication. The state of these pins is set after the communication interface mode is determined (see for power-up conditions and connection-diagram options for each communication mode supported by the AFEx82H1). Configure any unused communication pins as GPIO, and resistively tie the pins to IOVDD or GND, respectively, as described in . #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/TABLE_A3S_QDJ_MSB shows the pins and pin functions in UBM, SPI Mode, or SPI plus UART mode and lists the register configuration conditions to enable GPIO functionality for each pin. In addition to these register configurations, to use an available pin as GPIO, set the corresponding GPIO_CFG.EN bit. For a GPIO pin to be configured as an input, the following conditions must be met: GPIO_CFG.ODE for the pin must = 1 GPIO.DATA for the pin must = 1 After initialization, the pin state is Hi-Z. Reading the GPIO.DATA register reads the pin value. If the previous conditions are not met, the pin is an output. In this case, the output drive type is determined by the GPIO_CFG.ODE bits to be push-pull or pseudo open drain. The GPIO output is driven by the GPIO.DATA bits. All reads of GPIO.DATA reports the values of the pins, regardless if the pins are configured as GPIO or not. Data written to the GPIO.DATA bits cannot be read directly. If a pin is available for use as GPIO, then the corresponding GPIO_CFG.EN bit must be set to enable GPIO functionality. Pin Configuration in Each Interface Mode PIN UBM SPI SPI PLUS UART REGISTER CONFIGURATION TO ENABLE GPIO #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/LI_PW1_PQF_VVB FUNCTION DIRECTION FUNCTION DIRECTION FUNCTION DIRECTION GPIO6/CS GPIO Input/Output CS Input CS Input (UBM.REG_MODE = 1) GPIO5/SDI CLR/GPIO Input/Output SDI Input SDI Input (UBM.REG_MODE = 1) AND (CONFIG.CLR_PIN_EN = 0) GPIO4/SDO IRQ/GPIO Input/Output SDO Output SDO Output (UBM.REG_MODE = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO3/UARTIN UARTIN Input GPIO Input/Output UARTIN Input (CONFIG.UART_DIS = 1) GPIO2/UARTOUT UARTOUT Output IRQ/GPIO Input/Output UARTOUT Output (CONFIG.UART_DIS = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO1/CD CD Output CD/GPIO Input/Output CD Output (CONFIG.UART_DIS = 1) GPIO0/CLK_OUT CLKO/GPIO Input/Output CLKO/GPIO Input/Output CLKO/GPIO Input/Output (CONFIG.CLKO = 0) AND ((UBM.REGMODE = 1) OR (CONFIG.UART_DIS = 1)) Required by pin in addition to the corresponding GPIO_CFG.EN bit. GPIO Programming Seven physical pins are interoperable as GPIOs in the AFEx82H1 when not used for communication. The state of these pins is set after the communication interface mode is determined (see for power-up conditions and connection-diagram options for each communication mode supported by the AFEx82H1). Configure any unused communication pins as GPIO, and resistively tie the pins to IOVDD or GND, respectively, as described in . #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/TABLE_A3S_QDJ_MSB shows the pins and pin functions in UBM, SPI Mode, or SPI plus UART mode and lists the register configuration conditions to enable GPIO functionality for each pin. In addition to these register configurations, to use an available pin as GPIO, set the corresponding GPIO_CFG.EN bit. For a GPIO pin to be configured as an input, the following conditions must be met: GPIO_CFG.ODE for the pin must = 1 GPIO.DATA for the pin must = 1 After initialization, the pin state is Hi-Z. Reading the GPIO.DATA register reads the pin value. If the previous conditions are not met, the pin is an output. In this case, the output drive type is determined by the GPIO_CFG.ODE bits to be push-pull or pseudo open drain. The GPIO output is driven by the GPIO.DATA bits. All reads of GPIO.DATA reports the values of the pins, regardless if the pins are configured as GPIO or not. Data written to the GPIO.DATA bits cannot be read directly. If a pin is available for use as GPIO, then the corresponding GPIO_CFG.EN bit must be set to enable GPIO functionality. Pin Configuration in Each Interface Mode PIN UBM SPI SPI PLUS UART REGISTER CONFIGURATION TO ENABLE GPIO #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/LI_PW1_PQF_VVB FUNCTION DIRECTION FUNCTION DIRECTION FUNCTION DIRECTION GPIO6/CS GPIO Input/Output CS Input CS Input (UBM.REG_MODE = 1) GPIO5/SDI CLR/GPIO Input/Output SDI Input SDI Input (UBM.REG_MODE = 1) AND (CONFIG.CLR_PIN_EN = 0) GPIO4/SDO IRQ/GPIO Input/Output SDO Output SDO Output (UBM.REG_MODE = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO3/UARTIN UARTIN Input GPIO Input/Output UARTIN Input (CONFIG.UART_DIS = 1) GPIO2/UARTOUT UARTOUT Output IRQ/GPIO Input/Output UARTOUT Output (CONFIG.UART_DIS = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO1/CD CD Output CD/GPIO Input/Output CD Output (CONFIG.UART_DIS = 1) GPIO0/CLK_OUT CLKO/GPIO Input/Output CLKO/GPIO Input/Output CLKO/GPIO Input/Output (CONFIG.CLKO = 0) AND ((UBM.REGMODE = 1) OR (CONFIG.UART_DIS = 1)) Required by pin in addition to the corresponding GPIO_CFG.EN bit. Seven physical pins are interoperable as GPIOs in the AFEx82H1 when not used for communication. The state of these pins is set after the communication interface mode is determined (see for power-up conditions and connection-diagram options for each communication mode supported by the AFEx82H1). Configure any unused communication pins as GPIO, and resistively tie the pins to IOVDD or GND, respectively, as described in . #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/TABLE_A3S_QDJ_MSB shows the pins and pin functions in UBM, SPI Mode, or SPI plus UART mode and lists the register configuration conditions to enable GPIO functionality for each pin. In addition to these register configurations, to use an available pin as GPIO, set the corresponding GPIO_CFG.EN bit. For a GPIO pin to be configured as an input, the following conditions must be met: GPIO_CFG.ODE for the pin must = 1 GPIO.DATA for the pin must = 1 After initialization, the pin state is Hi-Z. Reading the GPIO.DATA register reads the pin value. If the previous conditions are not met, the pin is an output. In this case, the output drive type is determined by the GPIO_CFG.ODE bits to be push-pull or pseudo open drain. The GPIO output is driven by the GPIO.DATA bits. All reads of GPIO.DATA reports the values of the pins, regardless if the pins are configured as GPIO or not. Data written to the GPIO.DATA bits cannot be read directly. If a pin is available for use as GPIO, then the corresponding GPIO_CFG.EN bit must be set to enable GPIO functionality. Pin Configuration in Each Interface Mode PIN UBM SPI SPI PLUS UART REGISTER CONFIGURATION TO ENABLE GPIO #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/LI_PW1_PQF_VVB FUNCTION DIRECTION FUNCTION DIRECTION FUNCTION DIRECTION GPIO6/CS GPIO Input/Output CS Input CS Input (UBM.REG_MODE = 1) GPIO5/SDI CLR/GPIO Input/Output SDI Input SDI Input (UBM.REG_MODE = 1) AND (CONFIG.CLR_PIN_EN = 0) GPIO4/SDO IRQ/GPIO Input/Output SDO Output SDO Output (UBM.REG_MODE = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO3/UARTIN UARTIN Input GPIO Input/Output UARTIN Input (CONFIG.UART_DIS = 1) GPIO2/UARTOUT UARTOUT Output IRQ/GPIO Input/Output UARTOUT Output (CONFIG.UART_DIS = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO1/CD CD Output CD/GPIO Input/Output CD Output (CONFIG.UART_DIS = 1) GPIO0/CLK_OUT CLKO/GPIO Input/Output CLKO/GPIO Input/Output CLKO/GPIO Input/Output (CONFIG.CLKO = 0) AND ((UBM.REGMODE = 1) OR (CONFIG.UART_DIS = 1)) Required by pin in addition to the corresponding GPIO_CFG.EN bit. Seven physical pins are interoperable as GPIOs in the AFEx82H1 when not used for communication. The state of these pins is set after the communication interface mode is determined (see for power-up conditions and connection-diagram options for each communication mode supported by the AFEx82H1). Configure any unused communication pins as GPIO, and resistively tie the pins to IOVDD or GND, respectively, as described in .AFEx82H1AFEx82H1 #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/TABLE_A3S_QDJ_MSB shows the pins and pin functions in UBM, SPI Mode, or SPI plus UART mode and lists the register configuration conditions to enable GPIO functionality for each pin. In addition to these register configurations, to use an available pin as GPIO, set the corresponding GPIO_CFG.EN bit.#GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/TABLE_A3S_QDJ_MSB, SPI Mode, or SPI plus UART modeFor a GPIO pin to be configured as an input, the following conditions must be met: GPIO_CFG.ODE for the pin must = 1 GPIO.DATA for the pin must = 1 GPIO_CFG.ODE for the pin must = 1GPIO.DATA for the pin must = 1After initialization, the pin state is Hi-Z. Reading the GPIO.DATA register reads the pin value.If the previous conditions are not met, the pin is an output. In this case, the output drive type is determined by the GPIO_CFG.ODE bits to be push-pull or pseudo open drain. The GPIO output is driven by the GPIO.DATA bits. All reads of GPIO.DATA reports the values of the pins, regardless if the pins are configured as GPIO or not. Data written to the GPIO.DATA bits cannot be read directly. If a pin is available for use as GPIO, then the corresponding GPIO_CFG.EN bit must be set to enable GPIO functionality. Pin Configuration in Each Interface Mode PIN UBM SPI SPI PLUS UART REGISTER CONFIGURATION TO ENABLE GPIO #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/LI_PW1_PQF_VVB FUNCTION DIRECTION FUNCTION DIRECTION FUNCTION DIRECTION GPIO6/CS GPIO Input/Output CS Input CS Input (UBM.REG_MODE = 1) GPIO5/SDI CLR/GPIO Input/Output SDI Input SDI Input (UBM.REG_MODE = 1) AND (CONFIG.CLR_PIN_EN = 0) GPIO4/SDO IRQ/GPIO Input/Output SDO Output SDO Output (UBM.REG_MODE = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO3/UARTIN UARTIN Input GPIO Input/Output UARTIN Input (CONFIG.UART_DIS = 1) GPIO2/UARTOUT UARTOUT Output IRQ/GPIO Input/Output UARTOUT Output (CONFIG.UART_DIS = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO1/CD CD Output CD/GPIO Input/Output CD Output (CONFIG.UART_DIS = 1) GPIO0/CLK_OUT CLKO/GPIO Input/Output CLKO/GPIO Input/Output CLKO/GPIO Input/Output (CONFIG.CLKO = 0) AND ((UBM.REGMODE = 1) OR (CONFIG.UART_DIS = 1)) Pin Configuration in Each Interface Mode PIN UBM SPI SPI PLUS UART REGISTER CONFIGURATION TO ENABLE GPIO #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/LI_PW1_PQF_VVB FUNCTION DIRECTION FUNCTION DIRECTION FUNCTION DIRECTION GPIO6/CS GPIO Input/Output CS Input CS Input (UBM.REG_MODE = 1) GPIO5/SDI CLR/GPIO Input/Output SDI Input SDI Input (UBM.REG_MODE = 1) AND (CONFIG.CLR_PIN_EN = 0) GPIO4/SDO IRQ/GPIO Input/Output SDO Output SDO Output (UBM.REG_MODE = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO3/UARTIN UARTIN Input GPIO Input/Output UARTIN Input (CONFIG.UART_DIS = 1) GPIO2/UARTOUT UARTOUT Output IRQ/GPIO Input/Output UARTOUT Output (CONFIG.UART_DIS = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO1/CD CD Output CD/GPIO Input/Output CD Output (CONFIG.UART_DIS = 1) GPIO0/CLK_OUT CLKO/GPIO Input/Output CLKO/GPIO Input/Output CLKO/GPIO Input/Output (CONFIG.CLKO = 0) AND ((UBM.REGMODE = 1) OR (CONFIG.UART_DIS = 1)) PIN UBM SPI SPI PLUS UART REGISTER CONFIGURATION TO ENABLE GPIO #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/LI_PW1_PQF_VVB FUNCTION DIRECTION FUNCTION DIRECTION FUNCTION DIRECTION PIN UBM SPI SPI PLUS UART REGISTER CONFIGURATION TO ENABLE GPIO #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/LI_PW1_PQF_VVB PINUBMSPISPI PLUS UART REGISTER CONFIGURATION TO ENABLE GPIO #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/LI_PW1_PQF_VVB #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/LI_PW1_PQF_VVB #GUID-AC39C9E9-25BF-402C-8596-483CEA8EEB0C/LI_PW1_PQF_VVB FUNCTION DIRECTION FUNCTION DIRECTION FUNCTION DIRECTION FUNCTIONDIRECTIONFUNCTIONDIRECTIONFUNCTIONDIRECTION GPIO6/CS GPIO Input/Output CS Input CS Input (UBM.REG_MODE = 1) GPIO5/SDI CLR/GPIO Input/Output SDI Input SDI Input (UBM.REG_MODE = 1) AND (CONFIG.CLR_PIN_EN = 0) GPIO4/SDO IRQ/GPIO Input/Output SDO Output SDO Output (UBM.REG_MODE = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO3/UARTIN UARTIN Input GPIO Input/Output UARTIN Input (CONFIG.UART_DIS = 1) GPIO2/UARTOUT UARTOUT Output IRQ/GPIO Input/Output UARTOUT Output (CONFIG.UART_DIS = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO1/CD CD Output CD/GPIO Input/Output CD Output (CONFIG.UART_DIS = 1) GPIO0/CLK_OUT CLKO/GPIO Input/Output CLKO/GPIO Input/Output CLKO/GPIO Input/Output (CONFIG.CLKO = 0) AND ((UBM.REGMODE = 1) OR (CONFIG.UART_DIS = 1)) GPIO6/CS GPIO Input/Output CS Input CS Input (UBM.REG_MODE = 1) GPIO6/CS CSGPIOInput/Output CS CSInput CS CSInput(UBM.REG_MODE = 1) GPIO5/SDI CLR/GPIO Input/Output SDI Input SDI Input (UBM.REG_MODE = 1) AND (CONFIG.CLR_PIN_EN = 0) GPIO5/SDICLR/GPIOInput/OutputSDIInputSDIInput(UBM.REG_MODE = 1) AND (CONFIG.CLR_PIN_EN = 0) GPIO4/SDO IRQ/GPIO Input/Output SDO Output SDO Output (UBM.REG_MODE = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO4/SDOIRQ/GPIOInput/OutputSDOOutputSDOOutput(UBM.REG_MODE = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO3/UARTIN UARTIN Input GPIO Input/Output UARTIN Input (CONFIG.UART_DIS = 1) GPIO3/UARTINUARTINInputGPIOInput/OutputUARTINInput(CONFIG.UART_DIS = 1) GPIO2/UARTOUT UARTOUT Output IRQ/GPIO Input/Output UARTOUT Output (CONFIG.UART_DIS = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO2/UARTOUTUARTOUTOutputIRQ/GPIOInput/OutputUARTOUTOutput(CONFIG.UART_DIS = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO1/CD CD Output CD/GPIO Input/Output CD Output (CONFIG.UART_DIS = 1) GPIO1/CDCDOutputCD/GPIOInput/OutputCDOutput(CONFIG.UART_DIS = 1) GPIO0/CLK_OUT CLKO/GPIO Input/Output CLKO/GPIO Input/Output CLKO/GPIO Input/Output (CONFIG.CLKO = 0) AND ((UBM.REGMODE = 1) OR (CONFIG.UART_DIS = 1)) GPIO0/CLK_OUTCLKO/GPIOInput/OutputCLKO/GPIOInput/OutputCLKO/GPIOInput/Output(CONFIG.CLKO = 0) AND ((UBM.REGMODE = 1) OR (CONFIG.UART_DIS = 1)) Required by pin in addition to the corresponding GPIO_CFG.EN bit. Required by pin in addition to the corresponding GPIO_CFG.EN bit. Serial Peripheral Interface (SPI) The AFEx82H1 are controlled over a versatile four-wire serial interface (SDIN, SDO, SCLK, and CS). The interface operates at clock rates of up to 12.5 MHz and is compatible with SPI, QSPI, Microwire, and digital signal processing (DSP) standards. The SPI communication command consists of a read or write address, a data word, and an optional CRC byte. The SPI can access all register addresses except for the UBM register. Read-only and read-write capability is defined by register (see ). The SPI supports both SPI Mode 1 (CPOL = 0, CPHA = 1) and SPI Mode 2 (CPOL = 1, CPHA = 0). The default SCLK value is low for SPI Mode 1 and high for SPI Mode 2. See for timing diagrams in each mode. The serial clock, SCLK, can be continuous or gated. SPI Frame Definition Subject to the timing requirements listed in the Timing Requirements , the first SCLK falling edge immediately following the falling edge of CS captures the first frame bit. Subject to the same requirements, the last SCLK falling edge before the rising edge of CS captures the last bit of the frame. shows that the SPI shift register frame is 32-bits wide, and consists of an R/W bit, followed by a 7-bit address, and a 16-bit data word. The 8-bit CRC is optional (enabled by default) and is disabled by setting CONFIG.CRC_EN = 0 (see also ). shows that when the CRC is disabled, the frame is 24-bits wide. SPI Frame Details (Default, CRC Enabled) SPI Frame Details (CRC Disabled) For a valid frame, a full frame length of data (24 bits if CRC is disabled or 32 bits if CRC is enabled) must be transmitted before CS is brought high. If CS is brought high before the last falling SCLK edge of a full frame, then the data word is not transferred into the internal registers. If more than a full frame length of falling SCLK edges are applied before CS is brought high, then the last full frame length number of bits are used. In other words, if the number of falling SCLK edges while CS = 0 is 34, then the last 32 SCLK cycles (or 24 if CRC is disabled) are treated as the valid frame. The device internal registers are updated from the SPI shift register on the rising edge of CS. To start another serial transfer, bring CS low again. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is high impedance. SPI Read and Write The SDI input bit is latched on the SCLK falling edge. The SDI pin receives right-justified data. At the rising edge of CS, the right-most (last) bits are evaluated as a frame. Extra clock cycles (exceeding frame length) during the frame begin to output on SDO the SDI data delayed by one frame length. A read operation is started when R/W bit is 1. The data word input for SDI is ignored in the read command frame. Send the subsequent read or write command frame into SDI to clock out the data of the addressed register on SDO. If no other read or write commands are needed, then issue a NOP command to retrieve the requested data. The read register value is output most significant bit first on SDO on successive edges (rising or falling based on CONFIG.FSDO setting) of SCLK. A write operation starts when R/W bit is 0. The SDO output to a write command, delivered in the next frame, contains status bits, data described in , and if the CRC is enabled, an 8-bit CRC for the output frame. Command Functions COMMAND BIT SDI INPUT DATA WORD SDO RESPONSE DATA WORD Write (R/W = 0) Data to be written (16b) 0x0000 Read (R/W = 1) Ignored Register output data (16b) Response data portion in next frame output. The input bits are included in the calculation for CRC, if enabled (see ). Valid SDO output is driven only when CS = 0 and CONFIG.DSDO = 0; otherwise, the SDO pin remains Hi-Z to save power. The SDO data bits are left-justified within the frame, meaning the most significant bit is produced on the line (subject to timing details) when CS is asserted low (bit is driven by falling edge of CS). The subsequent bits in the frame are driven by the rising SCLK edge when CONFIG.FSDO = 0 (default). To drive the SDO data on the falling edge of SCLK, set CONFIG.FSDO = 1. This setting effectively gives the SDO data an additional ½ clock period for setup time, but at the expense of hold time. The frame output on SDO contains the command bit of the input that generated the frame (previous input frame), followed by seven status bits (see ). When an input frame CRC error is detected, the status bit CRC_ERR = 1. If there is no input frame CRC error, then CRC_ERR = 0. See for details. Frame Error Checking If the AFEx82H1 are used in a noisy environment, use the CRC to check the integrity of the SPI data communication between the device and the system controller. This feature is enabled by default and is controlled by the CONFIG.CRC_EN bit. If the CRC is not required in the system, disable frame error checking through the CRC_EN bit, and switch from the default 32-bit frame to the 24-bit frame. Frame error checking is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (9'b100000111). For the output register readback, the AFEx82H1 supply the calculated 8-bit CRC for the 24 bits of data provided, as part of the 32-bit frame. The AFEx82H1 decodes 24-bits of the input frame data and the 8-bit CRC to compute the CRC remainder. If no error exists in the frame, the CRC remainder is zero. When the remainder is nonzero (that is, the input frame has single-bit or multiple-bit errors) the ALARM_STATUS.CRC_ERR_CNT bits are incremented. A bad CRC value prevents execution of commands to the device, which prevents FIFO data from being lost as a result of an invalid read command. When the CRC error counter reaches the limit programmed in CONFIG.CRC_ERR_CNT, the CRC_FLT status bit is set in the ALARM_STATUS register. The fault is reported (as long as the corresponding mask is not set) as an ALARM_IRQ on SDO during the next frame. The ALARM pin asserts low if enabled by the alarm action configuration (see ). The CRC_ERR status bit (see ) in the SDO frame is not sticky and is only reported for the previous frame. The ALARM_STATUS.CRC_FLT bit is sticky and is only cleared after a successful read of the ALARM_STATUS register. Read the GEN_STATUS, MODEM_STATUS or ALARM_STATUS registers to clear any sticky bits that are set. The sticky status bits are cleared at the start of the readback frame and are latched again at the end of the readback frame. Therefore, if the fault condition previously reported in the status register is no longer present at the end of the readback frame, and the data are received by the microcontroller with the CRC error, the fault information is lost. If a robust monitoring of the status bits is required in a noisy environment, use the IRQ pin in combination with the status mask bits to find out the status of each fault before clearing the status bits. Set the CONFIG.IRQ_LVL bit to monitor the signal level on the IRQ pin, and unmask each status bit one at a time to retrieve the information from the status registers. Synchronization The AFEx82H1 register map runs on the internal clock domain. Both the SPI and UBM packets are synchronized to this domain. This synchronization adds a latency of 0.4 µs to 1.22 µs (1.5 internal clocks), with respect to the rising edge of CS or the STOP bit of the last byte of the UBM packet. The effect of clock synchronization on UBM communication is not evident because of the lower speed and asynchronous nature of UBM communication. In SPI mode, if changing register bits CONFIG.DSDO, CONFIG.FSDO, or CONFIG.CRC_EN, keep CS high for at least two clock cycles before issuing the next frame. Frame data corruption can occur if the two extra cycles are not used. The following are examples of frame corruption: Setting CONFIG.DSDO = 0: SDO begins to drive in the middle of the next frame. Changing CONFIG.FSDO: The launching edge of SDO changes in the middle of the next frame. Setting CONFIG.CRC_EN = 1: The next frame has a CRC error because the CRC is enabled in the middle of the frame. Send a NOP command (SDI = 0x00_0000) after setting the DSDO, FSDO, and CRC_EN bits to prevent the corrupted frames from impacting communication. Sending a NOP after CONFIG.CRC_EN is set still generates a CRC error, and is reported in the STATUS portion of SDO. To avoid false errors, wait approximately 2 µs after setting CONFIG.CRC_EN before sending the next frame. Serial Peripheral Interface (SPI) The AFEx82H1 are controlled over a versatile four-wire serial interface (SDIN, SDO, SCLK, and CS). The interface operates at clock rates of up to 12.5 MHz and is compatible with SPI, QSPI, Microwire, and digital signal processing (DSP) standards. The SPI communication command consists of a read or write address, a data word, and an optional CRC byte. The SPI can access all register addresses except for the UBM register. Read-only and read-write capability is defined by register (see ). The SPI supports both SPI Mode 1 (CPOL = 0, CPHA = 1) and SPI Mode 2 (CPOL = 1, CPHA = 0). The default SCLK value is low for SPI Mode 1 and high for SPI Mode 2. See for timing diagrams in each mode. The serial clock, SCLK, can be continuous or gated. The AFEx82H1 are controlled over a versatile four-wire serial interface (SDIN, SDO, SCLK, and CS). The interface operates at clock rates of up to 12.5 MHz and is compatible with SPI, QSPI, Microwire, and digital signal processing (DSP) standards. The SPI communication command consists of a read or write address, a data word, and an optional CRC byte. The SPI can access all register addresses except for the UBM register. Read-only and read-write capability is defined by register (see ). The SPI supports both SPI Mode 1 (CPOL = 0, CPHA = 1) and SPI Mode 2 (CPOL = 1, CPHA = 0). The default SCLK value is low for SPI Mode 1 and high for SPI Mode 2. See for timing diagrams in each mode. The serial clock, SCLK, can be continuous or gated. The AFEx82H1 are controlled over a versatile four-wire serial interface (SDIN, SDO, SCLK, and CS). The interface operates at clock rates of up to 12.5 MHz and is compatible with SPI, QSPI, Microwire, and digital signal processing (DSP) standards. The SPI communication command consists of a read or write address, a data word, and an optional CRC byte.AFEx82H1CSThe SPI can access all register addresses except for the UBM register. Read-only and read-write capability is defined by register (see ). The SPI supports both SPI Mode 1 (CPOL = 0, CPHA = 1) and SPI Mode 2 (CPOL = 1, CPHA = 0). The default SCLK value is low for SPI Mode 1 and high for SPI Mode 2. See for timing diagrams in each mode. The serial clock, SCLK, can be continuous or gated. SPI Frame Definition Subject to the timing requirements listed in the Timing Requirements , the first SCLK falling edge immediately following the falling edge of CS captures the first frame bit. Subject to the same requirements, the last SCLK falling edge before the rising edge of CS captures the last bit of the frame. shows that the SPI shift register frame is 32-bits wide, and consists of an R/W bit, followed by a 7-bit address, and a 16-bit data word. The 8-bit CRC is optional (enabled by default) and is disabled by setting CONFIG.CRC_EN = 0 (see also ). shows that when the CRC is disabled, the frame is 24-bits wide. SPI Frame Details (Default, CRC Enabled) SPI Frame Details (CRC Disabled) For a valid frame, a full frame length of data (24 bits if CRC is disabled or 32 bits if CRC is enabled) must be transmitted before CS is brought high. If CS is brought high before the last falling SCLK edge of a full frame, then the data word is not transferred into the internal registers. If more than a full frame length of falling SCLK edges are applied before CS is brought high, then the last full frame length number of bits are used. In other words, if the number of falling SCLK edges while CS = 0 is 34, then the last 32 SCLK cycles (or 24 if CRC is disabled) are treated as the valid frame. The device internal registers are updated from the SPI shift register on the rising edge of CS. To start another serial transfer, bring CS low again. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is high impedance. SPI Frame Definition Subject to the timing requirements listed in the Timing Requirements , the first SCLK falling edge immediately following the falling edge of CS captures the first frame bit. Subject to the same requirements, the last SCLK falling edge before the rising edge of CS captures the last bit of the frame. shows that the SPI shift register frame is 32-bits wide, and consists of an R/W bit, followed by a 7-bit address, and a 16-bit data word. The 8-bit CRC is optional (enabled by default) and is disabled by setting CONFIG.CRC_EN = 0 (see also ). shows that when the CRC is disabled, the frame is 24-bits wide. SPI Frame Details (Default, CRC Enabled) SPI Frame Details (CRC Disabled) For a valid frame, a full frame length of data (24 bits if CRC is disabled or 32 bits if CRC is enabled) must be transmitted before CS is brought high. If CS is brought high before the last falling SCLK edge of a full frame, then the data word is not transferred into the internal registers. If more than a full frame length of falling SCLK edges are applied before CS is brought high, then the last full frame length number of bits are used. In other words, if the number of falling SCLK edges while CS = 0 is 34, then the last 32 SCLK cycles (or 24 if CRC is disabled) are treated as the valid frame. The device internal registers are updated from the SPI shift register on the rising edge of CS. To start another serial transfer, bring CS low again. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is high impedance. Subject to the timing requirements listed in the Timing Requirements , the first SCLK falling edge immediately following the falling edge of CS captures the first frame bit. Subject to the same requirements, the last SCLK falling edge before the rising edge of CS captures the last bit of the frame. shows that the SPI shift register frame is 32-bits wide, and consists of an R/W bit, followed by a 7-bit address, and a 16-bit data word. The 8-bit CRC is optional (enabled by default) and is disabled by setting CONFIG.CRC_EN = 0 (see also ). shows that when the CRC is disabled, the frame is 24-bits wide. SPI Frame Details (Default, CRC Enabled) SPI Frame Details (CRC Disabled) For a valid frame, a full frame length of data (24 bits if CRC is disabled or 32 bits if CRC is enabled) must be transmitted before CS is brought high. If CS is brought high before the last falling SCLK edge of a full frame, then the data word is not transferred into the internal registers. If more than a full frame length of falling SCLK edges are applied before CS is brought high, then the last full frame length number of bits are used. In other words, if the number of falling SCLK edges while CS = 0 is 34, then the last 32 SCLK cycles (or 24 if CRC is disabled) are treated as the valid frame. The device internal registers are updated from the SPI shift register on the rising edge of CS. To start another serial transfer, bring CS low again. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is high impedance. Subject to the timing requirements listed in the Timing Requirements , the first SCLK falling edge immediately following the falling edge of CS captures the first frame bit. Subject to the same requirements, the last SCLK falling edge before the rising edge of CS captures the last bit of the frame. shows that the SPI shift register frame is 32-bits wide, and consists of an R/W bit, followed by a 7-bit address, and a 16-bit data word. The 8-bit CRC is optional (enabled by default) and is disabled by setting CONFIG.CRC_EN = 0 (see also ). shows that when the CRC is disabled, the frame is 24-bits wide. Timing Requirements Timing Requirements Timing RequirementsCSCS SPI Frame Details (Default, CRC Enabled) SPI Frame Details (Default, CRC Enabled) SPI Frame Details (CRC Disabled) SPI Frame Details (CRC Disabled)For a valid frame, a full frame length of data (24 bits if CRC is disabled or 32 bits if CRC is enabled) must be transmitted before CS is brought high. If CS is brought high before the last falling SCLK edge of a full frame, then the data word is not transferred into the internal registers. If more than a full frame length of falling SCLK edges are applied before CS is brought high, then the last full frame length number of bits are used. In other words, if the number of falling SCLK edges while CS = 0 is 34, then the last 32 SCLK cycles (or 24 if CRC is disabled) are treated as the valid frame. The device internal registers are updated from the SPI shift register on the rising edge of CS. To start another serial transfer, bring CS low again. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is high impedance.CSCSCSCSCSCSCS SPI Read and Write The SDI input bit is latched on the SCLK falling edge. The SDI pin receives right-justified data. At the rising edge of CS, the right-most (last) bits are evaluated as a frame. Extra clock cycles (exceeding frame length) during the frame begin to output on SDO the SDI data delayed by one frame length. A read operation is started when R/W bit is 1. The data word input for SDI is ignored in the read command frame. Send the subsequent read or write command frame into SDI to clock out the data of the addressed register on SDO. If no other read or write commands are needed, then issue a NOP command to retrieve the requested data. The read register value is output most significant bit first on SDO on successive edges (rising or falling based on CONFIG.FSDO setting) of SCLK. A write operation starts when R/W bit is 0. The SDO output to a write command, delivered in the next frame, contains status bits, data described in , and if the CRC is enabled, an 8-bit CRC for the output frame. Command Functions COMMAND BIT SDI INPUT DATA WORD SDO RESPONSE DATA WORD Write (R/W = 0) Data to be written (16b) 0x0000 Read (R/W = 1) Ignored Register output data (16b) Response data portion in next frame output. The input bits are included in the calculation for CRC, if enabled (see ). Valid SDO output is driven only when CS = 0 and CONFIG.DSDO = 0; otherwise, the SDO pin remains Hi-Z to save power. The SDO data bits are left-justified within the frame, meaning the most significant bit is produced on the line (subject to timing details) when CS is asserted low (bit is driven by falling edge of CS). The subsequent bits in the frame are driven by the rising SCLK edge when CONFIG.FSDO = 0 (default). To drive the SDO data on the falling edge of SCLK, set CONFIG.FSDO = 1. This setting effectively gives the SDO data an additional ½ clock period for setup time, but at the expense of hold time. The frame output on SDO contains the command bit of the input that generated the frame (previous input frame), followed by seven status bits (see ). When an input frame CRC error is detected, the status bit CRC_ERR = 1. If there is no input frame CRC error, then CRC_ERR = 0. See for details. SPI Read and Write The SDI input bit is latched on the SCLK falling edge. The SDI pin receives right-justified data. At the rising edge of CS, the right-most (last) bits are evaluated as a frame. Extra clock cycles (exceeding frame length) during the frame begin to output on SDO the SDI data delayed by one frame length. A read operation is started when R/W bit is 1. The data word input for SDI is ignored in the read command frame. Send the subsequent read or write command frame into SDI to clock out the data of the addressed register on SDO. If no other read or write commands are needed, then issue a NOP command to retrieve the requested data. The read register value is output most significant bit first on SDO on successive edges (rising or falling based on CONFIG.FSDO setting) of SCLK. A write operation starts when R/W bit is 0. The SDO output to a write command, delivered in the next frame, contains status bits, data described in , and if the CRC is enabled, an 8-bit CRC for the output frame. Command Functions COMMAND BIT SDI INPUT DATA WORD SDO RESPONSE DATA WORD Write (R/W = 0) Data to be written (16b) 0x0000 Read (R/W = 1) Ignored Register output data (16b) Response data portion in next frame output. The input bits are included in the calculation for CRC, if enabled (see ). Valid SDO output is driven only when CS = 0 and CONFIG.DSDO = 0; otherwise, the SDO pin remains Hi-Z to save power. The SDO data bits are left-justified within the frame, meaning the most significant bit is produced on the line (subject to timing details) when CS is asserted low (bit is driven by falling edge of CS). The subsequent bits in the frame are driven by the rising SCLK edge when CONFIG.FSDO = 0 (default). To drive the SDO data on the falling edge of SCLK, set CONFIG.FSDO = 1. This setting effectively gives the SDO data an additional ½ clock period for setup time, but at the expense of hold time. The frame output on SDO contains the command bit of the input that generated the frame (previous input frame), followed by seven status bits (see ). When an input frame CRC error is detected, the status bit CRC_ERR = 1. If there is no input frame CRC error, then CRC_ERR = 0. See for details. The SDI input bit is latched on the SCLK falling edge. The SDI pin receives right-justified data. At the rising edge of CS, the right-most (last) bits are evaluated as a frame. Extra clock cycles (exceeding frame length) during the frame begin to output on SDO the SDI data delayed by one frame length. A read operation is started when R/W bit is 1. The data word input for SDI is ignored in the read command frame. Send the subsequent read or write command frame into SDI to clock out the data of the addressed register on SDO. If no other read or write commands are needed, then issue a NOP command to retrieve the requested data. The read register value is output most significant bit first on SDO on successive edges (rising or falling based on CONFIG.FSDO setting) of SCLK. A write operation starts when R/W bit is 0. The SDO output to a write command, delivered in the next frame, contains status bits, data described in , and if the CRC is enabled, an 8-bit CRC for the output frame. Command Functions COMMAND BIT SDI INPUT DATA WORD SDO RESPONSE DATA WORD Write (R/W = 0) Data to be written (16b) 0x0000 Read (R/W = 1) Ignored Register output data (16b) Response data portion in next frame output. The input bits are included in the calculation for CRC, if enabled (see ). Valid SDO output is driven only when CS = 0 and CONFIG.DSDO = 0; otherwise, the SDO pin remains Hi-Z to save power. The SDO data bits are left-justified within the frame, meaning the most significant bit is produced on the line (subject to timing details) when CS is asserted low (bit is driven by falling edge of CS). The subsequent bits in the frame are driven by the rising SCLK edge when CONFIG.FSDO = 0 (default). To drive the SDO data on the falling edge of SCLK, set CONFIG.FSDO = 1. This setting effectively gives the SDO data an additional ½ clock period for setup time, but at the expense of hold time. The frame output on SDO contains the command bit of the input that generated the frame (previous input frame), followed by seven status bits (see ). When an input frame CRC error is detected, the status bit CRC_ERR = 1. If there is no input frame CRC error, then CRC_ERR = 0. See for details. The SDI input bit is latched on the SCLK falling edge. The SDI pin receives right-justified data. At the rising edge of CS, the right-most (last) bits are evaluated as a frame. Extra clock cycles (exceeding frame length) during the frame begin to output on SDO the SDI data delayed by one frame length.CSA read operation is started when R/W bit is 1. The data word input for SDI is ignored in the read command frame. Send the subsequent read or write command frame into SDI to clock out the data of the addressed register on SDO. If no other read or write commands are needed, then issue a NOP command to retrieve the requested data. The read register value is output most significant bit first on SDO on successive edges (rising or falling based on CONFIG.FSDO setting) of SCLK.A write operation starts when R/W bit is 0. The SDO output to a write command, delivered in the next frame, contains status bits, data described in , and if the CRC is enabled, an 8-bit CRC for the output frame. Command Functions COMMAND BIT SDI INPUT DATA WORD SDO RESPONSE DATA WORD Write (R/W = 0) Data to be written (16b) 0x0000 Read (R/W = 1) Ignored Register output data (16b) Command Functions COMMAND BIT SDI INPUT DATA WORD SDO RESPONSE DATA WORD Write (R/W = 0) Data to be written (16b) 0x0000 Read (R/W = 1) Ignored Register output data (16b) COMMAND BIT SDI INPUT DATA WORD SDO RESPONSE DATA WORD COMMAND BIT SDI INPUT DATA WORD SDO RESPONSE DATA WORD COMMAND BITSDI INPUT DATA WORDSDO RESPONSE DATA WORD Write (R/W = 0) Data to be written (16b) 0x0000 Read (R/W = 1) Ignored Register output data (16b) Write (R/W = 0) Data to be written (16b) 0x0000 Write (R/W = 0)Data to be written (16b)0x0000 Read (R/W = 1) Ignored Register output data (16b) Read (R/W = 1)Ignored Register output data (16b) Response data portion in next frame output. The input bits are included in the calculation for CRC, if enabled (see ). Response data portion in next frame output.The input bits are included in the calculation for CRC, if enabled (see ).Valid SDO output is driven only when CS = 0 and CONFIG.DSDO = 0; otherwise, the SDO pin remains Hi-Z to save power. The SDO data bits are left-justified within the frame, meaning the most significant bit is produced on the line (subject to timing details) when CS is asserted low (bit is driven by falling edge of CS). The subsequent bits in the frame are driven by the rising SCLK edge when CONFIG.FSDO = 0 (default). To drive the SDO data on the falling edge of SCLK, set CONFIG.FSDO = 1. This setting effectively gives the SDO data an additional ½ clock period for setup time, but at the expense of hold time.CSCSCSThe frame output on SDO contains the command bit of the input that generated the frame (previous input frame), followed by seven status bits (see ). When an input frame CRC error is detected, the status bit CRC_ERR = 1. If there is no input frame CRC error, then CRC_ERR = 0. See for details. Frame Error Checking If the AFEx82H1 are used in a noisy environment, use the CRC to check the integrity of the SPI data communication between the device and the system controller. This feature is enabled by default and is controlled by the CONFIG.CRC_EN bit. If the CRC is not required in the system, disable frame error checking through the CRC_EN bit, and switch from the default 32-bit frame to the 24-bit frame. Frame error checking is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (9'b100000111). For the output register readback, the AFEx82H1 supply the calculated 8-bit CRC for the 24 bits of data provided, as part of the 32-bit frame. The AFEx82H1 decodes 24-bits of the input frame data and the 8-bit CRC to compute the CRC remainder. If no error exists in the frame, the CRC remainder is zero. When the remainder is nonzero (that is, the input frame has single-bit or multiple-bit errors) the ALARM_STATUS.CRC_ERR_CNT bits are incremented. A bad CRC value prevents execution of commands to the device, which prevents FIFO data from being lost as a result of an invalid read command. When the CRC error counter reaches the limit programmed in CONFIG.CRC_ERR_CNT, the CRC_FLT status bit is set in the ALARM_STATUS register. The fault is reported (as long as the corresponding mask is not set) as an ALARM_IRQ on SDO during the next frame. The ALARM pin asserts low if enabled by the alarm action configuration (see ). The CRC_ERR status bit (see ) in the SDO frame is not sticky and is only reported for the previous frame. The ALARM_STATUS.CRC_FLT bit is sticky and is only cleared after a successful read of the ALARM_STATUS register. Read the GEN_STATUS, MODEM_STATUS or ALARM_STATUS registers to clear any sticky bits that are set. The sticky status bits are cleared at the start of the readback frame and are latched again at the end of the readback frame. Therefore, if the fault condition previously reported in the status register is no longer present at the end of the readback frame, and the data are received by the microcontroller with the CRC error, the fault information is lost. If a robust monitoring of the status bits is required in a noisy environment, use the IRQ pin in combination with the status mask bits to find out the status of each fault before clearing the status bits. Set the CONFIG.IRQ_LVL bit to monitor the signal level on the IRQ pin, and unmask each status bit one at a time to retrieve the information from the status registers. Frame Error Checking If the AFEx82H1 are used in a noisy environment, use the CRC to check the integrity of the SPI data communication between the device and the system controller. This feature is enabled by default and is controlled by the CONFIG.CRC_EN bit. If the CRC is not required in the system, disable frame error checking through the CRC_EN bit, and switch from the default 32-bit frame to the 24-bit frame. Frame error checking is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (9'b100000111). For the output register readback, the AFEx82H1 supply the calculated 8-bit CRC for the 24 bits of data provided, as part of the 32-bit frame. The AFEx82H1 decodes 24-bits of the input frame data and the 8-bit CRC to compute the CRC remainder. If no error exists in the frame, the CRC remainder is zero. When the remainder is nonzero (that is, the input frame has single-bit or multiple-bit errors) the ALARM_STATUS.CRC_ERR_CNT bits are incremented. A bad CRC value prevents execution of commands to the device, which prevents FIFO data from being lost as a result of an invalid read command. When the CRC error counter reaches the limit programmed in CONFIG.CRC_ERR_CNT, the CRC_FLT status bit is set in the ALARM_STATUS register. The fault is reported (as long as the corresponding mask is not set) as an ALARM_IRQ on SDO during the next frame. The ALARM pin asserts low if enabled by the alarm action configuration (see ). The CRC_ERR status bit (see ) in the SDO frame is not sticky and is only reported for the previous frame. The ALARM_STATUS.CRC_FLT bit is sticky and is only cleared after a successful read of the ALARM_STATUS register. Read the GEN_STATUS, MODEM_STATUS or ALARM_STATUS registers to clear any sticky bits that are set. The sticky status bits are cleared at the start of the readback frame and are latched again at the end of the readback frame. Therefore, if the fault condition previously reported in the status register is no longer present at the end of the readback frame, and the data are received by the microcontroller with the CRC error, the fault information is lost. If a robust monitoring of the status bits is required in a noisy environment, use the IRQ pin in combination with the status mask bits to find out the status of each fault before clearing the status bits. Set the CONFIG.IRQ_LVL bit to monitor the signal level on the IRQ pin, and unmask each status bit one at a time to retrieve the information from the status registers. If the AFEx82H1 are used in a noisy environment, use the CRC to check the integrity of the SPI data communication between the device and the system controller. This feature is enabled by default and is controlled by the CONFIG.CRC_EN bit. If the CRC is not required in the system, disable frame error checking through the CRC_EN bit, and switch from the default 32-bit frame to the 24-bit frame. Frame error checking is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (9'b100000111). For the output register readback, the AFEx82H1 supply the calculated 8-bit CRC for the 24 bits of data provided, as part of the 32-bit frame. The AFEx82H1 decodes 24-bits of the input frame data and the 8-bit CRC to compute the CRC remainder. If no error exists in the frame, the CRC remainder is zero. When the remainder is nonzero (that is, the input frame has single-bit or multiple-bit errors) the ALARM_STATUS.CRC_ERR_CNT bits are incremented. A bad CRC value prevents execution of commands to the device, which prevents FIFO data from being lost as a result of an invalid read command. When the CRC error counter reaches the limit programmed in CONFIG.CRC_ERR_CNT, the CRC_FLT status bit is set in the ALARM_STATUS register. The fault is reported (as long as the corresponding mask is not set) as an ALARM_IRQ on SDO during the next frame. The ALARM pin asserts low if enabled by the alarm action configuration (see ). The CRC_ERR status bit (see ) in the SDO frame is not sticky and is only reported for the previous frame. The ALARM_STATUS.CRC_FLT bit is sticky and is only cleared after a successful read of the ALARM_STATUS register. Read the GEN_STATUS, MODEM_STATUS or ALARM_STATUS registers to clear any sticky bits that are set. The sticky status bits are cleared at the start of the readback frame and are latched again at the end of the readback frame. Therefore, if the fault condition previously reported in the status register is no longer present at the end of the readback frame, and the data are received by the microcontroller with the CRC error, the fault information is lost. If a robust monitoring of the status bits is required in a noisy environment, use the IRQ pin in combination with the status mask bits to find out the status of each fault before clearing the status bits. Set the CONFIG.IRQ_LVL bit to monitor the signal level on the IRQ pin, and unmask each status bit one at a time to retrieve the information from the status registers. If the AFEx82H1 are used in a noisy environment, use the CRC to check the integrity of the SPI data communication between the device and the system controller. This feature is enabled by default and is controlled by the CONFIG.CRC_EN bit. If the CRC is not required in the system, disable frame error checking through the CRC_EN bit, and switch from the default 32-bit frame to the 24-bit frame. AFEx82H1Frame error checking is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (9'b100000111). x8 + x2 + x + 1829'b100000111For the output register readback, the AFEx82H1 supply the calculated 8-bit CRC for the 24 bits of data provided, as part of the 32-bit frame.AFEx82H1The AFEx82H1 decodes 24-bits of the input frame data and the 8-bit CRC to compute the CRC remainder. If no error exists in the frame, the CRC remainder is zero. When the remainder is nonzero (that is, the input frame has single-bit or multiple-bit errors) the ALARM_STATUS.CRC_ERR_CNT bits are incremented. A bad CRC value prevents execution of commands to the device, which prevents FIFO data from being lost as a result of an invalid read command.AFEx82H1, which prevents FIFO data from being lost as a result of an invalid read commandWhen the CRC error counter reaches the limit programmed in CONFIG.CRC_ERR_CNT, the CRC_FLT status bit is set in the ALARM_STATUS register. The fault is reported (as long as the corresponding mask is not set) as an ALARM_IRQ on SDO during the next frame. The ALARM pin asserts low if enabled by the alarm action configuration (see ).ALARMThe CRC_ERR status bit (see ) in the SDO frame is not sticky and is only reported for the previous frame. The ALARM_STATUS.CRC_FLT bit is sticky and is only cleared after a successful read of the ALARM_STATUS register. Read the GEN_STATUS, MODEM_STATUS or ALARM_STATUS registers to clear any sticky bits that are set., MODEM_STATUSThe sticky status bits are cleared at the start of the readback frame and are latched again at the end of the readback frame. Therefore, if the fault condition previously reported in the status register is no longer present at the end of the readback frame, and the data are received by the microcontroller with the CRC error, the fault information is lost. If a robust monitoring of the status bits is required in a noisy environment, use the IRQ pin in combination with the status mask bits to find out the status of each fault before clearing the status bits. Set the CONFIG.IRQ_LVL bit to monitor the signal level on the IRQ pin, and unmask each status bit one at a time to retrieve the information from the status registers. Synchronization The AFEx82H1 register map runs on the internal clock domain. Both the SPI and UBM packets are synchronized to this domain. This synchronization adds a latency of 0.4 µs to 1.22 µs (1.5 internal clocks), with respect to the rising edge of CS or the STOP bit of the last byte of the UBM packet. The effect of clock synchronization on UBM communication is not evident because of the lower speed and asynchronous nature of UBM communication. In SPI mode, if changing register bits CONFIG.DSDO, CONFIG.FSDO, or CONFIG.CRC_EN, keep CS high for at least two clock cycles before issuing the next frame. Frame data corruption can occur if the two extra cycles are not used. The following are examples of frame corruption: Setting CONFIG.DSDO = 0: SDO begins to drive in the middle of the next frame. Changing CONFIG.FSDO: The launching edge of SDO changes in the middle of the next frame. Setting CONFIG.CRC_EN = 1: The next frame has a CRC error because the CRC is enabled in the middle of the frame. Send a NOP command (SDI = 0x00_0000) after setting the DSDO, FSDO, and CRC_EN bits to prevent the corrupted frames from impacting communication. Sending a NOP after CONFIG.CRC_EN is set still generates a CRC error, and is reported in the STATUS portion of SDO. To avoid false errors, wait approximately 2 µs after setting CONFIG.CRC_EN before sending the next frame. Synchronization The AFEx82H1 register map runs on the internal clock domain. Both the SPI and UBM packets are synchronized to this domain. This synchronization adds a latency of 0.4 µs to 1.22 µs (1.5 internal clocks), with respect to the rising edge of CS or the STOP bit of the last byte of the UBM packet. The effect of clock synchronization on UBM communication is not evident because of the lower speed and asynchronous nature of UBM communication. In SPI mode, if changing register bits CONFIG.DSDO, CONFIG.FSDO, or CONFIG.CRC_EN, keep CS high for at least two clock cycles before issuing the next frame. Frame data corruption can occur if the two extra cycles are not used. The following are examples of frame corruption: Setting CONFIG.DSDO = 0: SDO begins to drive in the middle of the next frame. Changing CONFIG.FSDO: The launching edge of SDO changes in the middle of the next frame. Setting CONFIG.CRC_EN = 1: The next frame has a CRC error because the CRC is enabled in the middle of the frame. Send a NOP command (SDI = 0x00_0000) after setting the DSDO, FSDO, and CRC_EN bits to prevent the corrupted frames from impacting communication. Sending a NOP after CONFIG.CRC_EN is set still generates a CRC error, and is reported in the STATUS portion of SDO. To avoid false errors, wait approximately 2 µs after setting CONFIG.CRC_EN before sending the next frame. The AFEx82H1 register map runs on the internal clock domain. Both the SPI and UBM packets are synchronized to this domain. This synchronization adds a latency of 0.4 µs to 1.22 µs (1.5 internal clocks), with respect to the rising edge of CS or the STOP bit of the last byte of the UBM packet. The effect of clock synchronization on UBM communication is not evident because of the lower speed and asynchronous nature of UBM communication. In SPI mode, if changing register bits CONFIG.DSDO, CONFIG.FSDO, or CONFIG.CRC_EN, keep CS high for at least two clock cycles before issuing the next frame. Frame data corruption can occur if the two extra cycles are not used. The following are examples of frame corruption: Setting CONFIG.DSDO = 0: SDO begins to drive in the middle of the next frame. Changing CONFIG.FSDO: The launching edge of SDO changes in the middle of the next frame. Setting CONFIG.CRC_EN = 1: The next frame has a CRC error because the CRC is enabled in the middle of the frame. Send a NOP command (SDI = 0x00_0000) after setting the DSDO, FSDO, and CRC_EN bits to prevent the corrupted frames from impacting communication. Sending a NOP after CONFIG.CRC_EN is set still generates a CRC error, and is reported in the STATUS portion of SDO. To avoid false errors, wait approximately 2 µs after setting CONFIG.CRC_EN before sending the next frame. The AFEx82H1 register map runs on the internal clock domain. Both the SPI and UBM packets are synchronized to this domain. This synchronization adds a latency of 0.4 µs to 1.22 µs (1.5 internal clocks), with respect to the rising edge of CS or the STOP bit of the last byte of the UBM packet. AFEx82H1CSThe effect of clock synchronization on UBM communication is not evident because of the lower speed and asynchronous nature of UBM communication. In SPI mode, if changing register bits CONFIG.DSDO, CONFIG.FSDO, or CONFIG.CRC_EN, keep CS high for at least two clock cycles before issuing the next frame. Frame data corruption can occur if the two extra cycles are not used. The following are examples of frame corruption: CS Setting CONFIG.DSDO = 0: SDO begins to drive in the middle of the next frame. Changing CONFIG.FSDO: The launching edge of SDO changes in the middle of the next frame. Setting CONFIG.CRC_EN = 1: The next frame has a CRC error because the CRC is enabled in the middle of the frame. Setting CONFIG.DSDO = 0: SDO begins to drive in the middle of the next frame.Changing CONFIG.FSDO: The launching edge of SDO changes in the middle of the next frame.Setting CONFIG.CRC_EN = 1: The next frame has a CRC error because the CRC is enabled in the middle of the frame.Send a NOP command (SDI = 0x00_0000) after setting the DSDO, FSDO, and CRC_EN bits to prevent the corrupted frames from impacting communication. Sending a NOP after CONFIG.CRC_EN is set still generates a CRC error, and is reported in the STATUS portion of SDO. To avoid false errors, wait approximately 2 µs after setting CONFIG.CRC_EN before sending the next frame. UART Interface In UART mode, the device expects 1 start bit, 8 data bits, 1 odd parity bit, and 1 stop bit, or an 8O1 UART character format. When using SPI to communicate with the registers, and only using UART for HART communication, use 1200 baud. The baud must have ±1% accuracy. UART Break Mode (UBM) In UART break mode (UBM), the microcontroller issues a UART break to start communication. The device interprets the UART break as the start to receive commands from the UART. A communication UART character consists of one start bit, eight data bits, one odd parity bit, and at least one stop bit. A UART break character is all 11 bits (including start, data, parity and stop bit) held low by the microcontroller on the UARTIN pin and by the AFEx82H1 on the UARTOUT pin. When a valid break character is detected on UARTIN by the AFEx82H1, no parity (even though parity is odd) or stop bit errors are flagged for this character. The parity and stop bit differences between valid UBM break and communication characters must be managed by the system microcontroller when receiving these characters from the UARTOUT pin of the AFEx82H1. See for UBM break character, communication timing details, and bit order. Two baud rates are supported for UART communication: 9600 and 1200. The 9600 baud rate is default for UBM. The 1200 baud rate is supported to maintain backward compatibility and requires the use of SPI to communicate with the register map; whereas, the UART pins are used only for HART communication. The baud rates are selected by register bit CONFIG.UART_BAUD. When CONFIG.UART_BAUD = 1 (default), the UART operates at 9600 baud. When CONFIG.UART_BAUD = 0, the UART operates at 1200 baud. The break function of the UART protocol is enabled only for 9600 baud. This configuration allows interleaving of HART data with register communication and enables the access to all registers of the device, when configured correctly. Set UBM.REG_MODE = 1 to enable register map access through the UART. By default, this bit is set to 0. The entire register map can only be accessed with SPI, except for the UBM register. The UBM register can only be accessed with UBM. After UBM.REG_MODE is set to 1, the SPI does not have access to the register map, and the full register map is accessible by UBM. A UBM data output packet is initiated by AFEx82H1 on UARTOUT in two cases. See for packet structure details. If the R/IRQn status bit is 0 an IRQ event initiated the break command. If the R/IRQn status bit is 1, the break command is a response to the prior read request. For details on HART data see . To enable IRQ events, set CONFIG.UBM_IRQ_EN = 1. When IRQ is enabled, the AFEx82H1 triggers a break command followed by data on UARTOUT (see ). The contents of the data are listed in order of priority below. If ALARM_IRQ bit is set, then the contents of the ALARM_STATUS register are output. If GEN_IRQ is set, then the contents of the GEN_STATUS register are output. If MODEM_IRQ bit is set, then the contents of the MODEM_STATUS register are output. If none of the previous bits are set, then an IRQ is not generated. A break byte is followed by three bytes. These three bytes have information identical to the SPI frame without the CRC (see ). The CRC cannot be enabled for UBM. All communication characters on the UART bus are transmitted least significant data bit (D0) first. shows the data structure of the UBM write command, and shows the data structure of the UBM read command. UARTIN Break Write Data Format UARTIN Break Read Data Format shows the UARTOUT data frame with details of the status bits produced by the AFEx82H1. See for details. UARTOUT Break Data Format Interface With FIFO Buffers and Register Map In UBM, the HART data characters are interleaved with break commands for register map access or interrupt reporting. The device reports parity and frame errors received on UARTIN. These status bits can be found in the GEN_STATUS register and are maskable to create IRQ events. Avoid the large gaps between the HART bytes. The HART standard has a gap specification of 11 bit times (11 × tBAUDHART ms); therefore, gaps longer than 10.5 HART bit times (10.5 × tBAUDHART ms) can cause a gap error in the HART modem. The following timing diagrams illustrate examples of microcontroller communication with the device registers, as well as HART transmit and receive data transfers. Interleaved HART Transmit With UBM Register Writes Packed HART Transmit With UBM Register Writes Interleaved HART Transmit With UBM Register Read Requests and Responses Packed HART Transmit With UBM Register Write and Read Requests and Responses Interleaved HART Receive With UBM Register Write and Read Requests and Responses UART Interface In UART mode, the device expects 1 start bit, 8 data bits, 1 odd parity bit, and 1 stop bit, or an 8O1 UART character format. When using SPI to communicate with the registers, and only using UART for HART communication, use 1200 baud. The baud must have ±1% accuracy. In UART mode, the device expects 1 start bit, 8 data bits, 1 odd parity bit, and 1 stop bit, or an 8O1 UART character format. When using SPI to communicate with the registers, and only using UART for HART communication, use 1200 baud. The baud must have ±1% accuracy. In UART mode, the device expects 1 start bit, 8 data bits, 1 odd parity bit, and 1 stop bit, or an 8O1 UART character format. When using SPI to communicate with the registers, and only using UART for HART communication, use 1200 baud. The baud must have ±1% accuracy. UART Break Mode (UBM) In UART break mode (UBM), the microcontroller issues a UART break to start communication. The device interprets the UART break as the start to receive commands from the UART. A communication UART character consists of one start bit, eight data bits, one odd parity bit, and at least one stop bit. A UART break character is all 11 bits (including start, data, parity and stop bit) held low by the microcontroller on the UARTIN pin and by the AFEx82H1 on the UARTOUT pin. When a valid break character is detected on UARTIN by the AFEx82H1, no parity (even though parity is odd) or stop bit errors are flagged for this character. The parity and stop bit differences between valid UBM break and communication characters must be managed by the system microcontroller when receiving these characters from the UARTOUT pin of the AFEx82H1. See for UBM break character, communication timing details, and bit order. Two baud rates are supported for UART communication: 9600 and 1200. The 9600 baud rate is default for UBM. The 1200 baud rate is supported to maintain backward compatibility and requires the use of SPI to communicate with the register map; whereas, the UART pins are used only for HART communication. The baud rates are selected by register bit CONFIG.UART_BAUD. When CONFIG.UART_BAUD = 1 (default), the UART operates at 9600 baud. When CONFIG.UART_BAUD = 0, the UART operates at 1200 baud. The break function of the UART protocol is enabled only for 9600 baud. This configuration allows interleaving of HART data with register communication and enables the access to all registers of the device, when configured correctly. Set UBM.REG_MODE = 1 to enable register map access through the UART. By default, this bit is set to 0. The entire register map can only be accessed with SPI, except for the UBM register. The UBM register can only be accessed with UBM. After UBM.REG_MODE is set to 1, the SPI does not have access to the register map, and the full register map is accessible by UBM. A UBM data output packet is initiated by AFEx82H1 on UARTOUT in two cases. See for packet structure details. If the R/IRQn status bit is 0 an IRQ event initiated the break command. If the R/IRQn status bit is 1, the break command is a response to the prior read request. For details on HART data see . To enable IRQ events, set CONFIG.UBM_IRQ_EN = 1. When IRQ is enabled, the AFEx82H1 triggers a break command followed by data on UARTOUT (see ). The contents of the data are listed in order of priority below. If ALARM_IRQ bit is set, then the contents of the ALARM_STATUS register are output. If GEN_IRQ is set, then the contents of the GEN_STATUS register are output. If MODEM_IRQ bit is set, then the contents of the MODEM_STATUS register are output. If none of the previous bits are set, then an IRQ is not generated. A break byte is followed by three bytes. These three bytes have information identical to the SPI frame without the CRC (see ). The CRC cannot be enabled for UBM. All communication characters on the UART bus are transmitted least significant data bit (D0) first. shows the data structure of the UBM write command, and shows the data structure of the UBM read command. UARTIN Break Write Data Format UARTIN Break Read Data Format shows the UARTOUT data frame with details of the status bits produced by the AFEx82H1. See for details. UARTOUT Break Data Format Interface With FIFO Buffers and Register Map In UBM, the HART data characters are interleaved with break commands for register map access or interrupt reporting. The device reports parity and frame errors received on UARTIN. These status bits can be found in the GEN_STATUS register and are maskable to create IRQ events. Avoid the large gaps between the HART bytes. The HART standard has a gap specification of 11 bit times (11 × tBAUDHART ms); therefore, gaps longer than 10.5 HART bit times (10.5 × tBAUDHART ms) can cause a gap error in the HART modem. The following timing diagrams illustrate examples of microcontroller communication with the device registers, as well as HART transmit and receive data transfers. Interleaved HART Transmit With UBM Register Writes Packed HART Transmit With UBM Register Writes Interleaved HART Transmit With UBM Register Read Requests and Responses Packed HART Transmit With UBM Register Write and Read Requests and Responses Interleaved HART Receive With UBM Register Write and Read Requests and Responses UART Break Mode (UBM) In UART break mode (UBM), the microcontroller issues a UART break to start communication. The device interprets the UART break as the start to receive commands from the UART. A communication UART character consists of one start bit, eight data bits, one odd parity bit, and at least one stop bit. A UART break character is all 11 bits (including start, data, parity and stop bit) held low by the microcontroller on the UARTIN pin and by the AFEx82H1 on the UARTOUT pin. When a valid break character is detected on UARTIN by the AFEx82H1, no parity (even though parity is odd) or stop bit errors are flagged for this character. The parity and stop bit differences between valid UBM break and communication characters must be managed by the system microcontroller when receiving these characters from the UARTOUT pin of the AFEx82H1. See for UBM break character, communication timing details, and bit order. Two baud rates are supported for UART communication: 9600 and 1200. The 9600 baud rate is default for UBM. The 1200 baud rate is supported to maintain backward compatibility and requires the use of SPI to communicate with the register map; whereas, the UART pins are used only for HART communication. The baud rates are selected by register bit CONFIG.UART_BAUD. When CONFIG.UART_BAUD = 1 (default), the UART operates at 9600 baud. When CONFIG.UART_BAUD = 0, the UART operates at 1200 baud. The break function of the UART protocol is enabled only for 9600 baud. This configuration allows interleaving of HART data with register communication and enables the access to all registers of the device, when configured correctly. Set UBM.REG_MODE = 1 to enable register map access through the UART. By default, this bit is set to 0. The entire register map can only be accessed with SPI, except for the UBM register. The UBM register can only be accessed with UBM. After UBM.REG_MODE is set to 1, the SPI does not have access to the register map, and the full register map is accessible by UBM. A UBM data output packet is initiated by AFEx82H1 on UARTOUT in two cases. See for packet structure details. If the R/IRQn status bit is 0 an IRQ event initiated the break command. If the R/IRQn status bit is 1, the break command is a response to the prior read request. For details on HART data see . To enable IRQ events, set CONFIG.UBM_IRQ_EN = 1. When IRQ is enabled, the AFEx82H1 triggers a break command followed by data on UARTOUT (see ). The contents of the data are listed in order of priority below. If ALARM_IRQ bit is set, then the contents of the ALARM_STATUS register are output. If GEN_IRQ is set, then the contents of the GEN_STATUS register are output. If MODEM_IRQ bit is set, then the contents of the MODEM_STATUS register are output. If none of the previous bits are set, then an IRQ is not generated. A break byte is followed by three bytes. These three bytes have information identical to the SPI frame without the CRC (see ). The CRC cannot be enabled for UBM. All communication characters on the UART bus are transmitted least significant data bit (D0) first. shows the data structure of the UBM write command, and shows the data structure of the UBM read command. UARTIN Break Write Data Format UARTIN Break Read Data Format shows the UARTOUT data frame with details of the status bits produced by the AFEx82H1. See for details. UARTOUT Break Data Format In UART break mode (UBM), the microcontroller issues a UART break to start communication. The device interprets the UART break as the start to receive commands from the UART. A communication UART character consists of one start bit, eight data bits, one odd parity bit, and at least one stop bit. A UART break character is all 11 bits (including start, data, parity and stop bit) held low by the microcontroller on the UARTIN pin and by the AFEx82H1 on the UARTOUT pin. When a valid break character is detected on UARTIN by the AFEx82H1, no parity (even though parity is odd) or stop bit errors are flagged for this character. The parity and stop bit differences between valid UBM break and communication characters must be managed by the system microcontroller when receiving these characters from the UARTOUT pin of the AFEx82H1. See for UBM break character, communication timing details, and bit order. Two baud rates are supported for UART communication: 9600 and 1200. The 9600 baud rate is default for UBM. The 1200 baud rate is supported to maintain backward compatibility and requires the use of SPI to communicate with the register map; whereas, the UART pins are used only for HART communication. The baud rates are selected by register bit CONFIG.UART_BAUD. When CONFIG.UART_BAUD = 1 (default), the UART operates at 9600 baud. When CONFIG.UART_BAUD = 0, the UART operates at 1200 baud. The break function of the UART protocol is enabled only for 9600 baud. This configuration allows interleaving of HART data with register communication and enables the access to all registers of the device, when configured correctly. Set UBM.REG_MODE = 1 to enable register map access through the UART. By default, this bit is set to 0. The entire register map can only be accessed with SPI, except for the UBM register. The UBM register can only be accessed with UBM. After UBM.REG_MODE is set to 1, the SPI does not have access to the register map, and the full register map is accessible by UBM. A UBM data output packet is initiated by AFEx82H1 on UARTOUT in two cases. See for packet structure details. If the R/IRQn status bit is 0 an IRQ event initiated the break command. If the R/IRQn status bit is 1, the break command is a response to the prior read request. For details on HART data see . To enable IRQ events, set CONFIG.UBM_IRQ_EN = 1. When IRQ is enabled, the AFEx82H1 triggers a break command followed by data on UARTOUT (see ). The contents of the data are listed in order of priority below. If ALARM_IRQ bit is set, then the contents of the ALARM_STATUS register are output. If GEN_IRQ is set, then the contents of the GEN_STATUS register are output. If MODEM_IRQ bit is set, then the contents of the MODEM_STATUS register are output. If none of the previous bits are set, then an IRQ is not generated. A break byte is followed by three bytes. These three bytes have information identical to the SPI frame without the CRC (see ). The CRC cannot be enabled for UBM. All communication characters on the UART bus are transmitted least significant data bit (D0) first. shows the data structure of the UBM write command, and shows the data structure of the UBM read command. UARTIN Break Write Data Format UARTIN Break Read Data Format shows the UARTOUT data frame with details of the status bits produced by the AFEx82H1. See for details. UARTOUT Break Data Format In UART break mode (UBM), the microcontroller issues a UART break to start communication. The device interprets the UART break as the start to receive commands from the UART. A communication UART character consists of one start bit, eight data bits, one odd parity bit, and at least one stop bit. A UART break character is all 11 bits (including start, data, parity and stop bit) held low by the microcontroller on the UARTIN pin and by the AFEx82H1 on the UARTOUT pin. When a valid break character is detected on UARTIN by the AFEx82H1, no parity (even though parity is odd) or stop bit errors are flagged for this character. The parity and stop bit differences between valid UBM break and communication characters must be managed by the system microcontroller when receiving these characters from the UARTOUT pin of the AFEx82H1. See for UBM break character, communication timing details, and bit order. AFEx82H1AFEx82H1AFEx82H1Two baud rates are supported for UART communication: 9600 and 1200. The 9600 baud rate is default for UBM. The 1200 baud rate is supported to maintain backward compatibility and requires the use of SPI to communicate with the register map; whereas, the UART pins are used only for HART communication. The baud rates are selected by register bit CONFIG.UART_BAUD. When CONFIG.UART_BAUD = 1 (default), the UART operates at 9600 baud. When CONFIG.UART_BAUD = 0, the UART operates at 1200 baud. The break function of the UART protocol is enabled only for 9600 baud. This configuration allows interleaving of HART data with register communication and enables the access to all registers of the device, when configured correctly.Set UBM.REG_MODE = 1 to enable register map access through the UART. By default, this bit is set to 0. The entire register map can only be accessed with SPI, except for the UBM register. The UBM register can only be accessed with UBM. After UBM.REG_MODE is set to 1, the SPI does not have access to the register map, and the full register map is accessible by UBM.A UBM data output packet is initiated by AFEx82H1 on UARTOUT in two cases. See for packet structure details. If the R/IRQn status bit is 0 an IRQ event initiated the break command. If the R/IRQn status bit is 1, the break command is a response to the prior read request. For details on HART data see . AFEx82H1For details on HART data see .To enable IRQ events, set CONFIG.UBM_IRQ_EN = 1. When IRQ is enabled, the AFEx82H1 triggers a break command followed by data on UARTOUT (see ). AFEx82H1The contents of the data are listed in order of priority below. If ALARM_IRQ bit is set, then the contents of the ALARM_STATUS register are output. If GEN_IRQ is set, then the contents of the GEN_STATUS register are output. If MODEM_IRQ bit is set, then the contents of the MODEM_STATUS register are output. If none of the previous bits are set, then an IRQ is not generated. If ALARM_IRQ bit is set, then the contents of the ALARM_STATUS register are output. If GEN_IRQ is set, then the contents of the GEN_STATUS register are output.If MODEM_IRQ bit is set, then the contents of the MODEM_STATUS register are output.If none of the previous bits are set, then an IRQ is not generated.A break byte is followed by three bytes. These three bytes have information identical to the SPI frame without the CRC (see ). The CRC cannot be enabled for UBM. All communication characters on the UART bus are transmitted least significant data bit (D0) first. shows the data structure of the UBM write command, and shows the data structure of the UBM read command. UARTIN Break Write Data Format UARTIN Break Write Data Format UARTIN Break Read Data Format UARTIN Break Read Data Format shows the UARTOUT data frame with details of the status bits produced by the AFEx82H1. See for details. AFEx82H1 UARTOUT Break Data Format UARTOUT Break Data Format Interface With FIFO Buffers and Register Map In UBM, the HART data characters are interleaved with break commands for register map access or interrupt reporting. The device reports parity and frame errors received on UARTIN. These status bits can be found in the GEN_STATUS register and are maskable to create IRQ events. Avoid the large gaps between the HART bytes. The HART standard has a gap specification of 11 bit times (11 × tBAUDHART ms); therefore, gaps longer than 10.5 HART bit times (10.5 × tBAUDHART ms) can cause a gap error in the HART modem. The following timing diagrams illustrate examples of microcontroller communication with the device registers, as well as HART transmit and receive data transfers. Interleaved HART Transmit With UBM Register Writes Packed HART Transmit With UBM Register Writes Interleaved HART Transmit With UBM Register Read Requests and Responses Packed HART Transmit With UBM Register Write and Read Requests and Responses Interleaved HART Receive With UBM Register Write and Read Requests and Responses Interface With FIFO Buffers and Register Map In UBM, the HART data characters are interleaved with break commands for register map access or interrupt reporting. The device reports parity and frame errors received on UARTIN. These status bits can be found in the GEN_STATUS register and are maskable to create IRQ events. Avoid the large gaps between the HART bytes. The HART standard has a gap specification of 11 bit times (11 × tBAUDHART ms); therefore, gaps longer than 10.5 HART bit times (10.5 × tBAUDHART ms) can cause a gap error in the HART modem. The following timing diagrams illustrate examples of microcontroller communication with the device registers, as well as HART transmit and receive data transfers. Interleaved HART Transmit With UBM Register Writes Packed HART Transmit With UBM Register Writes Interleaved HART Transmit With UBM Register Read Requests and Responses Packed HART Transmit With UBM Register Write and Read Requests and Responses Interleaved HART Receive With UBM Register Write and Read Requests and Responses In UBM, the HART data characters are interleaved with break commands for register map access or interrupt reporting. The device reports parity and frame errors received on UARTIN. These status bits can be found in the GEN_STATUS register and are maskable to create IRQ events. Avoid the large gaps between the HART bytes. The HART standard has a gap specification of 11 bit times (11 × tBAUDHART ms); therefore, gaps longer than 10.5 HART bit times (10.5 × tBAUDHART ms) can cause a gap error in the HART modem. The following timing diagrams illustrate examples of microcontroller communication with the device registers, as well as HART transmit and receive data transfers. Interleaved HART Transmit With UBM Register Writes Packed HART Transmit With UBM Register Writes Interleaved HART Transmit With UBM Register Read Requests and Responses Packed HART Transmit With UBM Register Write and Read Requests and Responses Interleaved HART Receive With UBM Register Write and Read Requests and Responses In UBM, the HART data characters are interleaved with break commands for register map access or interrupt reporting.The device reports parity and frame errors received on UARTIN. These status bits can be found in the GEN_STATUS register and are maskable to create IRQ events. Avoid the large gaps between the HART bytes. The HART standard has a gap specification of 11 bit times (11 × tBAUDHART ms); therefore, gaps longer than 10.5 HART bit times (10.5 × tBAUDHART ms) can cause a gap error in the HART modem.BAUDHARTBAUDHARTThe following timing diagrams illustrate examples of microcontroller communication with the device registers, as well as HART transmit and receive data transfers. Interleaved HART Transmit With UBM Register Writes Interleaved HART Transmit With UBM Register Writes Packed HART Transmit With UBM Register Writes Packed HART Transmit With UBM Register Writes Interleaved HART Transmit With UBM Register Read Requests and Responses Interleaved HART Transmit With UBM Register Read Requests and Responses Packed HART Transmit With UBM Register Write and Read Requests and Responses Packed HART Transmit With UBM Register Write and Read Requests and Responses Interleaved HART Receive With UBM Register Write and Read Requests and Responses Interleaved HART Receive With UBM Register Write and Read Requests and Responses Status Bits In SPI mode and UBM, every response from the AFEx82H1 includes a set of status bits. For SPI mode bit order, see . For UBM bit order, . Status Bits STATUS BIT DESCRIPTION NOTES / REFERENCE ALARM_IRQ 1h = ALARM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . CRC_ERR(CRC enabled SPI only) 1h = CRC error detect in input frame 0h = No CRC error detected Generated by the SPI on a frame by frame basis. See . GEN_IRQ 1h = GEN_IRQ asserted 0h = Normal Operation From the ALARM_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . MODEM_IRQ 1h = MODEM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . OSC_DIV_1024 (UBM mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 1024) sampled at the falling edge of the status byte start bit. See also . OSC_DIV_2 (SPI mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 2) sampled at CS falling edge. See also . R/IRQn (UBM only) 1h = Read request 0h = IRQ event Generated by the UART interface on a frame by frame basis. See for details. RBIST 1h = RBIST busy (registers not readable) 0h = RBIST done (registers readable) RBIST running status. See for details. RESET 1h = First readback after RESET0h = All other readbacks From the GEN_STATUS register (). See also . ALARM_STATUS, MODEM_STATUS, and GEN_STATUS registers contain cross-readable IRQ flags for the other registers. The ALARM_STATUS register has the GEN_IRQ and MODEM_IRQ bits. MODEM_STATUS has the GEN_IRQ and ALARM_IRQ bits. GEN_STATUS has the ALARM_IRQ and MODEM_IRQ bits. This functionality enables the system microcontroller to always get full status information by reading only one register, and thus save power. Status Bits In SPI mode and UBM, every response from the AFEx82H1 includes a set of status bits. For SPI mode bit order, see . For UBM bit order, . Status Bits STATUS BIT DESCRIPTION NOTES / REFERENCE ALARM_IRQ 1h = ALARM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . CRC_ERR(CRC enabled SPI only) 1h = CRC error detect in input frame 0h = No CRC error detected Generated by the SPI on a frame by frame basis. See . GEN_IRQ 1h = GEN_IRQ asserted 0h = Normal Operation From the ALARM_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . MODEM_IRQ 1h = MODEM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . OSC_DIV_1024 (UBM mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 1024) sampled at the falling edge of the status byte start bit. See also . OSC_DIV_2 (SPI mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 2) sampled at CS falling edge. See also . R/IRQn (UBM only) 1h = Read request 0h = IRQ event Generated by the UART interface on a frame by frame basis. See for details. RBIST 1h = RBIST busy (registers not readable) 0h = RBIST done (registers readable) RBIST running status. See for details. RESET 1h = First readback after RESET0h = All other readbacks From the GEN_STATUS register (). See also . ALARM_STATUS, MODEM_STATUS, and GEN_STATUS registers contain cross-readable IRQ flags for the other registers. The ALARM_STATUS register has the GEN_IRQ and MODEM_IRQ bits. MODEM_STATUS has the GEN_IRQ and ALARM_IRQ bits. GEN_STATUS has the ALARM_IRQ and MODEM_IRQ bits. This functionality enables the system microcontroller to always get full status information by reading only one register, and thus save power. In SPI mode and UBM, every response from the AFEx82H1 includes a set of status bits. For SPI mode bit order, see . For UBM bit order, . Status Bits STATUS BIT DESCRIPTION NOTES / REFERENCE ALARM_IRQ 1h = ALARM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . CRC_ERR(CRC enabled SPI only) 1h = CRC error detect in input frame 0h = No CRC error detected Generated by the SPI on a frame by frame basis. See . GEN_IRQ 1h = GEN_IRQ asserted 0h = Normal Operation From the ALARM_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . MODEM_IRQ 1h = MODEM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . OSC_DIV_1024 (UBM mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 1024) sampled at the falling edge of the status byte start bit. See also . OSC_DIV_2 (SPI mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 2) sampled at CS falling edge. See also . R/IRQn (UBM only) 1h = Read request 0h = IRQ event Generated by the UART interface on a frame by frame basis. See for details. RBIST 1h = RBIST busy (registers not readable) 0h = RBIST done (registers readable) RBIST running status. See for details. RESET 1h = First readback after RESET0h = All other readbacks From the GEN_STATUS register (). See also . ALARM_STATUS, MODEM_STATUS, and GEN_STATUS registers contain cross-readable IRQ flags for the other registers. The ALARM_STATUS register has the GEN_IRQ and MODEM_IRQ bits. MODEM_STATUS has the GEN_IRQ and ALARM_IRQ bits. GEN_STATUS has the ALARM_IRQ and MODEM_IRQ bits. This functionality enables the system microcontroller to always get full status information by reading only one register, and thus save power. In SPI mode and UBM, every response from the AFEx82H1 includes a set of status bits. For SPI mode bit order, see . For UBM bit order, .AFEx82H1 Status Bits STATUS BIT DESCRIPTION NOTES / REFERENCE ALARM_IRQ 1h = ALARM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . CRC_ERR(CRC enabled SPI only) 1h = CRC error detect in input frame 0h = No CRC error detected Generated by the SPI on a frame by frame basis. See . GEN_IRQ 1h = GEN_IRQ asserted 0h = Normal Operation From the ALARM_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . MODEM_IRQ 1h = MODEM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . OSC_DIV_1024 (UBM mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 1024) sampled at the falling edge of the status byte start bit. See also . OSC_DIV_2 (SPI mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 2) sampled at CS falling edge. See also . R/IRQn (UBM only) 1h = Read request 0h = IRQ event Generated by the UART interface on a frame by frame basis. See for details. RBIST 1h = RBIST busy (registers not readable) 0h = RBIST done (registers readable) RBIST running status. See for details. RESET 1h = First readback after RESET0h = All other readbacks From the GEN_STATUS register (). See also . Status Bits STATUS BIT DESCRIPTION NOTES / REFERENCE ALARM_IRQ 1h = ALARM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . CRC_ERR(CRC enabled SPI only) 1h = CRC error detect in input frame 0h = No CRC error detected Generated by the SPI on a frame by frame basis. See . GEN_IRQ 1h = GEN_IRQ asserted 0h = Normal Operation From the ALARM_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . MODEM_IRQ 1h = MODEM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . OSC_DIV_1024 (UBM mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 1024) sampled at the falling edge of the status byte start bit. See also . OSC_DIV_2 (SPI mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 2) sampled at CS falling edge. See also . R/IRQn (UBM only) 1h = Read request 0h = IRQ event Generated by the UART interface on a frame by frame basis. See for details. RBIST 1h = RBIST busy (registers not readable) 0h = RBIST done (registers readable) RBIST running status. See for details. RESET 1h = First readback after RESET0h = All other readbacks From the GEN_STATUS register (). See also . STATUS BIT DESCRIPTION NOTES / REFERENCE STATUS BIT DESCRIPTION NOTES / REFERENCE STATUS BITDESCRIPTIONNOTES / REFERENCE ALARM_IRQ 1h = ALARM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . CRC_ERR(CRC enabled SPI only) 1h = CRC error detect in input frame 0h = No CRC error detected Generated by the SPI on a frame by frame basis. See . GEN_IRQ 1h = GEN_IRQ asserted 0h = Normal Operation From the ALARM_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . MODEM_IRQ 1h = MODEM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . OSC_DIV_1024 (UBM mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 1024) sampled at the falling edge of the status byte start bit. See also . OSC_DIV_2 (SPI mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 2) sampled at CS falling edge. See also . R/IRQn (UBM only) 1h = Read request 0h = IRQ event Generated by the UART interface on a frame by frame basis. See for details. RBIST 1h = RBIST busy (registers not readable) 0h = RBIST done (registers readable) RBIST running status. See for details. RESET 1h = First readback after RESET0h = All other readbacks From the GEN_STATUS register (). See also . ALARM_IRQ 1h = ALARM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . ALARM_IRQ1h = ALARM_IRQ asserted 0h = Normal operationFrom the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also .#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B CRC_ERR(CRC enabled SPI only) 1h = CRC error detect in input frame 0h = No CRC error detected Generated by the SPI on a frame by frame basis. See . CRC_ERR(CRC enabled SPI only) 1h = CRC error detect in input frame 0h = No CRC error detected Generated by the SPI on a frame by frame basis. See . GEN_IRQ 1h = GEN_IRQ asserted 0h = Normal Operation From the ALARM_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . GEN_IRQ1h = GEN_IRQ asserted 0h = Normal OperationFrom the ALARM_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also .#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B MODEM_IRQ 1h = MODEM_IRQ asserted 0h = Normal operation From the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also . MODEM_IRQ1h = MODEM_IRQ asserted 0h = Normal operationFrom the GEN_STATUS#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B register (). See also .#GUID-363C029C-AA5A-4105-AA62-66FBDF8253D7/LI_T4K_3BX_P5B OSC_DIV_1024 (UBM mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 1024) sampled at the falling edge of the status byte start bit. See also . OSC_DIV_1024 (UBM mode) 1h = Sampled signal is high 0h = Sampled signal is low 1h = Sampled signal is high0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 1024) sampled at the falling edge of the status byte start bit. See also . OSC_DIV_2 (SPI mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 2) sampled at CS falling edge. See also . OSC_DIV_2 (SPI mode)1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 2) sampled at CS falling edge. See also .CS R/IRQn (UBM only) 1h = Read request 0h = IRQ event Generated by the UART interface on a frame by frame basis. See for details. R/IRQn (UBM only)1h = Read request 0h = IRQ eventGenerated by the UART interface on a frame by frame basis. See for details. RBIST 1h = RBIST busy (registers not readable) 0h = RBIST done (registers readable) RBIST running status. See for details. RBIST1h = RBIST busy (registers not readable) 0h = RBIST done (registers readable)RBIST running status. See for details. RESET 1h = First readback after RESET0h = All other readbacks From the GEN_STATUS register (). See also . RESET1h = First readback after RESET0h = All other readbacksFrom the GEN_STATUS register (). See also . ALARM_STATUS, MODEM_STATUS, and GEN_STATUS registers contain cross-readable IRQ flags for the other registers. The ALARM_STATUS register has the GEN_IRQ and MODEM_IRQ bits. MODEM_STATUS has the GEN_IRQ and ALARM_IRQ bits. GEN_STATUS has the ALARM_IRQ and MODEM_IRQ bits. This functionality enables the system microcontroller to always get full status information by reading only one register, and thus save power. ALARM_STATUS, MODEM_STATUS, and GEN_STATUS registers contain cross-readable IRQ flags for the other registers. The ALARM_STATUS register has the GEN_IRQ and MODEM_IRQ bits. MODEM_STATUS has the GEN_IRQ and ALARM_IRQ bits. GEN_STATUS has the ALARM_IRQ and MODEM_IRQ bits. This functionality enables the system microcontroller to always get full status information by reading only one register, and thus save power.MODEM_STATUS, s and MODEM_IRQs. MODEM_STATUS has the GEN_IRQ and ALARM_IRQ bitsand MODEM_IRQ s Watchdog Timer The AFEx82H1 include a watchdog timer (WDT) that is used to make sure that communication between the system controller and the device is not lost. The WDT checks that the device received a communication from the system controller within a programmable period of time. To enable this feature, set WDT.WDT_EN to 1. The WDT monitors both SPI and UBM communications. The WDT has two limit fields: WDT.WDT_UP and WDT.WDT_LO. The WDT_UP field sets the upper time limit for the WDT. The WDT_LO field sets the lower time limit. If the WDT_LO is set to a value other than 2’b00, then the WDT acts as a window comparator. If the write occurs too quickly (less than the WDT_LO time), or too slowly (greater than the WDT_UP time), then a WDT error is asserted. When acting as a window comparator, in the event of a WDT error, the WDT resets only when a write to the WDT register occurs. If the WDT_LO is set to 2'b00, then a write to any register resets the WDT time counter. In this mode, the WDT error is asserted when the timer expires. If enabled, the chip must have any SPI or UBM write to the device within the programmed timeout window. Otherwise, the ALARM pin asserts low, and the ALARM_STATUS.WD_FLT bit is set to 1. The WD_FLT bit is sticky. After a WD_FLT has been asserted, WDT.WDT_EN must be set to 0 to clear the WDT condition. Then the WDT can be re-enabled. The WDT condition is also cleared by issuing a software or hardware reset. After the WDT condition is clear, WD_FLT is cleared by reading the ALARM_STATUS register. When using multiple AFEx82H1 devices in a daisy-chain configuration, connect the open-drain ALARM pins of all devices together to form a wired-OR network. The watchdog timer can be enabled in any number of the devices in the chain; although, enabling the watchdog timer in one device in the chain is usually sufficient. The wired-OR ALARM pin can be pulled low in response to the simultaneous presence of different trigger conditions in the devices in the daisy-chain. The host processor must read the ALARM_STATUS register of each device to know all the fault conditions present in the chain. The watchdog timeout period is based on a 1200-Hz clock (1.2288 MHz / 1024). Watchdog Timer The AFEx82H1 include a watchdog timer (WDT) that is used to make sure that communication between the system controller and the device is not lost. The WDT checks that the device received a communication from the system controller within a programmable period of time. To enable this feature, set WDT.WDT_EN to 1. The WDT monitors both SPI and UBM communications. The WDT has two limit fields: WDT.WDT_UP and WDT.WDT_LO. The WDT_UP field sets the upper time limit for the WDT. The WDT_LO field sets the lower time limit. If the WDT_LO is set to a value other than 2’b00, then the WDT acts as a window comparator. If the write occurs too quickly (less than the WDT_LO time), or too slowly (greater than the WDT_UP time), then a WDT error is asserted. When acting as a window comparator, in the event of a WDT error, the WDT resets only when a write to the WDT register occurs. If the WDT_LO is set to 2'b00, then a write to any register resets the WDT time counter. In this mode, the WDT error is asserted when the timer expires. If enabled, the chip must have any SPI or UBM write to the device within the programmed timeout window. Otherwise, the ALARM pin asserts low, and the ALARM_STATUS.WD_FLT bit is set to 1. The WD_FLT bit is sticky. After a WD_FLT has been asserted, WDT.WDT_EN must be set to 0 to clear the WDT condition. Then the WDT can be re-enabled. The WDT condition is also cleared by issuing a software or hardware reset. After the WDT condition is clear, WD_FLT is cleared by reading the ALARM_STATUS register. When using multiple AFEx82H1 devices in a daisy-chain configuration, connect the open-drain ALARM pins of all devices together to form a wired-OR network. The watchdog timer can be enabled in any number of the devices in the chain; although, enabling the watchdog timer in one device in the chain is usually sufficient. The wired-OR ALARM pin can be pulled low in response to the simultaneous presence of different trigger conditions in the devices in the daisy-chain. The host processor must read the ALARM_STATUS register of each device to know all the fault conditions present in the chain. The watchdog timeout period is based on a 1200-Hz clock (1.2288 MHz / 1024). The AFEx82H1 include a watchdog timer (WDT) that is used to make sure that communication between the system controller and the device is not lost. The WDT checks that the device received a communication from the system controller within a programmable period of time. To enable this feature, set WDT.WDT_EN to 1. The WDT monitors both SPI and UBM communications. The WDT has two limit fields: WDT.WDT_UP and WDT.WDT_LO. The WDT_UP field sets the upper time limit for the WDT. The WDT_LO field sets the lower time limit. If the WDT_LO is set to a value other than 2’b00, then the WDT acts as a window comparator. If the write occurs too quickly (less than the WDT_LO time), or too slowly (greater than the WDT_UP time), then a WDT error is asserted. When acting as a window comparator, in the event of a WDT error, the WDT resets only when a write to the WDT register occurs. If the WDT_LO is set to 2'b00, then a write to any register resets the WDT time counter. In this mode, the WDT error is asserted when the timer expires. If enabled, the chip must have any SPI or UBM write to the device within the programmed timeout window. Otherwise, the ALARM pin asserts low, and the ALARM_STATUS.WD_FLT bit is set to 1. The WD_FLT bit is sticky. After a WD_FLT has been asserted, WDT.WDT_EN must be set to 0 to clear the WDT condition. Then the WDT can be re-enabled. The WDT condition is also cleared by issuing a software or hardware reset. After the WDT condition is clear, WD_FLT is cleared by reading the ALARM_STATUS register. When using multiple AFEx82H1 devices in a daisy-chain configuration, connect the open-drain ALARM pins of all devices together to form a wired-OR network. The watchdog timer can be enabled in any number of the devices in the chain; although, enabling the watchdog timer in one device in the chain is usually sufficient. The wired-OR ALARM pin can be pulled low in response to the simultaneous presence of different trigger conditions in the devices in the daisy-chain. The host processor must read the ALARM_STATUS register of each device to know all the fault conditions present in the chain. The watchdog timeout period is based on a 1200-Hz clock (1.2288 MHz / 1024). The AFEx82H1 include a watchdog timer (WDT) that is used to make sure that communication between the system controller and the device is not lost. The WDT checks that the device received a communication from the system controller within a programmable period of time. To enable this feature, set WDT.WDT_EN to 1. The WDT monitors both SPI and UBM communications. AFEx82H1The WDT has two limit fields: WDT.WDT_UP and WDT.WDT_LO. The WDT_UP field sets the upper time limit for the WDT. The WDT_LO field sets the lower time limit. If the WDT_LO is set to a value other than 2’b00, then the WDT acts as a window comparator. If the write occurs too quickly (less than the WDT_LO time), or too slowly (greater than the WDT_UP time), then a WDT error is asserted. When acting as a window comparator, in the event of a WDT error, the WDT resets only when a write to the WDT register occurs. If the WDT_LO is set to 2'b00, then a write to any register resets the WDT time counter. In this mode, the WDT error is asserted when the timer expires.If enabled, the chip must have any SPI or UBM write to the device within the programmed timeout window. Otherwise, the ALARM pin asserts low, and the ALARM_STATUS.WD_FLT bit is set to 1. The WD_FLT bit is sticky. After a WD_FLT has been asserted, WDT.WDT_EN must be set to 0 to clear the WDT condition. Then the WDT can be re-enabled. The WDT condition is also cleared by issuing a software or hardware reset. After the WDT condition is clear, WD_FLT is cleared by reading the ALARM_STATUS register. ALARMWhen using multiple AFEx82H1 devices in a daisy-chain configuration, connect the open-drain ALARM pins of all devices together to form a wired-OR network. The watchdog timer can be enabled in any number of the devices in the chain; although, enabling the watchdog timer in one device in the chain is usually sufficient. The wired-OR ALARM pin can be pulled low in response to the simultaneous presence of different trigger conditions in the devices in the daisy-chain. The host processor must read the ALARM_STATUS register of each device to know all the fault conditions present in the chain.AFEx82H1ALARMALARMThe watchdog timeout period is based on a 1200-Hz clock (1.2288 MHz / 1024). Register Maps #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/TABLE_ILZ_TX1_TPB lists the memory-mapped registers for the AFEx82H1 registers. Consider all register offset addresses not listed in #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/TABLE_ILZ_TX1_TPB as reserved locations; do not modify these register contents. Register Map ADDR (HEX) REGISTER BIT DESCRIPTION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h NOP NOP [15:0] 01h DAC_DATA DATA [15:0] 02h CONFIG CRC_ERR_CNT [1:0] CLKO [3:0] UBM_IRQ_EN IRQ_PIN_EN CLR_PIN_EN UART_DIS UART_BAUD CRC_EN IRQ_POL IRQ_LVL DSDO FSDO 03h DAC_CFG RESERVED PD SR_CLK [2:0] SR_STEP [2:0] SR_EN SR_MODE RESERVED CLR RESERVED 04h DAC_GAIN GAIN [15:0] 05h DAC_OFFSET OFFSET [15:0] 06h DAC_CLR_CODE CODE [15:0] 07h RESET RESERVED SW_RST [7:0] 08h ADC_CFG BUF_PD HYST [6:0] FLT_CNT [2:0] AIN_RANGE EOC_PER_CH CONV_RATE [1:0] DIRECT_MODE 09h ADC_INDEX_CFG RESERVED STOP [3:0] START [3:0] 0Ah TRIGGER RESERVED RBIST MBIST SHADOWLOAD ADC 0Bh SPECIAL_CFG #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-DDD5E850-D3C4-44CC-92C9-81DB08FE3C68 RESERVED OTP_LOAD_SW_RST ALMV_POL AIN1_ENB 0Eh MODEM_CFG Tx2200Hz RESERVED DUPLEX_EXT RX_HORD_EN RX_EXTFILT_EN TxRES TxAMP [4:0] HART_EN DUPLEX TxHPD RTS 0Fh FIFO_CFG RESERVED FIFO_H2U_FLUSH FIFO_U2H_FLUSH H2U_LEVEL_SET [3:0] U2H_LEVEL_SET [3:0] 10h ALARM_ACT SD_FLT [1:0] TEMP_FLT [1:0] AIN1_FLT [1:0] AIN0_FLT [1:0] CRC_WDT_FLT [1:0] VREF_FLT [1:0] THERM_ERR_FLT [1:0] THERM_WARN_FLT [1:0] 11h WDT RESERVED WDT_UP [2:0] WDT_LO [1:0] WDT_EN 12h AIN0_THRESHOLD Hi [7:0] Lo [7:0] 13h AIN1_THRESHOLD Hi [7:0] Lo [7:0] 14h TEMP_THRESHOLD Hi [7:0] Lo [7:0] 15h FIFO_U2H_WR RESERVED PARITY DATA [7:0] 16h UBM #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-D0D7F115-E0CF-4F1A-A6B9-B372A61327B8 RESERVED REG_MODE 18h SCRATCH DATA [15:0] 19h CHIP_ID_LSB ID [15:0] 1Ah CHIP_ID_MSB ID [15:0] 1Bh GPIO_CFG RESERVED EN [6:0] RESERVED ODE [6:0] 1Ch GPIO RESERVED DATA [6:0] 1Dh ALARM_STATUS_MASK RESERVED SD_FLT OSC_FAIL RESERVED OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 1Eh GEN_STATUS_MASK RESERVED BIST_DONE BIST_FAIL RESERVED SR_BUSYn ADC_EOC RESERVED BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 1Fh MODEM_STATUS_MASK RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 20h ALARM_STATUS GEN_IRQ MODEM_IRQ SD_FLT OSC_FAIL CRC_CNT [1:0] OTP_LOADEDn OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 21h GEN_STATUS ALARM_IRQ MODEM_IRQ RESERVED OTP_BUSY BIST_ MODE BIST_DONE BIST_FAIL RESET SR_BUSYn ADC_EOC ADC_BUSY PVDD_HI BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 22h MODEM_STATUS ALARM_IRQ GEN_IRQ RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 23h ADC_FLAGS RESERVED SD4_FAIL SD3_FAIL SD2_FAIL SD1_FAIL SD0_FAIL TEMP_FAIL AIN1_FAIL AIN0_FAIL RESERVED 24h ADC_AIN0 RESERVED DATA [11:0] 25h ADC_AIN1 RESERVED DATA [11:0] 26h ADC_TEMP RESERVED DATA [11:0] 27h ADC_SD_MUX RESERVED DATA [11:0] 28h ADC_OFFSET RESERVED DATA [11:0] 2Ah FIFO_H2U_RD LEVEL [3:0] LEVEL_FLAG FULL_FLAG EMPTY_FLAG PARITY DATA [7:0] 2Bh FIFO_STATUS H2U_LEVEL [3:0] H2U_LEVEL_FLAG H2U_FULL_FLAG H2U_EMPTY_FLAG RESERVED U2H_LEVEL [3:0] U2H_LEVEL_FLAG U2H_FULL_FLAG U2H_EMPTY_FLAG RESERVED 2Ch DAC_OUT DATA [15:0] 2Dh ADC_OUT RESERVED DATA [11:0] 2Eh ADC_BYP DATA_BYP_EN OFST_BYP_EN DIS_GND_SAMP RESERVED DATA [11:0] 2Fh FORCE_FAIL CRC_FLT VREF_FLT THERM_ERR_FLT THERM_WARN_FLT RESERVED SD4_HI_FLT SD4_LO_FLT SD3_HI_FLT SD3_LO_FLT SD2_HI_FLT SD2_LO_FLT SD1_HI_FLT SD1_LO_FLT SD0_HI_FLT SD0_LO_FLT 3Bh TIMER_CFG_0 RESERVED CLK_SEL [1:0] INVERT ENABLE 3Ch TIMER_CFG_1 PERIOD [15:0] 3Dh TIMER_CFG_2 SET_TIME [15:0] 3Eh CRC_RD CRC [15:0] 3Fh RBIST_CRC CRC [15:0] The SPECIAL_CFG register can only be reset with POR, and does not respond to the RESET pin or SW_RST command. The UBM register can only be accessed with a UBM command. AFEx82H1 Registers Complex bit access types are encoded to fit into small table cells. The following table shows the codes that are used for access types in this section. AFEx82H1 Access-Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W WO Write only W WSC Write self clear Reset or Default Value -n Value after reset or the default value Register Array Variables i,j,k,l,m,n When used in a register name, an offset, or an address, these variables refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. y When used in a register name, an offset, or an address, this variable refers to the value of a register array. NOP Register (Offset = 0h) [Reset = 0000h] Return to the Register Map . NOP Register Field Descriptions Bit Field Type Reset Description 15-0 NOP WO 0h No operation. Data written to this field have no effect. Always reads zeros. DAC_DATA Register (Offset = 1h) [Reset = 0000h] Return to the Register Map . DAC code for VOUT. DAC_DATA Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W 0h Data. DAC code for VOUT. CONFIG Register (Offset = 2h) [Reset = 0036h] Return to the Register Map . CONFIG Register Field Descriptions Bit Field Type Reset Description 15-14 CRC_ERR_CNT R/W 0h CRC Errors Count LimitSets the numbers of consecutive SPI CRC frames that must have errors before the status bits is set. 0h = 1 (default); 1h = 2; 2h = 4; 3h = 8 13-10 CLKO R/W 0h CLKO EnableEnable the CLK_OUT pin and set the divider value. 0h = CLKO disabled (default); 1h = 1.2288 MHz; 2h = 1.2288 / 2 MHz; 3h = 1.2288 / 4 MHz; 4h = 1.2288 / 8 MHz; 5h = 1.2288 / 16 MHz; 6h =1.2288 / 32 MHz; 7h = 1.2288 / 64 MHz; 8h = 1.2288 / 128 MHz; 9h = 1.2288 / 256 MHz; Ah = 1.2288 / 512 MHz; Bh = 1.2288 / 1024 MHz; Ch = 1'b0; Dh = 1'b0; Eh = 1'b0; Fh = Timer 9 UBM_IRQ_EN R/W 0h UBM IRQ EnableEnable IRQ to be sent on UARTOUT through UBM.0h = Disabled (default); 1h = Enabled 8 IRQ_PIN_EN R/W 0h IRQ Pin EnableEnable IRQ pin functionality.0h = Disabled (default); 1h = Enabled 7 CLR_PIN_EN R/W 0h Clear Input Pin EnableEnable pin-based transition to the CLEAR state in UBM.0h = Disabled (default); 1h = SDI pin configured as clear input pin 6 UART_DIS R/W 0h UART DisableDisable UART functionality.0h = UART Enabled (default); 1h = UART Disabled 5 UART_BAUD R/W 1h UART BaudConfigure BAUD rate for UART.0h = 1200 baud (no break); 1h = 9600 baud (Break mode) (default) 4 CRC_EN R/W 1h CRC EnableEnable CRC for SPI.0h = Disabled; 1h = Enabled (default) 3 IRQ_POL R/W 0h IRQ Polarity0h = Active low (default); 1h = Active high 2 IRQ_LVL R/W 1h IRQ Level0h = Edge sensitive; 1h = Level sensitive (default) 1 DSDO R/W 1h SDO Hi-Z0h = Drive SDO during CS = 0; 1h = SDO always Hi-Z (default) 0 FSDO R/W 0h Fast SDOSDO is driven on negative edge of SCLK.0h = drive SDO on rising edge of SCLK (launching edge) (default) 1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock early) DAC_CFG Register (Offset = 3h) [Reset = 0B00h] Return to the Register Map . DAC_CFG Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R/W 0h 12 PD R/W 0h DAC Output Buffer Power-down DAC output set to Hi-Z in power-down. 0h = DAC output buffer enabled (default) 1h = DAC output buffer disabled 11-9 SR_CLK R/W 5h Slew Clock Rate 0h = 307.2 kHz 1h = 153.6 kHz 2h = 76.8 kHz 3h = 38.4 kHz 4h = 19.2 kHz 5h = 9600 Hz (default) 6h = 4800 Hz 7h = 2400 Hz 8-6 SR_STEP R/W 4h Slew Step Size 0h = 1 code 1h = 2 codes 2h = 4 codes 3h = 8 codes 4h = 16 codes (default) 5h = 32 codes 6h = 64 codes 7h = 128 codes 5 SR_EN R/W 0h Slew Enable Enables slew on the output voltage. 0h = Disabled (default) 1h = Enabled 4 SR_MODE R/W 0h Slew Mode Output slew rate mode select. 0h = Linear Slew (default) 1h = Sinusoidal Slew 3 RESERVED R 0h 2 CLR R/W 0h CLEAR State 0h = Normal operation (default) 1h = Force the DAC to the CLEAR state 1-0 RESERVED R 0h DAC_GAIN Register (Offset = 4h) [Reset = 8000h] Return to the Register Map . DAC_GAIN Register Field Descriptions Bit Field Type Reset Description 15-0 GAIN R/W 8000h GainSet the gain of the DAC output from 0.5 – 1.499985. For example: 0000h = 0.5 8000h = 1.0 (default) FFFFh = 1.499985 DAC_OFFSET Register (Offset = 5h) [Reset = 0000h] Return to the Register Map . DAC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-0 OFFSET R/W 0h OffsetAdjust the offset of the DAC output, 2's complement number. For example: 0000h = 0 (default) FFFFh = –1 DAC_CLR_CODE Register (Offset = 6h) [Reset = 0000h] Return to the Register Map . DAC_CLR_CODE Register Field Descriptions Bit Field Type Reset Description 15-0 CODE R/W 0h CLEAR State DAC CodeDAC code applied in the CLEAR state. See . RESET Register (Offset = 7h) [Reset = 0000h] Return to the Register Map . RESET Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-0 SW_RST WSC 0h Software Reset Write ADh to initiate software reset. ADC_CFG Register (Offset = 8h) [Reset = 8810h] Return to the Register Map . ADC_CFG Register Field Descriptions Bit Field Type Reset Description 15 BUF_PD R/W 1h ADC Buffer Power-Down 0h = ADC buffer enabled; 1h = ADC buffer powered down (default) 14-8 HYST R/W 8h HysteresisThe number of codes of hysteresis used when a threshold is exceeded for an ADC measurement of AIN0/AIN1/TEMP. 7-5 FLT_CNT R/W 0h Fault Count Number of successive faults to trip an alarm.Number of successive faults is programmed value + 1 (1-8 faults). 4 AIN_RANGE R/W 1h ADC Analog Input Range Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs. 0h = 2 × VREF; 1h = 1 × VREF (default) 3 EOC_PER_CH R/W 0h ADC End-of-Conversion for Every ChannelSends an EOC pulse at the end of each channel instead of at the end of all the channels.0h = EOC after last channel (default); 1h = EOC for every channel 2-1 CONV_RATE R/W 0h ADC Conversion RateThis setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based on a 76.8-kHz ADC clock. All other channels use 2560 Hz. 0h = 3840 Hz (default) 1h = 2560 Hz 2h = 1280 Hz 3h = 640 Hz 0 DIRECT_MODE R/W 0h Direct Mode Enable 0h = Auto mode (default); 1h = Direct mode ADC_INDEX_CFG Register (Offset = 9h) [Reset = 0080h] Return to the Register Map . The ADC custom channel sequencing configuration is shown in #GUID-121F6531-236F-4BFA-AA11-8CC4C580B655/GUID-84429441-E2D5-4137-992B-F0A3EE3367A1. ADC_INDEX_CFG Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-4 STOP R/W 8h Custom Channel Sequencer Stop IndexCCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START. 0h = OFFSET 1h = AIN0 2h = AIN1 3h = TEMP 4h = SD0 (VREF) 5h = SD1 (PVDD) 6h = SD2 (VDD) 7h = SD3 (ZTAT) 8h = SD4 (VOUT) (default) 9h through Fh = GND 3-0 START R/W 0h Custom Channel Sequencer Start IndexCCS index to start ADC sequence.0h through Fh = Same as STOP field (0h is default) TRIGGER Register (Offset = Ah) [Reset = 0000h] Return to the Register Map . TRIGGER Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED R 0h 3 RBIST WSC 0h RBIST Trigger This trigger initiates a Register BIST. This BIST runs a CRC calculation through the configuration registers () and compares the result to a stored CRC value in the RBIST_CRC register. 2 MBIST WSC 0h Memory Built-In Self-Test Trigger This trigger initiates an MBIST on the SRAM that is used for the FIFO. During this time communication to/from HART does not work as MBIST takes over the control of the SRAM. 1 SHADOWLOAD WSC 0h Shadow Load TriggerThis trigger initiates the loading of the OTP array into the parallel latches. If an OTP CRC error is detected, assert this trigger to try and reload the OTP into the memory locations. 0 ADC WSC 0h ADC TriggerIn auto mode, this bit enables or disables the conversions. Manually set to 1 (enable) or 0 (disable). In direct mode, set this bit to start a conversion sequence. The bit is cleared at the end of the sequence. To stop a sequence prematurely, manually clear this bit. SPECIAL_CFG Register (Offset = Bh) [Reset = 0000h] Return to the Register Map . SPECIAL_CFG Register Field Descriptions Bit Field Type Reset Description 15-3 RESERVED R 0h 2 OTP_LOAD_SW_RST R/W 0h OTP (One Time Programmable Factory Trimmed Registers) LOAD with SW RESETOTP reloads with the assertion of a software reset (SW_RST). 0h = No reload with SW_RST 1h = Reload with SW_RST 1 ALMV_POL R/W 0h Alarm Voltage PolarityThis register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB bit is low) to control the VOUT during a hardware reset condition or if alarm is active and alarm action is set appropriately. The following Boolean function is implemented for the internal signal ALMV_POL_o that sets the VOUT voltage:ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT AIN1_ENB) 0h = Low (0 V) 1h = High (2.5 V) 0 AIN1_ENB R/W 0h AIN1 Pin EnableThis bit determines whether the POL_SEL/AIN1 pin acts as alarm voltage polarity control bit or an input channel to the ADC. 0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts GND 1h = AIN1 pin is an active channel to the ADC MODEM_CFG Register (Offset = Eh) [Reset = 0040h] Return to the Register Map . MODEM_CFG Register Field Descriptions Bit Field Type Reset Description 15 Tx2200Hz R/W 0h Transmit 2200 Hz OnlyBy not sending data to the FIFO buffer and asserting RTS, the user can transmit multiples of 1200 Hz as long as RTS is asserted. By setting this bit the user can transmit multiples of 2200 Hz. Setting this bit prevents data in the FIFO buffer from being correctly transmitted. If using this bit there is no need to use the FIFO buffer. 0h = Transmit 1200 Hz and 2200 Hz (default) 1h = Transmit only 2200 Hz 14-13 RESERVED R 0h 12 DUPLEX_EXT R/W 0h Duplex External ModeAllows full duplex mode but expects the connection of MOD_OUT to RX_IN to be made externally. 0h = Internal duplex connection (default) 1h = External duplex connection 11 RX_HORD_EN R/W 0h High Order Filter EnableEnables a higher order filter on HART_RX. 0h = Disable (default); 1h = Enable 10 RX_EXTFILT_EN R/W 0h External Filter EnableEnables the use of an external filter for HART_RX. If enabled, then connect the HART signal to RX_INF. 0h = Use internal filter (default); 1h = Use external filter 9 TxRES R/W 0h HART Transmit Resolution0h = 32 steps per period (default) at 38.4 kHz update rate for 1200 baud 1h = 128 steps per period at 153.6 kHz update rate for 1200 baud 128-step per period waveform consumes more power. 8-4 TxAMP R/W 4h Transmit AmplitudeHART Tx amplitude. 00h = 400 mVPP; 01h = 425 mVPP 02h = 450 mVPP; 03h = 475 mVPP 04h = 500 mVPP (default); 05h = 525 mVPP 06h = 550 mVPP; 07h = 575 mVPP 08h = 600 mVPP; 09h = 625 mVPP 0Ah = 650 mVPP; 0Bh = 675 mVPP 0Ch = 700 mVPP; 0Dh = 725 mVPP 0Eh = 750 mVPP; 0Fh = 775 mVPP 10h through 1Fh = 800 mVPP 3 HART_EN R/W 0h HART EnableEnable the HART Tx and Rx.0h = Disable (default); 1h = Enable 2 DUPLEX R/W 0h Duplex ModeEnable internal connection of Tx to Rx for debug and testing.0h = Normal operation (default); 1h = Duplex enabled 1 TxHPD R/W 0h HART Tx DAC Output Buffer Hi-Z in Rx Mode or When Disabled0h = HART Tx DAC output is set to midcode with 50 kΩ output impedance (default) 1h = HART Tx DAC is Hi-Z in Rx mode or when disabled. Users can set the default voltage level with an external circuit. 0 RTS R/W 0h Request To Send Starts transmitting a carrier on MOD_OUT pin.0h = No action (default) 1h = Request to send. Device starts modulating the MOD_OUT pin if CD = 0. FIFO_CFG Register (Offset = Fh) [Reset = 00F0h] Return to the Register Map . FIFO_CFG Register Field Descriptions Bit Field Type Reset Description 15-10 RESERVED R 0h 9 FIFO_H2U_FLUSH WSC 0h Flush HART-to-µC FIFO (FIFO_H2U) Clear the pointers for the FIFO_H2U. 8 FIFO_U2H_FLUSH WSC 0h Flush µC-to-HART FIFO (FIFO_U2H) Clear the pointers for the FIFO_U2H. 7-4 H2U_LEVEL_SET R/W Fh FIFO_H2U FIFO Level Flag Trip SetSets the level for FIFO_H2U at which the Level Flag trips. This is a (>) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. 3-0 U2H_LEVEL_SET R/W 0h FIFO_U2H FIFO Level Flag Trip SetSets the level for FIFO_U2H at which the Level Flag trips. This is a (<) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. ALARM_ACT Register (Offset = 10h) [Reset = 8020h] Return to the Register Map . ALARM_ACT Register Field Descriptions Bit Field Type Reset Description 15-14 SD_FLT R/W 2h Self-Diagnostic Fault Action These bits set the device action after a self-diagnostic fault. 0h = No Action 1h = Set DAC to CLEAR state 2h = Switch to alarm voltage determined by ALMV_POL (default) 3h = Place DAC into Hi-Z (power-down) 13-12 TEMP_FLT R/W 0h TEMP Fault ActionThese bits set the device action if the ADC temperature is outside the TEMP_THRESHOLD Hi or Lo thresholds.0h through 3h = Same as SD_FLT field (default 0h) 11-10 AIN1_FLT R/W 0h AIN1 Fault ActionThese bits set the device action if the ADC AIN1 channel is outside the AIN1_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 9-8 AIN0_FLT R/W 0h AIN0 Fault Action These bits set the device action if the ADC AIN0 channel is outside the AIN0_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 7-6 CRC_WDT_FLT R/W 0h CRC and WDT Fault ActionThese bits set the device action when a SPI CRC or SPI Watchdog Timeout error occurs. 0h through 3h = Same as SD_FLT field (default 0h) 5-4 VREF_FLT R/W 2h VREF Fault ActionThese bits set the device action when a fault is detected on VREF. 0h through 3h = Same as SD_FLT field a 3-2 THERM_ERR_FLT R/W 0h Thermal Error Fault ActionThese bits set the device action when a high temperature error occurs (> 130°C). 0h through 3h = Same as SD_FLT field (default 0h) 1-0 THERM_WARN_FLT R/W 0h Thermal Warning Fault ActionThese bits set the device action when a high temperature warning occurs (> 85°C). 0h through 3h = Same as SD_FLT field (default 0h) WDT Register (Offset = 11h) [Reset = 0018h] Return to the Register Map . WDT Register Field Descriptions Bit Field Type Reset Description 15-6 RESERVED R 0h 5-3 WDT_UP R/W 3h Watchdog Timer (WDT) Upper LimitIf the WDT is enabled and the timer exceeds the programmed value, a WDT error is asserted. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = 53 ms (64 clocks) 1h = 106 ms (128 clocks) 2h = 427 ms (512 clocks) 3h = 853 ms (1024 clocks, default) 4h = 1.7 s (2048 clocks) 5h = 2.56 s (3072 clocks) 6h = 3.41 s (4096 clocks) 7h = 5.12 s (6144 clocks) 2-1 WDT_LO R/W 0h WDT Lower LimitIf the WDT is enabled and the WDT Lower Limit is enabled, then only a write to this register resets the WDT timer. If the write occurs before the WDT Lower Limit time, or after the WDT Upper Limit time, then a WDT error is asserted. If WDT Lower Limit is disabled, then a write to any register resets the timer. This is true for both SPI and UART Break modes. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = Disabled (default) 1h = 53 ms (64 clocks) 2h = 106 ms (128 clocks) 3h = 427 ms (512 clocks) 0 WDT_EN R/W 0h WDT Enable 0h = Disabled (default); 1h = Enabled AIN0_THRESHOLD Register (Offset = 12h) [Reset = FF00h] Return to the Register Map . AIN0_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN0 {[11:4],4b1111} This value is compared (>) against AIN0 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN0 {[11:4],4b0000} This value is compared (<) against AIN0 data bits[11:0]. AIN1_THRESHOLD Register (Offset = 13h) [Reset = FF00h] Return to the Register Map . AIN1_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN1 {[11:4],4b1111} This value is compared (>) against AIN1 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN1 {[11:4],4b0000} This value is compared (<) against AIN1 data bits[11:0]. TEMP_THRESHOLD Register (Offset = 14h) [Reset = FF00h] Return to the Register Map . TEMP_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel TEMP {[11:4],4b1111} This value is compared (>) against TEMP data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel TEMP {[11:4],4b0000} This value is compared (<) against TEMP data bits[11:0]. FIFO_U2H_WR Register (Offset = 15h) [Reset = 0000h] Return to the Register Map . This register controls the HART to microcontroller FIFO buffer. FIFO_U2H_WR Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h 8 PARITY WO 0h ParityOdd parity bit to be transmitted with data. This field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. 7-0 DATA WO 0h Data ByteThis field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. UBM Register (Offset = 16h) [Reset = 0000h] Return to the Register Map . UBM Register Field Descriptions Bit Field Type Reset Description 15-1 RESERVED R 0h 0 REG_MODE R/W 0h Register ModeConfigure the rest of the Register Map to be accessed by UART break mode (UBM) or SPI. This register can only be written by the UART Break communication.0h = SPI Mode (default) 1h = UART Break Mode SCRATCH Register (Offset = 18h) [Reset = FFFFh] Return to the Register Map . SCRATCH Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W FFFFh Scratch Data Data written is read back as the inverted value. For example, writing 0xAAAA is read back as 0x5555. CHIP_ID_LSB Register (Offset = 19h) Return to the Register Map . CHIP ID LSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Unique part number within each lot CHIP_ID_MSB Register (Offset = 1Ah) Return to the Register Map . CHIP ID MSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Encoded lot identification number GPIO_CFG Register (Offset = 1Bh) [Reset = 00FFh] Return to the Register Map . GPIO CONFIG Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R 0h 14-8 EN R/W 00h GPIO per Pin Enable. (See for additional configuration required specific to each pin and communication mode) [14] = GPIO6 [13] = GPIO5 [12] = GPIO4 [11] = GPIO3 [10] = GPIO2 [9] = GPIO1 [8] = GPIO00h = GPIO function disable1h = GPIO function enabledFor any pin used either for the communication function or not used as an active GPIO, set this bit to 0h. 7 RESERVED R 0h 6-0 ODE R/W FFh Pseudo Open Drain EnableGPIO output enable and pseudo open drain functionality on the GPIO pins. (See for additional configuration required specific to each pin and communication mode.) [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO00h = Push-pull output enabled1h = Pseudo open-drain output enabled GPIO Register (Offset = 1Ch) [Reset = 007Fh] Return to the Register Map . GPIO Register Field Descriptions Bit Field Type Reset Description 15-7 RESERVED R 0h 6-0 DATA R/W 7Fh GPIO pin data. For GPIO input this bit must be written as 1 and GPIO_CFG.ODE = 1 and GPIO_CFG.EN = 1. Reading this register reads the pin value when the pin is correctly enabled. (See for additional configuration required specific to each pin and communication mode) For GPIO output this bit sets the pin value. [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO0 ALARM_STATUS_MASK Register (Offset = 1Dh) [Reset = EFDFh] Return to the Register Map . ALARM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-14 RESERVED R 3h 13 SD_FLT R/W 1h SD Fault Mask0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 12 OSC_FAIL R/W 0h OSC_FAIL Fault Mask Same as SD Fault Mask (default 0h). 11-9 RESERVED R 7h 8 OTP_CRC_ERR R/W 1h OTP CRC Error Mask Same as SD Fault Mask (default 1h). 7 CRC_FLT R/W 1h SPI CRC Fault Mask Same as SD Fault Mask (default 1h). 6 WD_FLT R/W 1h Watchdog Fault Mask Same as SD Fault Mask (default 1h). 5 VREF_FLT R/W 0h VREF Fault Mask Same as SD Fault Mask (default 0h). 4 ADC_AIN1_FLT R/W 1h ADC AIN1 Fault Mask Same as SD Fault Mask (default 1h). 3 ADC_AIN0_FLT R/W 1h ADC AIN0 Fault Mask Same as SD Fault Mask (default 1h). 2 ADC_TEMP_FLT R/W 1h ADC TEMP Fault Mask Same as SD Fault Mask (default 1h). 1 THERM_ERR_FLT R/W 1h Temperature > 130°C Error Mask Same as SD Fault Mask (default 1h). 0 THERM_WARN_FLT R/W 1h Temperature > 85°C Warning Mask Same as SD Fault Mask (default 1h). GEN_STATUS_MASK Register (Offset = 1Eh) [Reset = FFFFh] Return to the Register Map . GEN_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-11 RESERVED R 1Fh 10 BIST_DONE R/W 1h BIST Done Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 9 BIST_FAIL R/W 1h BIST Failed Fault Mask Same as BIST Done Mask (default 1h). 8 RESERVED R 1h 7 SR_BUSYn R/W 1h Slew Rate Not Busy Mask Same as BIST Done Mask (default 1h). 6 ADC_EOC R/W 1h ADC End Of Conversion Mask Same as BIST Done Mask (default 1h). 5-4 RESERVED R 3h 3 BREAK_FRAME_ERR R/W 1h Break Frame Error Fault Mask Same as BIST Done Mask (default 1h). 2 BREAK_PARITY_ERR R/W 1h Break Parity Error Fault Mask Same as BIST Done Mask (default 1h). 1 UART_FRAME_ERR R/W 1h UART Frame Error Fault Mask Same as BIST Done Mask (default 1h). 0 UART_PARITY_ERR R/W 1h UART Parity Error Fault Mask Same as BIST Done Mask (default 1h). MODEM_STATUS_MASK Register (Offset = 1Fh) [Reset = FFFFh] Return to the Register Map . MODEM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R 7h 12 GAP_ERR R/W 1h HART Gap Error Fault Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 11 FRAME_ERR R/W 1h HART Frame Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 10 PARITY_ERR R/W 1h HART Parity (ODD) Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 9 FIFO_H2U_LEVEL_FLAG R/W 1h FIFO_H2U Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 8 FIFO_H2U_FULL_FLAG R/W 1h FIFO_H2U Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 7 FIFO_H2U_EMPTY_FLAG R/W 1h FIFO_H2U Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 6 FIFO_U2H_LEVEL_FLAG R/W 1h FIFO_U2H Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 5 FIFO_U2H_FULL_FLAG R/W 1h FIFO_U2H Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 4 FIFO_U2H_EMPTY_FLAG R/W 1h FIFO_U2H Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 3 CD_DEASSERT R/W 1h CD Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 2 CD_ASSERT R/W 1h CD Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 1 CTS_DEASSERT R/W 1h CTS Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 0 CTS_ASSERT R/W 1h CTS Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). ALARM_STATUS Register (Offset = 20h) [Reset = 0200h] Return to the Register Map . ALARM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 SD_FLT R 0h Self Diagnostic (SD) Fault0h = All self diagnostic channels are within threshold limits 1h = At least one of the self diagnostic channels has failed 12 OSC_FAIL R 0h Oscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed IRQ.0h = Oscillator started; 1h = Oscillator has failed to start 11-10 CRC_CNT R 0h CRC Fault CounterIf counter limit ≤ 4 then bits[1:0] of the counter are shown here. If the counter limit = 8 then bits[2:1] of the counter are shown. 9 OTP_LOADEDn R 1h OTP NOT Loaded Clears when OTP has loaded at least once. Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ.0h = OTP has loaded at least once; 1h = OTP has not finished loading 8 OTP_CRC_ERR R 0h OTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation. Sticky, cleared by reading register, unless condition still persist.0h = No OTP CRC fault; 1h = OTP CRC fault 7 CRC_FLT R 0h CRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame. Sticky, cleared by reading register, unless condition still persist.0h = No CRC fault; 1h = CRC fault 6 WD_FLT R 0h Watchdog Timer Fault Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No watchdog fault; 1h = Watchdog fault 5 VREF_FLT R 0h Invalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Valid VREF voltage; 1h = Invalid VREF voltage 4 ADC_AIN1_FLT R 0h ADC AIN1 Fault. Maskable fault. 0h = AIN1 ADC measurement within threshold limits 1h = AIN1 ADC measurement outside threshold limits 3 ADC_AIN0_FLT R 0h ADC AIN0 Fault. Maskable fault. 0h = AIN0 ADC measurement within threshold limits 1h = AIN0 ADC measurement outside threshold limits 2 ADC_TEMP_FLT R 0h ADC Temp Fault. Maskable fault. 0h = TEMP ADC measurement within threshold limits 1h = TEMP ADC measurement outside threshold limits 1 THERM_ERR_FLT R 0h Temperature > 130°C error. Maskable fault. OR with FORCE_FAIL.THERM_ERR_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C 0 THERM_WARN_FLT R 0h Temperature > 85°C warning. Maskable fault. OR with FORCE_FAIL.THERM_WARN_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C GEN_STATUS Register (Offset = 21h) [Reset = 1180h] Return to the Register Map . GEN_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 RESERVED R 0h 12 OTP_BUSY R 1h OTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches.0h = OTP has completed loading into the device 1h = OTP is being loaded into the device 11 BIST_MODE R 0h Denotes which BIST is being run.0h = MBIST; 1h = RBIST 10 BIST_DONE R 0h BIST Completed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has not completed; 1h = BIST has completed 9 BIST_FAIL R 0h BIST Failed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has passed; 1h = BIST has failed 8 RESET R 1h Device Reset Occurred. Status only. Does not feed IRQ.Sticky, cleared by reading register, unless condition still persist. 0h = Device has not reset since last read of register 1h = Device has reset since last read of register 7 SR_BUSYn R 1h Slew Rate Not Busy. Maskable fault. 0h = DAC is slewing to the target code1h = DAC_OUT has reached the DAC_DATA. If slew rate is disabled, then this signal produces a rising edge within 3 internal clock cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can cause an unwanted fast transition on VOUT. 6 ADC_EOC R 0h ADC End of Conversion (EOC). Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No EOC since last read of register; 1h = ADC end of conversion 5 ADC_BUSY R 0h ADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true. 0h = No ADC activity; 1h = ADC is actively converting 4 PVDD_HI R 0h PVDD High. Status only. Does not feed IRQ. Set as long as condition is true. 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7 V 3 BREAK_FRAME_ERR R 0h Incorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break frame error; 1h = Break frame error 2 BREAK_PARITY_ERR R 0h Incorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break parity error; 1h = Break parity error 1 UART_FRAME_ERR R 0h Incorrect Stop Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART frame error; 1h = UART frame error 0 UART_PARITY_ERR R 0h Incorrect Parity (ODD) Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART parity error; 1h = UART parity error MODEM_STATUS Register (Offset = 22h) [Reset = 009Ah] Return to the Register Map . MODEM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 13 RESERVED R 0h 12 GAP_ERR R 0h HART Gap Error. Maskable fault. Applies to RX_IN/RX_INF. Too much time (11 bit times) between HART characters. Sticky, cleared by reading register, unless condition still persist. Fatal Fault.0h = No HART gap error; 1h = HART gap error 11 FRAME_ERR R 0h Incorrect Stop Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. Fatal Fault. 0h = No HART frame error; 1h = HART frame error 10 PARITY_ERR R 0h Incorrect Parity (ODD) Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. 0h = No HART parity error; 1h = HART parity error 9 FIFO_H2U_LEVEL_FLAG R 0h FIFO HART-to-µC Level Flag. Maskable fault. If the level of the FIFO_H2U is full, then the level flag is not asserted, but the full flag is, so no information is lost.0h = FIFO_H2U level ≤ {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 1h = FIFO_H2U level > {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 8 FIFO_H2U_FULL_FLAG R 0h FIFO HART-to-µC Full Flag. Maskable fault. 0h = FIFO_H2U is not full; 1h = FIFO_H2U is full 7 FIFO_H2U_EMPTY_FLAG R 1h FIFO HART-to-µC Empty Flag. Maskable fault. 0h = FIFO_H2U is not empty; 1h = FIFO_H2U is empty 6 FIFO_U2H_LEVEL_FLAG R 0h FIFO µC-to-HART Level Flag. Maskable fault. FIFO_U2H < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0}. When the FIFO_U2H is empty, this flag is set unless FIFO_CFG.U2H_LEVEL_SET = 0. This flag and the empty flag can be set at the same time.0h = FIFO_U2H level ≥ {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 1h = FIFO_U2H level < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 5 FIFO_U2H_FULL_FLAG R 0h FIFO µC-to-HART Full Flag. Maskable fault. 0h = FIFO_U2H is not full; 1h = FIFO_U2H is full 4 FIFO_U2H_EMPTY_FLAG R 1h FIFO µC-to-HART Empty Flag. Maskable fault. 0h = FIFO_U2H is not empty; 1h = FIFO_U2H is empty 3 CD_DEASSERT R 1h Carrier Detect Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is asserted; 1h = Carrier detect is deasserted 2 CD_ASSERT R 0h Carrier Detect Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is deasserted; 1h = Carrier detect is asserted 1 CTS_DEASSERT R 1h Clear To Send Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is asserted; 1h = Clear to send is deasserted 0 CTS_ASSERT R 0h Clear To Send Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is deasserted; 1h = Clear to send is asserted ADC_FLAGS Register (Offset = 23h) [Reset = 0000h] Return to the Register Map .The limits for Self Diagnostic (SD) Alarm ADC Thresholds are shown in . ADC_FLAGS Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h 8 SD4_FAIL R 0h SD4 (VOUT) Limit Fail 7 SD3_FAIL R 0h SD3 (ZTAT) Limit Fail 6 SD2_FAIL R 0h SD2 (VDD) Limit Fail 5 SD1_FAIL R 0h SD1 (PVDD) Limit Fail 4 SD0_FAIL R 0h SD0 (VREF) Limit Fail 3 TEMP_FAIL R 0h TEMP Limit Fail 2 AIN1_FAIL R 0h AIN1 Limit Fail 1 AIN0_FAIL R 0h AIN0 Limit Fail 0 RESERVED R 0h ADC_AIN0 Register (Offset = 24h) [Reset = 0000h] Return to the Register Map . ADC_AIN0 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN0 ADC_AIN1 Register (Offset = 25h) [Reset = 0000h] Return to the Register Map . ADC_AIN1 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN1 ADC_TEMP Register (Offset = 26h) [Reset = 0000h] Return to the Register Map . ADC_TEMP Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Temperature ADC_SD_MUX Register (Offset = 27h) [Reset = 0000h] Return to the Register Map . ADC_SD_MUX Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Self-Diagnostic (SD) MUX Input ADC_OFFSET Register (Offset = 28h) [Reset = 0000h] Return to the Register Map . ADC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Comparator Offset This value reports the offset measured in the device, and can be used to adjust each conversion value. If ADC_BYP.OFST_BYP_EN is set, then the value in ADC_BYP.DATA is used as the offset. This value is not affected by ADC_BYP. FIFO_H2U_RD Register (Offset = 2Ah) [Reset = 0200h] Return to the Register Map . FIFO_H2U_RD Register Field Descriptions Bit Field Type Reset Description 15-12 LEVEL R 0h LevelCurrent Level of FIFO_H2U, bits [4:1] represented as Level[3:0]. Pre-dequeue. 11 LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO_H2U Level > {Level,1b1}. Pre-dequeue.0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 FULL_FLAG R 0h HART-to-µC FIFO Full Flag. Pre-dequeue. 0h = FIFO_H2U is not full, pre-dequeue 1h = FIFO_H2U is full, pre-dequeue 9 EMPTY_FLAG R 1h HART-to-µC FIFO Empty Flag. Pre-dequeue. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 PARITY R 0h Parity Bit (ODD)Parity bit received with data on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. 7-0 DATA R 0h Data8-bit data received on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. FIFO_STATUS Register (Offset = 2Bh) [Reset = 0202h] Return to the Register Map . The FIFO_STATUS register is provided to allow the user to view the state of both FIFOs without enqueuing or dequeuing data in the FIFO. This also allows the flags to be viewed without disturbing other status bits in the MODEM_STATUS register. This register is provided to enable users to check the FIFO status register without disturbing other functions within the device. FIFO_STATUS Register Field Descriptions Bit Field Type Reset Description 15-12 H2U_LEVEL R 0h HART-to-µC FIFO LevelCurrent level of FIFO_H2U, right shifted 1 bit (>>1) so only even counts are represented. 11 H2U_LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO Level > {Level,1b1}. 0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 H2U_FULL_FLAG R 0h HART-to-µC FIFO Full FlagSet when FIFO is full. 0h = FIFO_H2U is not full 1h = FIFO_H2U is full 9 H2U_EMPTY_FLAG R 1h HART-to-µC Empty FlagSet when FIFO is empty. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 RESERVED R 0h 7-4 U2H_LEVEL R 0h µC-to-HART FIFO LevelCurrent level of FIFO_U2H, right shifted 1 bit (>>1) so only even counts are represented 3 U2H_LEVEL_FLAG R 0h µC-to-HART FIFO Level FlagSet when FIFO_U2H Level < {Level,1b0}. 0h = FIFO_U2H level ≥ {Level, 1b0} 1h = FIFO_U2H level < {Level, 1b0} 2 U2H_FULL_FLAG R 0h µC-to-HART Full FlagSet when FIFO_U2H is full. 0h = FIFO_U2H is not full 1h = FIFO_U2H is full 1 U2H_EMPTY_FLAG R 1h µC-to-HART Empty FlagSet when FIFO_U2H is empty. 0h = FIFO_U2H is not empty 1h = FIFO_U2H is empty 0 RESERVED R 0h DAC_OUT Register (Offset = 2Ch) [Reset = 0000h] Return to the Register Map . DAC_OUT Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R 0h DAC Code Applied to the Analog Circuit ADC_OUT Register (Offset = 2Dh) [Reset = 0000h] Return to the Register Map . ADC_OUT Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Data for Each Conversion Does not include ADC_OFFSET.DATA adjustment. Is not affected by ADC_BYP.DATA. ADC_BYP Register (Offset = 2Eh) [Reset = 0000h] Return to the Register Map . ADC_BYP is shown in ADC_BYP Register Field Descriptions . ADC_BYP Register Field Descriptions Bit Field Type Reset Description 15 DATA_BYP_EN R/W 0h Data Bypass EnableApplies ADC_BYP.DATA to the ADC channel being converted. ADC_OFFSET is ignored. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. If OFST_BYP_EN is also set, DATA_BYP_EN takes priority over OFST_BYP_EN. After a channel is converted, the ADC_BYP.DATA value appears in the readback register for the converted channel and is used to calculate faults. 0h = Data bypass disabled (default) 1h = Data bypass enabled 14 OFST_BYP_EN R/W 0h Offset Bypass EnableOverrides the offset register with the ADC_BYP.DATA value. When using this bit, the ADC_BYP.DATA field is processed as 2's complement. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time.0h = Offset bypass disabled (default) 1h = Offset bypass enabled 13 DIS_GND_SAMP R/W 0h Disable GND SamplingThis bit disables the sampling of GND during SAR activity. The sampling of GND is used to fully discharge the sampling CAP to reduce channel crosstalk. 0h = GND sampling enabled (default) 1h = GND sampling disabled 12 RESERVED R 0h 11-0 DATA R/W 0h Bypass Data FORCE_FAIL Register (Offset = 2Fh) [Reset = 0000h] Return to the Register Map . Force failures for fault detection. FORCE_FAIL Register Field Descriptions Bit Field Type Reset Description 15 CRC_FLT R/W 0h Force CRC Failure on SDO by Inverting the CRC Byte 0h = No force failure of CRC (default) 1h = Force failure of CRC 14 VREF_FLT R/W 0h Force Reference Voltage Failure. Analog signal.0h = No force failure of VREF (default) 1h = Force failure of VREF 13 THERM_ERR_FLT R/W 0h Force Temperature > 130°C Thermal Error. Analog signal.0h = No force temperature > 130°C error (default) 1h = Force temperature > 130°C error 12 THERM_WARN_FLT R/W 0h Force Temperature > 85°C thermal Warning. Analog signal.0h = No force temperature > 85°C warning (default) 1h = Force temperature > 85°C warning 11-10 RESERVED R/W 0h 9 SD4_HI_FLT R/W 0h SD4 (VOUT) High Limit Failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 8 SD4_LO_FLT R/W 0h SD4 (VOUT) Low limit failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 7 SD3_HI_FLT R/W 0h SD3 (ZTAT) High Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 6 SD3_LO_FLT R/W 0h SD3 (ZTAT) Low Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 5 SD2_HI_FLT R/W 0h SD2 (VDD) High Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 4 SD2_LO_FLT R/W 0h SD2 (VDD) Low Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 3 SD1_HI_FLT R/W 0h SD1 (PVDD) High Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 2 SD1_LO_FLT R/W 0h SD1 (PVDD) Low Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 1 SD0_HI_FLT R/W 0h SD0 (VREF) High Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 0 SD0_LO_FLT R/W 0h SD0 (VREF) Low Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) TIMER_CFG_0 Register (Offset = 3Bh) [Reset = 0000h] Return to the Register Map . TIMER Configuration 0. TIMER CONFIG 0 Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED TO 0h 3-2 CLK_SEL R/W 0h Clock SelectSelects the timer clock frequency. 0h = None (default) 1h = 1.2288 MHz 2h = 1.200 kHz 3h = 1.171 Hz 1 INVERT R/W 0h Invert OutputInvert the Timer output. By default, the output is set to 1 when the counter is ≥ SET_TIME (3Dh). 0 ENABLE R/W 0h Timer Enable The CLK_OUT pin must also be configured to output the Timer. TIMER_CFG_1 Register (Offset = 3Ch) [Reset = 0000h] Return to the Register Map . TIMER Configuration 1. TIMER CONFIG 1 Register Field Descriptions Bit Field Type Reset Description 15-0 PERIOD R/W 0h This field defines the period of the timer. The period is the product of (PERIOD + 1) and the clock period of CLK_SEL. For example, CLK_SEL = 2h (1200 Hz), The period is (PERIOD + 1) × 853 ms. TIMER_CFG_2 Register (Offset = 3Dh) [Reset = 0000h] Return to the Register Map . TIMER Configuration 2. TIMER CONFIG 2 Register Field Descriptions Bit Field Type Reset Description 15-0 SET_TIME R/W 0h The SET_TIME determine when the output of the timer goes high. The bits define the duty cycle of the timer (PERIOD – SET_TIME). The timer starts out as 0 and transitions to 1 when the SET_TIME is met. The polarity of the timer can be inverted using the TIMER_CFG_0.INVERT bit. CRC_RD Register (Offset = 3Eh) [Reset = 0000h] Return to the Register Map . CRC read. CRC Read Register Field Descriptions Bit Field Type Reset Description 15-0 CRC R/O 0h Calculated CRC for RBIST or SHADOWLOAD. Final value is calculated internally. This value changes while RBIST or shadow load are running. RBIST_CRC Register (Offset = 3Fh) [Reset = 0000h] Return to the Register Map . RBIST CRC. RBIST CRC Register Field Descriptions Bit Field Type Reset Description 15-0 RBIST CRC R/W 0h Calculated CRC for Register RBIST Register Maps #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/TABLE_ILZ_TX1_TPB lists the memory-mapped registers for the AFEx82H1 registers. Consider all register offset addresses not listed in #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/TABLE_ILZ_TX1_TPB as reserved locations; do not modify these register contents. Register Map ADDR (HEX) REGISTER BIT DESCRIPTION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h NOP NOP [15:0] 01h DAC_DATA DATA [15:0] 02h CONFIG CRC_ERR_CNT [1:0] CLKO [3:0] UBM_IRQ_EN IRQ_PIN_EN CLR_PIN_EN UART_DIS UART_BAUD CRC_EN IRQ_POL IRQ_LVL DSDO FSDO 03h DAC_CFG RESERVED PD SR_CLK [2:0] SR_STEP [2:0] SR_EN SR_MODE RESERVED CLR RESERVED 04h DAC_GAIN GAIN [15:0] 05h DAC_OFFSET OFFSET [15:0] 06h DAC_CLR_CODE CODE [15:0] 07h RESET RESERVED SW_RST [7:0] 08h ADC_CFG BUF_PD HYST [6:0] FLT_CNT [2:0] AIN_RANGE EOC_PER_CH CONV_RATE [1:0] DIRECT_MODE 09h ADC_INDEX_CFG RESERVED STOP [3:0] START [3:0] 0Ah TRIGGER RESERVED RBIST MBIST SHADOWLOAD ADC 0Bh SPECIAL_CFG #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-DDD5E850-D3C4-44CC-92C9-81DB08FE3C68 RESERVED OTP_LOAD_SW_RST ALMV_POL AIN1_ENB 0Eh MODEM_CFG Tx2200Hz RESERVED DUPLEX_EXT RX_HORD_EN RX_EXTFILT_EN TxRES TxAMP [4:0] HART_EN DUPLEX TxHPD RTS 0Fh FIFO_CFG RESERVED FIFO_H2U_FLUSH FIFO_U2H_FLUSH H2U_LEVEL_SET [3:0] U2H_LEVEL_SET [3:0] 10h ALARM_ACT SD_FLT [1:0] TEMP_FLT [1:0] AIN1_FLT [1:0] AIN0_FLT [1:0] CRC_WDT_FLT [1:0] VREF_FLT [1:0] THERM_ERR_FLT [1:0] THERM_WARN_FLT [1:0] 11h WDT RESERVED WDT_UP [2:0] WDT_LO [1:0] WDT_EN 12h AIN0_THRESHOLD Hi [7:0] Lo [7:0] 13h AIN1_THRESHOLD Hi [7:0] Lo [7:0] 14h TEMP_THRESHOLD Hi [7:0] Lo [7:0] 15h FIFO_U2H_WR RESERVED PARITY DATA [7:0] 16h UBM #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-D0D7F115-E0CF-4F1A-A6B9-B372A61327B8 RESERVED REG_MODE 18h SCRATCH DATA [15:0] 19h CHIP_ID_LSB ID [15:0] 1Ah CHIP_ID_MSB ID [15:0] 1Bh GPIO_CFG RESERVED EN [6:0] RESERVED ODE [6:0] 1Ch GPIO RESERVED DATA [6:0] 1Dh ALARM_STATUS_MASK RESERVED SD_FLT OSC_FAIL RESERVED OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 1Eh GEN_STATUS_MASK RESERVED BIST_DONE BIST_FAIL RESERVED SR_BUSYn ADC_EOC RESERVED BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 1Fh MODEM_STATUS_MASK RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 20h ALARM_STATUS GEN_IRQ MODEM_IRQ SD_FLT OSC_FAIL CRC_CNT [1:0] OTP_LOADEDn OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 21h GEN_STATUS ALARM_IRQ MODEM_IRQ RESERVED OTP_BUSY BIST_ MODE BIST_DONE BIST_FAIL RESET SR_BUSYn ADC_EOC ADC_BUSY PVDD_HI BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 22h MODEM_STATUS ALARM_IRQ GEN_IRQ RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 23h ADC_FLAGS RESERVED SD4_FAIL SD3_FAIL SD2_FAIL SD1_FAIL SD0_FAIL TEMP_FAIL AIN1_FAIL AIN0_FAIL RESERVED 24h ADC_AIN0 RESERVED DATA [11:0] 25h ADC_AIN1 RESERVED DATA [11:0] 26h ADC_TEMP RESERVED DATA [11:0] 27h ADC_SD_MUX RESERVED DATA [11:0] 28h ADC_OFFSET RESERVED DATA [11:0] 2Ah FIFO_H2U_RD LEVEL [3:0] LEVEL_FLAG FULL_FLAG EMPTY_FLAG PARITY DATA [7:0] 2Bh FIFO_STATUS H2U_LEVEL [3:0] H2U_LEVEL_FLAG H2U_FULL_FLAG H2U_EMPTY_FLAG RESERVED U2H_LEVEL [3:0] U2H_LEVEL_FLAG U2H_FULL_FLAG U2H_EMPTY_FLAG RESERVED 2Ch DAC_OUT DATA [15:0] 2Dh ADC_OUT RESERVED DATA [11:0] 2Eh ADC_BYP DATA_BYP_EN OFST_BYP_EN DIS_GND_SAMP RESERVED DATA [11:0] 2Fh FORCE_FAIL CRC_FLT VREF_FLT THERM_ERR_FLT THERM_WARN_FLT RESERVED SD4_HI_FLT SD4_LO_FLT SD3_HI_FLT SD3_LO_FLT SD2_HI_FLT SD2_LO_FLT SD1_HI_FLT SD1_LO_FLT SD0_HI_FLT SD0_LO_FLT 3Bh TIMER_CFG_0 RESERVED CLK_SEL [1:0] INVERT ENABLE 3Ch TIMER_CFG_1 PERIOD [15:0] 3Dh TIMER_CFG_2 SET_TIME [15:0] 3Eh CRC_RD CRC [15:0] 3Fh RBIST_CRC CRC [15:0] The SPECIAL_CFG register can only be reset with POR, and does not respond to the RESET pin or SW_RST command. The UBM register can only be accessed with a UBM command. #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/TABLE_ILZ_TX1_TPB lists the memory-mapped registers for the AFEx82H1 registers. Consider all register offset addresses not listed in #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/TABLE_ILZ_TX1_TPB as reserved locations; do not modify these register contents. Register Map ADDR (HEX) REGISTER BIT DESCRIPTION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h NOP NOP [15:0] 01h DAC_DATA DATA [15:0] 02h CONFIG CRC_ERR_CNT [1:0] CLKO [3:0] UBM_IRQ_EN IRQ_PIN_EN CLR_PIN_EN UART_DIS UART_BAUD CRC_EN IRQ_POL IRQ_LVL DSDO FSDO 03h DAC_CFG RESERVED PD SR_CLK [2:0] SR_STEP [2:0] SR_EN SR_MODE RESERVED CLR RESERVED 04h DAC_GAIN GAIN [15:0] 05h DAC_OFFSET OFFSET [15:0] 06h DAC_CLR_CODE CODE [15:0] 07h RESET RESERVED SW_RST [7:0] 08h ADC_CFG BUF_PD HYST [6:0] FLT_CNT [2:0] AIN_RANGE EOC_PER_CH CONV_RATE [1:0] DIRECT_MODE 09h ADC_INDEX_CFG RESERVED STOP [3:0] START [3:0] 0Ah TRIGGER RESERVED RBIST MBIST SHADOWLOAD ADC 0Bh SPECIAL_CFG #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-DDD5E850-D3C4-44CC-92C9-81DB08FE3C68 RESERVED OTP_LOAD_SW_RST ALMV_POL AIN1_ENB 0Eh MODEM_CFG Tx2200Hz RESERVED DUPLEX_EXT RX_HORD_EN RX_EXTFILT_EN TxRES TxAMP [4:0] HART_EN DUPLEX TxHPD RTS 0Fh FIFO_CFG RESERVED FIFO_H2U_FLUSH FIFO_U2H_FLUSH H2U_LEVEL_SET [3:0] U2H_LEVEL_SET [3:0] 10h ALARM_ACT SD_FLT [1:0] TEMP_FLT [1:0] AIN1_FLT [1:0] AIN0_FLT [1:0] CRC_WDT_FLT [1:0] VREF_FLT [1:0] THERM_ERR_FLT [1:0] THERM_WARN_FLT [1:0] 11h WDT RESERVED WDT_UP [2:0] WDT_LO [1:0] WDT_EN 12h AIN0_THRESHOLD Hi [7:0] Lo [7:0] 13h AIN1_THRESHOLD Hi [7:0] Lo [7:0] 14h TEMP_THRESHOLD Hi [7:0] Lo [7:0] 15h FIFO_U2H_WR RESERVED PARITY DATA [7:0] 16h UBM #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-D0D7F115-E0CF-4F1A-A6B9-B372A61327B8 RESERVED REG_MODE 18h SCRATCH DATA [15:0] 19h CHIP_ID_LSB ID [15:0] 1Ah CHIP_ID_MSB ID [15:0] 1Bh GPIO_CFG RESERVED EN [6:0] RESERVED ODE [6:0] 1Ch GPIO RESERVED DATA [6:0] 1Dh ALARM_STATUS_MASK RESERVED SD_FLT OSC_FAIL RESERVED OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 1Eh GEN_STATUS_MASK RESERVED BIST_DONE BIST_FAIL RESERVED SR_BUSYn ADC_EOC RESERVED BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 1Fh MODEM_STATUS_MASK RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 20h ALARM_STATUS GEN_IRQ MODEM_IRQ SD_FLT OSC_FAIL CRC_CNT [1:0] OTP_LOADEDn OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 21h GEN_STATUS ALARM_IRQ MODEM_IRQ RESERVED OTP_BUSY BIST_ MODE BIST_DONE BIST_FAIL RESET SR_BUSYn ADC_EOC ADC_BUSY PVDD_HI BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 22h MODEM_STATUS ALARM_IRQ GEN_IRQ RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 23h ADC_FLAGS RESERVED SD4_FAIL SD3_FAIL SD2_FAIL SD1_FAIL SD0_FAIL TEMP_FAIL AIN1_FAIL AIN0_FAIL RESERVED 24h ADC_AIN0 RESERVED DATA [11:0] 25h ADC_AIN1 RESERVED DATA [11:0] 26h ADC_TEMP RESERVED DATA [11:0] 27h ADC_SD_MUX RESERVED DATA [11:0] 28h ADC_OFFSET RESERVED DATA [11:0] 2Ah FIFO_H2U_RD LEVEL [3:0] LEVEL_FLAG FULL_FLAG EMPTY_FLAG PARITY DATA [7:0] 2Bh FIFO_STATUS H2U_LEVEL [3:0] H2U_LEVEL_FLAG H2U_FULL_FLAG H2U_EMPTY_FLAG RESERVED U2H_LEVEL [3:0] U2H_LEVEL_FLAG U2H_FULL_FLAG U2H_EMPTY_FLAG RESERVED 2Ch DAC_OUT DATA [15:0] 2Dh ADC_OUT RESERVED DATA [11:0] 2Eh ADC_BYP DATA_BYP_EN OFST_BYP_EN DIS_GND_SAMP RESERVED DATA [11:0] 2Fh FORCE_FAIL CRC_FLT VREF_FLT THERM_ERR_FLT THERM_WARN_FLT RESERVED SD4_HI_FLT SD4_LO_FLT SD3_HI_FLT SD3_LO_FLT SD2_HI_FLT SD2_LO_FLT SD1_HI_FLT SD1_LO_FLT SD0_HI_FLT SD0_LO_FLT 3Bh TIMER_CFG_0 RESERVED CLK_SEL [1:0] INVERT ENABLE 3Ch TIMER_CFG_1 PERIOD [15:0] 3Dh TIMER_CFG_2 SET_TIME [15:0] 3Eh CRC_RD CRC [15:0] 3Fh RBIST_CRC CRC [15:0] The SPECIAL_CFG register can only be reset with POR, and does not respond to the RESET pin or SW_RST command. The UBM register can only be accessed with a UBM command. #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/TABLE_ILZ_TX1_TPB lists the memory-mapped registers for the AFEx82H1 registers. Consider all register offset addresses not listed in #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/TABLE_ILZ_TX1_TPB as reserved locations; do not modify these register contents.#GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/TABLE_ILZ_TX1_TPBAFEx82H1#GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/TABLE_ILZ_TX1_TPB Register Map ADDR (HEX) REGISTER BIT DESCRIPTION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h NOP NOP [15:0] 01h DAC_DATA DATA [15:0] 02h CONFIG CRC_ERR_CNT [1:0] CLKO [3:0] UBM_IRQ_EN IRQ_PIN_EN CLR_PIN_EN UART_DIS UART_BAUD CRC_EN IRQ_POL IRQ_LVL DSDO FSDO 03h DAC_CFG RESERVED PD SR_CLK [2:0] SR_STEP [2:0] SR_EN SR_MODE RESERVED CLR RESERVED 04h DAC_GAIN GAIN [15:0] 05h DAC_OFFSET OFFSET [15:0] 06h DAC_CLR_CODE CODE [15:0] 07h RESET RESERVED SW_RST [7:0] 08h ADC_CFG BUF_PD HYST [6:0] FLT_CNT [2:0] AIN_RANGE EOC_PER_CH CONV_RATE [1:0] DIRECT_MODE 09h ADC_INDEX_CFG RESERVED STOP [3:0] START [3:0] 0Ah TRIGGER RESERVED RBIST MBIST SHADOWLOAD ADC 0Bh SPECIAL_CFG #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-DDD5E850-D3C4-44CC-92C9-81DB08FE3C68 RESERVED OTP_LOAD_SW_RST ALMV_POL AIN1_ENB 0Eh MODEM_CFG Tx2200Hz RESERVED DUPLEX_EXT RX_HORD_EN RX_EXTFILT_EN TxRES TxAMP [4:0] HART_EN DUPLEX TxHPD RTS 0Fh FIFO_CFG RESERVED FIFO_H2U_FLUSH FIFO_U2H_FLUSH H2U_LEVEL_SET [3:0] U2H_LEVEL_SET [3:0] 10h ALARM_ACT SD_FLT [1:0] TEMP_FLT [1:0] AIN1_FLT [1:0] AIN0_FLT [1:0] CRC_WDT_FLT [1:0] VREF_FLT [1:0] THERM_ERR_FLT [1:0] THERM_WARN_FLT [1:0] 11h WDT RESERVED WDT_UP [2:0] WDT_LO [1:0] WDT_EN 12h AIN0_THRESHOLD Hi [7:0] Lo [7:0] 13h AIN1_THRESHOLD Hi [7:0] Lo [7:0] 14h TEMP_THRESHOLD Hi [7:0] Lo [7:0] 15h FIFO_U2H_WR RESERVED PARITY DATA [7:0] 16h UBM #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-D0D7F115-E0CF-4F1A-A6B9-B372A61327B8 RESERVED REG_MODE 18h SCRATCH DATA [15:0] 19h CHIP_ID_LSB ID [15:0] 1Ah CHIP_ID_MSB ID [15:0] 1Bh GPIO_CFG RESERVED EN [6:0] RESERVED ODE [6:0] 1Ch GPIO RESERVED DATA [6:0] 1Dh ALARM_STATUS_MASK RESERVED SD_FLT OSC_FAIL RESERVED OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 1Eh GEN_STATUS_MASK RESERVED BIST_DONE BIST_FAIL RESERVED SR_BUSYn ADC_EOC RESERVED BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 1Fh MODEM_STATUS_MASK RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 20h ALARM_STATUS GEN_IRQ MODEM_IRQ SD_FLT OSC_FAIL CRC_CNT [1:0] OTP_LOADEDn OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 21h GEN_STATUS ALARM_IRQ MODEM_IRQ RESERVED OTP_BUSY BIST_ MODE BIST_DONE BIST_FAIL RESET SR_BUSYn ADC_EOC ADC_BUSY PVDD_HI BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 22h MODEM_STATUS ALARM_IRQ GEN_IRQ RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 23h ADC_FLAGS RESERVED SD4_FAIL SD3_FAIL SD2_FAIL SD1_FAIL SD0_FAIL TEMP_FAIL AIN1_FAIL AIN0_FAIL RESERVED 24h ADC_AIN0 RESERVED DATA [11:0] 25h ADC_AIN1 RESERVED DATA [11:0] 26h ADC_TEMP RESERVED DATA [11:0] 27h ADC_SD_MUX RESERVED DATA [11:0] 28h ADC_OFFSET RESERVED DATA [11:0] 2Ah FIFO_H2U_RD LEVEL [3:0] LEVEL_FLAG FULL_FLAG EMPTY_FLAG PARITY DATA [7:0] 2Bh FIFO_STATUS H2U_LEVEL [3:0] H2U_LEVEL_FLAG H2U_FULL_FLAG H2U_EMPTY_FLAG RESERVED U2H_LEVEL [3:0] U2H_LEVEL_FLAG U2H_FULL_FLAG U2H_EMPTY_FLAG RESERVED 2Ch DAC_OUT DATA [15:0] 2Dh ADC_OUT RESERVED DATA [11:0] 2Eh ADC_BYP DATA_BYP_EN OFST_BYP_EN DIS_GND_SAMP RESERVED DATA [11:0] 2Fh FORCE_FAIL CRC_FLT VREF_FLT THERM_ERR_FLT THERM_WARN_FLT RESERVED SD4_HI_FLT SD4_LO_FLT SD3_HI_FLT SD3_LO_FLT SD2_HI_FLT SD2_LO_FLT SD1_HI_FLT SD1_LO_FLT SD0_HI_FLT SD0_LO_FLT 3Bh TIMER_CFG_0 RESERVED CLK_SEL [1:0] INVERT ENABLE 3Ch TIMER_CFG_1 PERIOD [15:0] 3Dh TIMER_CFG_2 SET_TIME [15:0] 3Eh CRC_RD CRC [15:0] 3Fh RBIST_CRC CRC [15:0] Register Map ADDR (HEX) REGISTER BIT DESCRIPTION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h NOP NOP [15:0] 01h DAC_DATA DATA [15:0] 02h CONFIG CRC_ERR_CNT [1:0] CLKO [3:0] UBM_IRQ_EN IRQ_PIN_EN CLR_PIN_EN UART_DIS UART_BAUD CRC_EN IRQ_POL IRQ_LVL DSDO FSDO 03h DAC_CFG RESERVED PD SR_CLK [2:0] SR_STEP [2:0] SR_EN SR_MODE RESERVED CLR RESERVED 04h DAC_GAIN GAIN [15:0] 05h DAC_OFFSET OFFSET [15:0] 06h DAC_CLR_CODE CODE [15:0] 07h RESET RESERVED SW_RST [7:0] 08h ADC_CFG BUF_PD HYST [6:0] FLT_CNT [2:0] AIN_RANGE EOC_PER_CH CONV_RATE [1:0] DIRECT_MODE 09h ADC_INDEX_CFG RESERVED STOP [3:0] START [3:0] 0Ah TRIGGER RESERVED RBIST MBIST SHADOWLOAD ADC 0Bh SPECIAL_CFG #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-DDD5E850-D3C4-44CC-92C9-81DB08FE3C68 RESERVED OTP_LOAD_SW_RST ALMV_POL AIN1_ENB 0Eh MODEM_CFG Tx2200Hz RESERVED DUPLEX_EXT RX_HORD_EN RX_EXTFILT_EN TxRES TxAMP [4:0] HART_EN DUPLEX TxHPD RTS 0Fh FIFO_CFG RESERVED FIFO_H2U_FLUSH FIFO_U2H_FLUSH H2U_LEVEL_SET [3:0] U2H_LEVEL_SET [3:0] 10h ALARM_ACT SD_FLT [1:0] TEMP_FLT [1:0] AIN1_FLT [1:0] AIN0_FLT [1:0] CRC_WDT_FLT [1:0] VREF_FLT [1:0] THERM_ERR_FLT [1:0] THERM_WARN_FLT [1:0] 11h WDT RESERVED WDT_UP [2:0] WDT_LO [1:0] WDT_EN 12h AIN0_THRESHOLD Hi [7:0] Lo [7:0] 13h AIN1_THRESHOLD Hi [7:0] Lo [7:0] 14h TEMP_THRESHOLD Hi [7:0] Lo [7:0] 15h FIFO_U2H_WR RESERVED PARITY DATA [7:0] 16h UBM #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-D0D7F115-E0CF-4F1A-A6B9-B372A61327B8 RESERVED REG_MODE 18h SCRATCH DATA [15:0] 19h CHIP_ID_LSB ID [15:0] 1Ah CHIP_ID_MSB ID [15:0] 1Bh GPIO_CFG RESERVED EN [6:0] RESERVED ODE [6:0] 1Ch GPIO RESERVED DATA [6:0] 1Dh ALARM_STATUS_MASK RESERVED SD_FLT OSC_FAIL RESERVED OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 1Eh GEN_STATUS_MASK RESERVED BIST_DONE BIST_FAIL RESERVED SR_BUSYn ADC_EOC RESERVED BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 1Fh MODEM_STATUS_MASK RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 20h ALARM_STATUS GEN_IRQ MODEM_IRQ SD_FLT OSC_FAIL CRC_CNT [1:0] OTP_LOADEDn OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 21h GEN_STATUS ALARM_IRQ MODEM_IRQ RESERVED OTP_BUSY BIST_ MODE BIST_DONE BIST_FAIL RESET SR_BUSYn ADC_EOC ADC_BUSY PVDD_HI BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 22h MODEM_STATUS ALARM_IRQ GEN_IRQ RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 23h ADC_FLAGS RESERVED SD4_FAIL SD3_FAIL SD2_FAIL SD1_FAIL SD0_FAIL TEMP_FAIL AIN1_FAIL AIN0_FAIL RESERVED 24h ADC_AIN0 RESERVED DATA [11:0] 25h ADC_AIN1 RESERVED DATA [11:0] 26h ADC_TEMP RESERVED DATA [11:0] 27h ADC_SD_MUX RESERVED DATA [11:0] 28h ADC_OFFSET RESERVED DATA [11:0] 2Ah FIFO_H2U_RD LEVEL [3:0] LEVEL_FLAG FULL_FLAG EMPTY_FLAG PARITY DATA [7:0] 2Bh FIFO_STATUS H2U_LEVEL [3:0] H2U_LEVEL_FLAG H2U_FULL_FLAG H2U_EMPTY_FLAG RESERVED U2H_LEVEL [3:0] U2H_LEVEL_FLAG U2H_FULL_FLAG U2H_EMPTY_FLAG RESERVED 2Ch DAC_OUT DATA [15:0] 2Dh ADC_OUT RESERVED DATA [11:0] 2Eh ADC_BYP DATA_BYP_EN OFST_BYP_EN DIS_GND_SAMP RESERVED DATA [11:0] 2Fh FORCE_FAIL CRC_FLT VREF_FLT THERM_ERR_FLT THERM_WARN_FLT RESERVED SD4_HI_FLT SD4_LO_FLT SD3_HI_FLT SD3_LO_FLT SD2_HI_FLT SD2_LO_FLT SD1_HI_FLT SD1_LO_FLT SD0_HI_FLT SD0_LO_FLT 3Bh TIMER_CFG_0 RESERVED CLK_SEL [1:0] INVERT ENABLE 3Ch TIMER_CFG_1 PERIOD [15:0] 3Dh TIMER_CFG_2 SET_TIME [15:0] 3Eh CRC_RD CRC [15:0] 3Fh RBIST_CRC CRC [15:0] ADDR (HEX) REGISTER BIT DESCRIPTION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR (HEX) REGISTER BIT DESCRIPTION ADDR (HEX)REGISTERBIT DESCRIPTION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1514131211109876543210 00h NOP NOP [15:0] 01h DAC_DATA DATA [15:0] 02h CONFIG CRC_ERR_CNT [1:0] CLKO [3:0] UBM_IRQ_EN IRQ_PIN_EN CLR_PIN_EN UART_DIS UART_BAUD CRC_EN IRQ_POL IRQ_LVL DSDO FSDO 03h DAC_CFG RESERVED PD SR_CLK [2:0] SR_STEP [2:0] SR_EN SR_MODE RESERVED CLR RESERVED 04h DAC_GAIN GAIN [15:0] 05h DAC_OFFSET OFFSET [15:0] 06h DAC_CLR_CODE CODE [15:0] 07h RESET RESERVED SW_RST [7:0] 08h ADC_CFG BUF_PD HYST [6:0] FLT_CNT [2:0] AIN_RANGE EOC_PER_CH CONV_RATE [1:0] DIRECT_MODE 09h ADC_INDEX_CFG RESERVED STOP [3:0] START [3:0] 0Ah TRIGGER RESERVED RBIST MBIST SHADOWLOAD ADC 0Bh SPECIAL_CFG #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-DDD5E850-D3C4-44CC-92C9-81DB08FE3C68 RESERVED OTP_LOAD_SW_RST ALMV_POL AIN1_ENB 0Eh MODEM_CFG Tx2200Hz RESERVED DUPLEX_EXT RX_HORD_EN RX_EXTFILT_EN TxRES TxAMP [4:0] HART_EN DUPLEX TxHPD RTS 0Fh FIFO_CFG RESERVED FIFO_H2U_FLUSH FIFO_U2H_FLUSH H2U_LEVEL_SET [3:0] U2H_LEVEL_SET [3:0] 10h ALARM_ACT SD_FLT [1:0] TEMP_FLT [1:0] AIN1_FLT [1:0] AIN0_FLT [1:0] CRC_WDT_FLT [1:0] VREF_FLT [1:0] THERM_ERR_FLT [1:0] THERM_WARN_FLT [1:0] 11h WDT RESERVED WDT_UP [2:0] WDT_LO [1:0] WDT_EN 12h AIN0_THRESHOLD Hi [7:0] Lo [7:0] 13h AIN1_THRESHOLD Hi [7:0] Lo [7:0] 14h TEMP_THRESHOLD Hi [7:0] Lo [7:0] 15h FIFO_U2H_WR RESERVED PARITY DATA [7:0] 16h UBM #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-D0D7F115-E0CF-4F1A-A6B9-B372A61327B8 RESERVED REG_MODE 18h SCRATCH DATA [15:0] 19h CHIP_ID_LSB ID [15:0] 1Ah CHIP_ID_MSB ID [15:0] 1Bh GPIO_CFG RESERVED EN [6:0] RESERVED ODE [6:0] 1Ch GPIO RESERVED DATA [6:0] 1Dh ALARM_STATUS_MASK RESERVED SD_FLT OSC_FAIL RESERVED OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 1Eh GEN_STATUS_MASK RESERVED BIST_DONE BIST_FAIL RESERVED SR_BUSYn ADC_EOC RESERVED BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 1Fh MODEM_STATUS_MASK RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 20h ALARM_STATUS GEN_IRQ MODEM_IRQ SD_FLT OSC_FAIL CRC_CNT [1:0] OTP_LOADEDn OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 21h GEN_STATUS ALARM_IRQ MODEM_IRQ RESERVED OTP_BUSY BIST_ MODE BIST_DONE BIST_FAIL RESET SR_BUSYn ADC_EOC ADC_BUSY PVDD_HI BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 22h MODEM_STATUS ALARM_IRQ GEN_IRQ RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 23h ADC_FLAGS RESERVED SD4_FAIL SD3_FAIL SD2_FAIL SD1_FAIL SD0_FAIL TEMP_FAIL AIN1_FAIL AIN0_FAIL RESERVED 24h ADC_AIN0 RESERVED DATA [11:0] 25h ADC_AIN1 RESERVED DATA [11:0] 26h ADC_TEMP RESERVED DATA [11:0] 27h ADC_SD_MUX RESERVED DATA [11:0] 28h ADC_OFFSET RESERVED DATA [11:0] 2Ah FIFO_H2U_RD LEVEL [3:0] LEVEL_FLAG FULL_FLAG EMPTY_FLAG PARITY DATA [7:0] 2Bh FIFO_STATUS H2U_LEVEL [3:0] H2U_LEVEL_FLAG H2U_FULL_FLAG H2U_EMPTY_FLAG RESERVED U2H_LEVEL [3:0] U2H_LEVEL_FLAG U2H_FULL_FLAG U2H_EMPTY_FLAG RESERVED 2Ch DAC_OUT DATA [15:0] 2Dh ADC_OUT RESERVED DATA [11:0] 2Eh ADC_BYP DATA_BYP_EN OFST_BYP_EN DIS_GND_SAMP RESERVED DATA [11:0] 2Fh FORCE_FAIL CRC_FLT VREF_FLT THERM_ERR_FLT THERM_WARN_FLT RESERVED SD4_HI_FLT SD4_LO_FLT SD3_HI_FLT SD3_LO_FLT SD2_HI_FLT SD2_LO_FLT SD1_HI_FLT SD1_LO_FLT SD0_HI_FLT SD0_LO_FLT 3Bh TIMER_CFG_0 RESERVED CLK_SEL [1:0] INVERT ENABLE 3Ch TIMER_CFG_1 PERIOD [15:0] 3Dh TIMER_CFG_2 SET_TIME [15:0] 3Eh CRC_RD CRC [15:0] 3Fh RBIST_CRC CRC [15:0] 00h NOP NOP [15:0] 00h NOP NOPNOP [15:0] 01h DAC_DATA DATA [15:0] 01h DAC_DATA DAC_DATADATA [15:0] 02h CONFIG CRC_ERR_CNT [1:0] CLKO [3:0] UBM_IRQ_EN IRQ_PIN_EN CLR_PIN_EN UART_DIS UART_BAUD CRC_EN IRQ_POL IRQ_LVL DSDO FSDO 02h CONFIG CONFIGCRC_ERR_CNT [1:0]CLKO [3:0]UBM_IRQ_ENIRQ_PIN_ENCLR_PIN_ENUART_DISUART_BAUDCRC_ENIRQ_POLIRQ_LVLDSDOFSDO 03h DAC_CFG RESERVED PD SR_CLK [2:0] SR_STEP [2:0] SR_EN SR_MODE RESERVED CLR RESERVED 03h DAC_CFG DAC_CFGRESERVEDPDSR_CLK [2:0]SR_STEP [2:0]SR_ENSR_MODERESERVEDCLRRESERVED 04h DAC_GAIN GAIN [15:0] 04h DAC_GAIN DAC_GAINGAIN [15:0] 05h DAC_OFFSET OFFSET [15:0] 05h DAC_OFFSET DAC_OFFSETOFFSET [15:0] 06h DAC_CLR_CODE CODE [15:0] 06h DAC_CLR_CODE DAC_CLR_CODECODE [15:0] 07h RESET RESERVED SW_RST [7:0] 07h RESET RESETRESERVEDSW_RST [7:0] 08h ADC_CFG BUF_PD HYST [6:0] FLT_CNT [2:0] AIN_RANGE EOC_PER_CH CONV_RATE [1:0] DIRECT_MODE 08h ADC_CFG ADC_CFGBUF_PDHYST [6:0]FLT_CNT [2:0]AIN_RANGEEOC_PER_CHCONV_RATE [1:0]DIRECT_MODE 09h ADC_INDEX_CFG RESERVED STOP [3:0] START [3:0] 09h ADC_INDEX_CFG ADC_INDEX_CFGRESERVEDSTOP [3:0]START [3:0] 0Ah TRIGGER RESERVED RBIST MBIST SHADOWLOAD ADC 0Ah TRIGGER TRIGGERRESERVEDRBISTMBISTSHADOWLOADADC 0Bh SPECIAL_CFG #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-DDD5E850-D3C4-44CC-92C9-81DB08FE3C68 RESERVED OTP_LOAD_SW_RST ALMV_POL AIN1_ENB 0Bh SPECIAL_CFG #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-DDD5E850-D3C4-44CC-92C9-81DB08FE3C68 SPECIAL_CFG#GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-DDD5E850-D3C4-44CC-92C9-81DB08FE3C68RESERVEDOTP_LOAD_SW_RSTALMV_POLAIN1_ENB 0Eh MODEM_CFG Tx2200Hz RESERVED DUPLEX_EXT RX_HORD_EN RX_EXTFILT_EN TxRES TxAMP [4:0] HART_EN DUPLEX TxHPD RTS 0Eh MODEM_CFG MODEM_CFGTx2200HzRESERVEDDUPLEX_EXTRX_HORD_ENRX_EXTFILT_ENTxRESTxAMP [4:0]HART_ENDUPLEXTxHPDRTS 0Fh FIFO_CFG RESERVED FIFO_H2U_FLUSH FIFO_U2H_FLUSH H2U_LEVEL_SET [3:0] U2H_LEVEL_SET [3:0] 0Fh FIFO_CFG FIFO_CFGRESERVEDFIFO_H2U_FLUSHFIFO_U2H_FLUSHH2U_LEVEL_SET [3:0]U2H_LEVEL_SET [3:0] 10h ALARM_ACT SD_FLT [1:0] TEMP_FLT [1:0] AIN1_FLT [1:0] AIN0_FLT [1:0] CRC_WDT_FLT [1:0] VREF_FLT [1:0] THERM_ERR_FLT [1:0] THERM_WARN_FLT [1:0] 10h ALARM_ACT ALARM_ACTSD_FLT [1:0]TEMP_FLT [1:0]AIN1_FLT [1:0]AIN0_FLT [1:0]CRC_WDT_FLT [1:0]VREF_FLT [1:0]THERM_ERR_FLT [1:0]THERM_WARN_FLT [1:0] 11h WDT RESERVED WDT_UP [2:0] WDT_LO [1:0] WDT_EN 11h WDT WDTRESERVEDWDT_UP [2:0]WDT_LO [1:0]WDT_EN 12h AIN0_THRESHOLD Hi [7:0] Lo [7:0] 12h AIN0_THRESHOLD AIN0_THRESHOLDHi [7:0]Lo [7:0] 13h AIN1_THRESHOLD Hi [7:0] Lo [7:0] 13h AIN1_THRESHOLD AIN1_THRESHOLDHi [7:0]Lo [7:0] 14h TEMP_THRESHOLD Hi [7:0] Lo [7:0] 14h TEMP_THRESHOLD TEMP_THRESHOLDHi [7:0]Lo [7:0] 15h FIFO_U2H_WR RESERVED PARITY DATA [7:0] 15h FIFO_U2H_WR FIFO_U2H_WRRESERVEDPARITYDATA [7:0] 16h UBM #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-D0D7F115-E0CF-4F1A-A6B9-B372A61327B8 RESERVED REG_MODE 16h UBM #GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-D0D7F115-E0CF-4F1A-A6B9-B372A61327B8 UBM#GUID-97A62E66-E991-4083-B8DE-7E1896BD1F9E/GUID-D0D7F115-E0CF-4F1A-A6B9-B372A61327B8RESERVEDREG_MODE 18h SCRATCH DATA [15:0] 18h SCRATCH SCRATCHDATA [15:0] 19h CHIP_ID_LSB ID [15:0] 19h CHIP_ID_LSB CHIP_ID_LSBID [15:0] 1Ah CHIP_ID_MSB ID [15:0] 1Ah CHIP_ID_MSB CHIP_ID_MSBID [15:0] 1Bh GPIO_CFG RESERVED EN [6:0] RESERVED ODE [6:0] 1Bh GPIO_CFG GPIO_CFGRESERVEDEN [6:0]RESERVEDODE [6:0] 1Ch GPIO RESERVED DATA [6:0] 1Ch GPIO GPIORESERVEDDATA [6:0] 1Dh ALARM_STATUS_MASK RESERVED SD_FLT OSC_FAIL RESERVED OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 1Dh ALARM_STATUS_MASK ALARM_STATUS_MASKRESERVEDSD_FLTOSC_FAILRESERVEDOTP_CRC_ERRCRC_FLTWD_FLTVREF_FLTADC_AIN1_FLTADC_AIN0_FLTADC_TEMP_FLTTHERM_ERR_FLTTHERM_WARN_FLT 1Eh GEN_STATUS_MASK RESERVED BIST_DONE BIST_FAIL RESERVED SR_BUSYn ADC_EOC RESERVED BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 1Eh GEN_STATUS_MASK GEN_STATUS_MASKRESERVEDBIST_DONEBIST_FAILRESERVEDSR_BUSYnADC_EOCRESERVEDBREAK_FRAME_ERRBREAK_PARITY_ERRUART_FRAME_ERRUART_PARITY_ERR 1Fh MODEM_STATUS_MASK RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 1Fh MODEM_STATUS_MASK MODEM_STATUS_MASKRESERVEDGAP_ERRFRAME_ERRPARITY_ERRFIFO_H2U_LEVEL_FLAGFIFO_H2U_FULL_FLAGFIFO_H2U_EMPTY_FLAGFIFO_U2H_LEVEL_FLAGFIFO_U2H_FULL_FLAGFIFO_U2H_EMPTY_FLAGCD_DEASSERTCD_ASSERTCTS_DEASSERTCTS_ASSERT 20h ALARM_STATUS GEN_IRQ MODEM_IRQ SD_FLT OSC_FAIL CRC_CNT [1:0] OTP_LOADEDn OTP_CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_AIN1_FLT ADC_AIN0_FLT ADC_TEMP_FLT THERM_ERR_FLT THERM_WARN_FLT 20h ALARM_STATUS ALARM_STATUSGEN_IRQMODEM_IRQSD_FLTOSC_FAILCRC_CNT [1:0]OTP_LOADEDnOTP_CRC_ERRCRC_FLTWD_FLTVREF_FLTADC_AIN1_FLTADC_AIN0_FLTADC_TEMP_FLTTHERM_ERR_FLTTHERM_WARN_FLT 21h GEN_STATUS ALARM_IRQ MODEM_IRQ RESERVED OTP_BUSY BIST_ MODE BIST_DONE BIST_FAIL RESET SR_BUSYn ADC_EOC ADC_BUSY PVDD_HI BREAK_FRAME_ERR BREAK_PARITY_ERR UART_FRAME_ERR UART_PARITY_ERR 21h GEN_STATUS GEN_STATUSALARM_IRQMODEM_IRQRESERVEDOTP_BUSYBIST_ MODE BIST_DONEBIST_FAILRESETSR_BUSYnADC_EOCADC_BUSYPVDD_HIBREAK_FRAME_ERRBREAK_PARITY_ERRUART_FRAME_ERRUART_PARITY_ERR 22h MODEM_STATUS ALARM_IRQ GEN_IRQ RESERVED GAP_ERR FRAME_ERR PARITY_ERR FIFO_H2U_LEVEL_FLAG FIFO_H2U_FULL_FLAG FIFO_H2U_EMPTY_FLAG FIFO_U2H_LEVEL_FLAG FIFO_U2H_FULL_FLAG FIFO_U2H_EMPTY_FLAG CD_DEASSERT CD_ASSERT CTS_DEASSERT CTS_ASSERT 22h MODEM_STATUS MODEM_STATUSALARM_IRQGEN_IRQRESERVEDGAP_ERRFRAME_ERRPARITY_ERRFIFO_H2U_LEVEL_FLAGFIFO_H2U_FULL_FLAGFIFO_H2U_EMPTY_FLAGFIFO_U2H_LEVEL_FLAGFIFO_U2H_FULL_FLAGFIFO_U2H_EMPTY_FLAGCD_DEASSERTCD_ASSERTCTS_DEASSERTCTS_ASSERT 23h ADC_FLAGS RESERVED SD4_FAIL SD3_FAIL SD2_FAIL SD1_FAIL SD0_FAIL TEMP_FAIL AIN1_FAIL AIN0_FAIL RESERVED 23h ADC_FLAGS ADC_FLAGSRESERVEDSD4_FAILSD3_FAILSD2_FAILSD1_FAILSD0_FAILTEMP_FAILAIN1_FAILAIN0_FAILRESERVED 24h ADC_AIN0 RESERVED DATA [11:0] 24h ADC_AIN0 ADC_AIN0RESERVEDDATA [11:0] 25h ADC_AIN1 RESERVED DATA [11:0] 25h ADC_AIN1 ADC_AIN1RESERVEDDATA [11:0] 26h ADC_TEMP RESERVED DATA [11:0] 26h ADC_TEMP ADC_TEMPRESERVEDDATA [11:0] 27h ADC_SD_MUX RESERVED DATA [11:0] 27h ADC_SD_MUX ADC_SD_MUXRESERVEDDATA [11:0] 28h ADC_OFFSET RESERVED DATA [11:0] 28h ADC_OFFSET ADC_OFFSETRESERVEDDATA [11:0] 2Ah FIFO_H2U_RD LEVEL [3:0] LEVEL_FLAG FULL_FLAG EMPTY_FLAG PARITY DATA [7:0] 2Ah FIFO_H2U_RD FIFO_H2U_RDLEVEL [3:0]LEVEL_FLAGFULL_FLAGEMPTY_FLAGPARITYDATA [7:0] 2Bh FIFO_STATUS H2U_LEVEL [3:0] H2U_LEVEL_FLAG H2U_FULL_FLAG H2U_EMPTY_FLAG RESERVED U2H_LEVEL [3:0] U2H_LEVEL_FLAG U2H_FULL_FLAG U2H_EMPTY_FLAG RESERVED 2Bh FIFO_STATUS FIFO_STATUSH2U_LEVEL [3:0]H2U_LEVEL_FLAGH2U_FULL_FLAGH2U_EMPTY_FLAGRESERVEDU2H_LEVEL [3:0]U2H_LEVEL_FLAGU2H_FULL_FLAGU2H_EMPTY_FLAGRESERVED 2Ch DAC_OUT DATA [15:0] 2Ch DAC_OUT DAC_OUTDATA [15:0] 2Dh ADC_OUT RESERVED DATA [11:0] 2Dh ADC_OUT ADC_OUTRESERVEDDATA [11:0] 2Eh ADC_BYP DATA_BYP_EN OFST_BYP_EN DIS_GND_SAMP RESERVED DATA [11:0] 2Eh ADC_BYP ADC_BYPDATA_BYP_ENOFST_BYP_ENDIS_GND_SAMPRESERVEDDATA [11:0] 2Fh FORCE_FAIL CRC_FLT VREF_FLT THERM_ERR_FLT THERM_WARN_FLT RESERVED SD4_HI_FLT SD4_LO_FLT SD3_HI_FLT SD3_LO_FLT SD2_HI_FLT SD2_LO_FLT SD1_HI_FLT SD1_LO_FLT SD0_HI_FLT SD0_LO_FLT 2Fh FORCE_FAIL FORCE_FAILCRC_FLTVREF_FLTTHERM_ERR_FLTTHERM_WARN_FLTRESERVEDSD4_HI_FLTSD4_LO_FLTSD3_HI_FLTSD3_LO_FLTSD2_HI_FLTSD2_LO_FLTSD1_HI_FLTSD1_LO_FLTSD0_HI_FLTSD0_LO_FLT 3Bh TIMER_CFG_0 RESERVED CLK_SEL [1:0] INVERT ENABLE 3Bh TIMER_CFG_0 TIMER_CFG_0RESERVEDCLK_SEL [1:0]INVERTENABLE 3Ch TIMER_CFG_1 PERIOD [15:0] 3Ch TIMER_CFG_1 TIMER_CFG_1PERIOD [15:0] 3Dh TIMER_CFG_2 SET_TIME [15:0] 3Dh TIMER_CFG_2 TIMER_CFG_2SET_TIME [15:0] 3Eh CRC_RD CRC [15:0] 3Eh CRC_RD CRC_RDCRC [15:0] 3Fh RBIST_CRC CRC [15:0] 3Fh RBIST_CRC RBIST_CRCCRC [15:0] The SPECIAL_CFG register can only be reset with POR, and does not respond to the RESET pin or SW_RST command. The UBM register can only be accessed with a UBM command. The SPECIAL_CFG register can only be reset with POR, and does not respond to the RESET pin or SW_RST command.RESETThe UBM register can only be accessed with a UBM command. AFEx82H1 Registers Complex bit access types are encoded to fit into small table cells. The following table shows the codes that are used for access types in this section. AFEx82H1 Access-Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W WO Write only W WSC Write self clear Reset or Default Value -n Value after reset or the default value Register Array Variables i,j,k,l,m,n When used in a register name, an offset, or an address, these variables refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. y When used in a register name, an offset, or an address, this variable refers to the value of a register array. NOP Register (Offset = 0h) [Reset = 0000h] Return to the Register Map . NOP Register Field Descriptions Bit Field Type Reset Description 15-0 NOP WO 0h No operation. Data written to this field have no effect. Always reads zeros. DAC_DATA Register (Offset = 1h) [Reset = 0000h] Return to the Register Map . DAC code for VOUT. DAC_DATA Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W 0h Data. DAC code for VOUT. CONFIG Register (Offset = 2h) [Reset = 0036h] Return to the Register Map . CONFIG Register Field Descriptions Bit Field Type Reset Description 15-14 CRC_ERR_CNT R/W 0h CRC Errors Count LimitSets the numbers of consecutive SPI CRC frames that must have errors before the status bits is set. 0h = 1 (default); 1h = 2; 2h = 4; 3h = 8 13-10 CLKO R/W 0h CLKO EnableEnable the CLK_OUT pin and set the divider value. 0h = CLKO disabled (default); 1h = 1.2288 MHz; 2h = 1.2288 / 2 MHz; 3h = 1.2288 / 4 MHz; 4h = 1.2288 / 8 MHz; 5h = 1.2288 / 16 MHz; 6h =1.2288 / 32 MHz; 7h = 1.2288 / 64 MHz; 8h = 1.2288 / 128 MHz; 9h = 1.2288 / 256 MHz; Ah = 1.2288 / 512 MHz; Bh = 1.2288 / 1024 MHz; Ch = 1'b0; Dh = 1'b0; Eh = 1'b0; Fh = Timer 9 UBM_IRQ_EN R/W 0h UBM IRQ EnableEnable IRQ to be sent on UARTOUT through UBM.0h = Disabled (default); 1h = Enabled 8 IRQ_PIN_EN R/W 0h IRQ Pin EnableEnable IRQ pin functionality.0h = Disabled (default); 1h = Enabled 7 CLR_PIN_EN R/W 0h Clear Input Pin EnableEnable pin-based transition to the CLEAR state in UBM.0h = Disabled (default); 1h = SDI pin configured as clear input pin 6 UART_DIS R/W 0h UART DisableDisable UART functionality.0h = UART Enabled (default); 1h = UART Disabled 5 UART_BAUD R/W 1h UART BaudConfigure BAUD rate for UART.0h = 1200 baud (no break); 1h = 9600 baud (Break mode) (default) 4 CRC_EN R/W 1h CRC EnableEnable CRC for SPI.0h = Disabled; 1h = Enabled (default) 3 IRQ_POL R/W 0h IRQ Polarity0h = Active low (default); 1h = Active high 2 IRQ_LVL R/W 1h IRQ Level0h = Edge sensitive; 1h = Level sensitive (default) 1 DSDO R/W 1h SDO Hi-Z0h = Drive SDO during CS = 0; 1h = SDO always Hi-Z (default) 0 FSDO R/W 0h Fast SDOSDO is driven on negative edge of SCLK.0h = drive SDO on rising edge of SCLK (launching edge) (default) 1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock early) DAC_CFG Register (Offset = 3h) [Reset = 0B00h] Return to the Register Map . DAC_CFG Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R/W 0h 12 PD R/W 0h DAC Output Buffer Power-down DAC output set to Hi-Z in power-down. 0h = DAC output buffer enabled (default) 1h = DAC output buffer disabled 11-9 SR_CLK R/W 5h Slew Clock Rate 0h = 307.2 kHz 1h = 153.6 kHz 2h = 76.8 kHz 3h = 38.4 kHz 4h = 19.2 kHz 5h = 9600 Hz (default) 6h = 4800 Hz 7h = 2400 Hz 8-6 SR_STEP R/W 4h Slew Step Size 0h = 1 code 1h = 2 codes 2h = 4 codes 3h = 8 codes 4h = 16 codes (default) 5h = 32 codes 6h = 64 codes 7h = 128 codes 5 SR_EN R/W 0h Slew Enable Enables slew on the output voltage. 0h = Disabled (default) 1h = Enabled 4 SR_MODE R/W 0h Slew Mode Output slew rate mode select. 0h = Linear Slew (default) 1h = Sinusoidal Slew 3 RESERVED R 0h 2 CLR R/W 0h CLEAR State 0h = Normal operation (default) 1h = Force the DAC to the CLEAR state 1-0 RESERVED R 0h DAC_GAIN Register (Offset = 4h) [Reset = 8000h] Return to the Register Map . DAC_GAIN Register Field Descriptions Bit Field Type Reset Description 15-0 GAIN R/W 8000h GainSet the gain of the DAC output from 0.5 – 1.499985. For example: 0000h = 0.5 8000h = 1.0 (default) FFFFh = 1.499985 DAC_OFFSET Register (Offset = 5h) [Reset = 0000h] Return to the Register Map . DAC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-0 OFFSET R/W 0h OffsetAdjust the offset of the DAC output, 2's complement number. For example: 0000h = 0 (default) FFFFh = –1 DAC_CLR_CODE Register (Offset = 6h) [Reset = 0000h] Return to the Register Map . DAC_CLR_CODE Register Field Descriptions Bit Field Type Reset Description 15-0 CODE R/W 0h CLEAR State DAC CodeDAC code applied in the CLEAR state. See . RESET Register (Offset = 7h) [Reset = 0000h] Return to the Register Map . RESET Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-0 SW_RST WSC 0h Software Reset Write ADh to initiate software reset. ADC_CFG Register (Offset = 8h) [Reset = 8810h] Return to the Register Map . ADC_CFG Register Field Descriptions Bit Field Type Reset Description 15 BUF_PD R/W 1h ADC Buffer Power-Down 0h = ADC buffer enabled; 1h = ADC buffer powered down (default) 14-8 HYST R/W 8h HysteresisThe number of codes of hysteresis used when a threshold is exceeded for an ADC measurement of AIN0/AIN1/TEMP. 7-5 FLT_CNT R/W 0h Fault Count Number of successive faults to trip an alarm.Number of successive faults is programmed value + 1 (1-8 faults). 4 AIN_RANGE R/W 1h ADC Analog Input Range Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs. 0h = 2 × VREF; 1h = 1 × VREF (default) 3 EOC_PER_CH R/W 0h ADC End-of-Conversion for Every ChannelSends an EOC pulse at the end of each channel instead of at the end of all the channels.0h = EOC after last channel (default); 1h = EOC for every channel 2-1 CONV_RATE R/W 0h ADC Conversion RateThis setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based on a 76.8-kHz ADC clock. All other channels use 2560 Hz. 0h = 3840 Hz (default) 1h = 2560 Hz 2h = 1280 Hz 3h = 640 Hz 0 DIRECT_MODE R/W 0h Direct Mode Enable 0h = Auto mode (default); 1h = Direct mode ADC_INDEX_CFG Register (Offset = 9h) [Reset = 0080h] Return to the Register Map . The ADC custom channel sequencing configuration is shown in #GUID-121F6531-236F-4BFA-AA11-8CC4C580B655/GUID-84429441-E2D5-4137-992B-F0A3EE3367A1. ADC_INDEX_CFG Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-4 STOP R/W 8h Custom Channel Sequencer Stop IndexCCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START. 0h = OFFSET 1h = AIN0 2h = AIN1 3h = TEMP 4h = SD0 (VREF) 5h = SD1 (PVDD) 6h = SD2 (VDD) 7h = SD3 (ZTAT) 8h = SD4 (VOUT) (default) 9h through Fh = GND 3-0 START R/W 0h Custom Channel Sequencer Start IndexCCS index to start ADC sequence.0h through Fh = Same as STOP field (0h is default) TRIGGER Register (Offset = Ah) [Reset = 0000h] Return to the Register Map . TRIGGER Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED R 0h 3 RBIST WSC 0h RBIST Trigger This trigger initiates a Register BIST. This BIST runs a CRC calculation through the configuration registers () and compares the result to a stored CRC value in the RBIST_CRC register. 2 MBIST WSC 0h Memory Built-In Self-Test Trigger This trigger initiates an MBIST on the SRAM that is used for the FIFO. During this time communication to/from HART does not work as MBIST takes over the control of the SRAM. 1 SHADOWLOAD WSC 0h Shadow Load TriggerThis trigger initiates the loading of the OTP array into the parallel latches. If an OTP CRC error is detected, assert this trigger to try and reload the OTP into the memory locations. 0 ADC WSC 0h ADC TriggerIn auto mode, this bit enables or disables the conversions. Manually set to 1 (enable) or 0 (disable). In direct mode, set this bit to start a conversion sequence. The bit is cleared at the end of the sequence. To stop a sequence prematurely, manually clear this bit. SPECIAL_CFG Register (Offset = Bh) [Reset = 0000h] Return to the Register Map . SPECIAL_CFG Register Field Descriptions Bit Field Type Reset Description 15-3 RESERVED R 0h 2 OTP_LOAD_SW_RST R/W 0h OTP (One Time Programmable Factory Trimmed Registers) LOAD with SW RESETOTP reloads with the assertion of a software reset (SW_RST). 0h = No reload with SW_RST 1h = Reload with SW_RST 1 ALMV_POL R/W 0h Alarm Voltage PolarityThis register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB bit is low) to control the VOUT during a hardware reset condition or if alarm is active and alarm action is set appropriately. The following Boolean function is implemented for the internal signal ALMV_POL_o that sets the VOUT voltage:ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT AIN1_ENB) 0h = Low (0 V) 1h = High (2.5 V) 0 AIN1_ENB R/W 0h AIN1 Pin EnableThis bit determines whether the POL_SEL/AIN1 pin acts as alarm voltage polarity control bit or an input channel to the ADC. 0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts GND 1h = AIN1 pin is an active channel to the ADC MODEM_CFG Register (Offset = Eh) [Reset = 0040h] Return to the Register Map . MODEM_CFG Register Field Descriptions Bit Field Type Reset Description 15 Tx2200Hz R/W 0h Transmit 2200 Hz OnlyBy not sending data to the FIFO buffer and asserting RTS, the user can transmit multiples of 1200 Hz as long as RTS is asserted. By setting this bit the user can transmit multiples of 2200 Hz. Setting this bit prevents data in the FIFO buffer from being correctly transmitted. If using this bit there is no need to use the FIFO buffer. 0h = Transmit 1200 Hz and 2200 Hz (default) 1h = Transmit only 2200 Hz 14-13 RESERVED R 0h 12 DUPLEX_EXT R/W 0h Duplex External ModeAllows full duplex mode but expects the connection of MOD_OUT to RX_IN to be made externally. 0h = Internal duplex connection (default) 1h = External duplex connection 11 RX_HORD_EN R/W 0h High Order Filter EnableEnables a higher order filter on HART_RX. 0h = Disable (default); 1h = Enable 10 RX_EXTFILT_EN R/W 0h External Filter EnableEnables the use of an external filter for HART_RX. If enabled, then connect the HART signal to RX_INF. 0h = Use internal filter (default); 1h = Use external filter 9 TxRES R/W 0h HART Transmit Resolution0h = 32 steps per period (default) at 38.4 kHz update rate for 1200 baud 1h = 128 steps per period at 153.6 kHz update rate for 1200 baud 128-step per period waveform consumes more power. 8-4 TxAMP R/W 4h Transmit AmplitudeHART Tx amplitude. 00h = 400 mVPP; 01h = 425 mVPP 02h = 450 mVPP; 03h = 475 mVPP 04h = 500 mVPP (default); 05h = 525 mVPP 06h = 550 mVPP; 07h = 575 mVPP 08h = 600 mVPP; 09h = 625 mVPP 0Ah = 650 mVPP; 0Bh = 675 mVPP 0Ch = 700 mVPP; 0Dh = 725 mVPP 0Eh = 750 mVPP; 0Fh = 775 mVPP 10h through 1Fh = 800 mVPP 3 HART_EN R/W 0h HART EnableEnable the HART Tx and Rx.0h = Disable (default); 1h = Enable 2 DUPLEX R/W 0h Duplex ModeEnable internal connection of Tx to Rx for debug and testing.0h = Normal operation (default); 1h = Duplex enabled 1 TxHPD R/W 0h HART Tx DAC Output Buffer Hi-Z in Rx Mode or When Disabled0h = HART Tx DAC output is set to midcode with 50 kΩ output impedance (default) 1h = HART Tx DAC is Hi-Z in Rx mode or when disabled. Users can set the default voltage level with an external circuit. 0 RTS R/W 0h Request To Send Starts transmitting a carrier on MOD_OUT pin.0h = No action (default) 1h = Request to send. Device starts modulating the MOD_OUT pin if CD = 0. FIFO_CFG Register (Offset = Fh) [Reset = 00F0h] Return to the Register Map . FIFO_CFG Register Field Descriptions Bit Field Type Reset Description 15-10 RESERVED R 0h 9 FIFO_H2U_FLUSH WSC 0h Flush HART-to-µC FIFO (FIFO_H2U) Clear the pointers for the FIFO_H2U. 8 FIFO_U2H_FLUSH WSC 0h Flush µC-to-HART FIFO (FIFO_U2H) Clear the pointers for the FIFO_U2H. 7-4 H2U_LEVEL_SET R/W Fh FIFO_H2U FIFO Level Flag Trip SetSets the level for FIFO_H2U at which the Level Flag trips. This is a (>) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. 3-0 U2H_LEVEL_SET R/W 0h FIFO_U2H FIFO Level Flag Trip SetSets the level for FIFO_U2H at which the Level Flag trips. This is a (<) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. ALARM_ACT Register (Offset = 10h) [Reset = 8020h] Return to the Register Map . ALARM_ACT Register Field Descriptions Bit Field Type Reset Description 15-14 SD_FLT R/W 2h Self-Diagnostic Fault Action These bits set the device action after a self-diagnostic fault. 0h = No Action 1h = Set DAC to CLEAR state 2h = Switch to alarm voltage determined by ALMV_POL (default) 3h = Place DAC into Hi-Z (power-down) 13-12 TEMP_FLT R/W 0h TEMP Fault ActionThese bits set the device action if the ADC temperature is outside the TEMP_THRESHOLD Hi or Lo thresholds.0h through 3h = Same as SD_FLT field (default 0h) 11-10 AIN1_FLT R/W 0h AIN1 Fault ActionThese bits set the device action if the ADC AIN1 channel is outside the AIN1_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 9-8 AIN0_FLT R/W 0h AIN0 Fault Action These bits set the device action if the ADC AIN0 channel is outside the AIN0_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 7-6 CRC_WDT_FLT R/W 0h CRC and WDT Fault ActionThese bits set the device action when a SPI CRC or SPI Watchdog Timeout error occurs. 0h through 3h = Same as SD_FLT field (default 0h) 5-4 VREF_FLT R/W 2h VREF Fault ActionThese bits set the device action when a fault is detected on VREF. 0h through 3h = Same as SD_FLT field a 3-2 THERM_ERR_FLT R/W 0h Thermal Error Fault ActionThese bits set the device action when a high temperature error occurs (> 130°C). 0h through 3h = Same as SD_FLT field (default 0h) 1-0 THERM_WARN_FLT R/W 0h Thermal Warning Fault ActionThese bits set the device action when a high temperature warning occurs (> 85°C). 0h through 3h = Same as SD_FLT field (default 0h) WDT Register (Offset = 11h) [Reset = 0018h] Return to the Register Map . WDT Register Field Descriptions Bit Field Type Reset Description 15-6 RESERVED R 0h 5-3 WDT_UP R/W 3h Watchdog Timer (WDT) Upper LimitIf the WDT is enabled and the timer exceeds the programmed value, a WDT error is asserted. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = 53 ms (64 clocks) 1h = 106 ms (128 clocks) 2h = 427 ms (512 clocks) 3h = 853 ms (1024 clocks, default) 4h = 1.7 s (2048 clocks) 5h = 2.56 s (3072 clocks) 6h = 3.41 s (4096 clocks) 7h = 5.12 s (6144 clocks) 2-1 WDT_LO R/W 0h WDT Lower LimitIf the WDT is enabled and the WDT Lower Limit is enabled, then only a write to this register resets the WDT timer. If the write occurs before the WDT Lower Limit time, or after the WDT Upper Limit time, then a WDT error is asserted. If WDT Lower Limit is disabled, then a write to any register resets the timer. This is true for both SPI and UART Break modes. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = Disabled (default) 1h = 53 ms (64 clocks) 2h = 106 ms (128 clocks) 3h = 427 ms (512 clocks) 0 WDT_EN R/W 0h WDT Enable 0h = Disabled (default); 1h = Enabled AIN0_THRESHOLD Register (Offset = 12h) [Reset = FF00h] Return to the Register Map . AIN0_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN0 {[11:4],4b1111} This value is compared (>) against AIN0 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN0 {[11:4],4b0000} This value is compared (<) against AIN0 data bits[11:0]. AIN1_THRESHOLD Register (Offset = 13h) [Reset = FF00h] Return to the Register Map . AIN1_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN1 {[11:4],4b1111} This value is compared (>) against AIN1 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN1 {[11:4],4b0000} This value is compared (<) against AIN1 data bits[11:0]. TEMP_THRESHOLD Register (Offset = 14h) [Reset = FF00h] Return to the Register Map . TEMP_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel TEMP {[11:4],4b1111} This value is compared (>) against TEMP data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel TEMP {[11:4],4b0000} This value is compared (<) against TEMP data bits[11:0]. FIFO_U2H_WR Register (Offset = 15h) [Reset = 0000h] Return to the Register Map . This register controls the HART to microcontroller FIFO buffer. FIFO_U2H_WR Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h 8 PARITY WO 0h ParityOdd parity bit to be transmitted with data. This field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. 7-0 DATA WO 0h Data ByteThis field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. UBM Register (Offset = 16h) [Reset = 0000h] Return to the Register Map . UBM Register Field Descriptions Bit Field Type Reset Description 15-1 RESERVED R 0h 0 REG_MODE R/W 0h Register ModeConfigure the rest of the Register Map to be accessed by UART break mode (UBM) or SPI. This register can only be written by the UART Break communication.0h = SPI Mode (default) 1h = UART Break Mode SCRATCH Register (Offset = 18h) [Reset = FFFFh] Return to the Register Map . SCRATCH Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W FFFFh Scratch Data Data written is read back as the inverted value. For example, writing 0xAAAA is read back as 0x5555. CHIP_ID_LSB Register (Offset = 19h) Return to the Register Map . CHIP ID LSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Unique part number within each lot CHIP_ID_MSB Register (Offset = 1Ah) Return to the Register Map . CHIP ID MSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Encoded lot identification number GPIO_CFG Register (Offset = 1Bh) [Reset = 00FFh] Return to the Register Map . GPIO CONFIG Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R 0h 14-8 EN R/W 00h GPIO per Pin Enable. (See for additional configuration required specific to each pin and communication mode) [14] = GPIO6 [13] = GPIO5 [12] = GPIO4 [11] = GPIO3 [10] = GPIO2 [9] = GPIO1 [8] = GPIO00h = GPIO function disable1h = GPIO function enabledFor any pin used either for the communication function or not used as an active GPIO, set this bit to 0h. 7 RESERVED R 0h 6-0 ODE R/W FFh Pseudo Open Drain EnableGPIO output enable and pseudo open drain functionality on the GPIO pins. (See for additional configuration required specific to each pin and communication mode.) [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO00h = Push-pull output enabled1h = Pseudo open-drain output enabled GPIO Register (Offset = 1Ch) [Reset = 007Fh] Return to the Register Map . GPIO Register Field Descriptions Bit Field Type Reset Description 15-7 RESERVED R 0h 6-0 DATA R/W 7Fh GPIO pin data. For GPIO input this bit must be written as 1 and GPIO_CFG.ODE = 1 and GPIO_CFG.EN = 1. Reading this register reads the pin value when the pin is correctly enabled. (See for additional configuration required specific to each pin and communication mode) For GPIO output this bit sets the pin value. [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO0 ALARM_STATUS_MASK Register (Offset = 1Dh) [Reset = EFDFh] Return to the Register Map . ALARM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-14 RESERVED R 3h 13 SD_FLT R/W 1h SD Fault Mask0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 12 OSC_FAIL R/W 0h OSC_FAIL Fault Mask Same as SD Fault Mask (default 0h). 11-9 RESERVED R 7h 8 OTP_CRC_ERR R/W 1h OTP CRC Error Mask Same as SD Fault Mask (default 1h). 7 CRC_FLT R/W 1h SPI CRC Fault Mask Same as SD Fault Mask (default 1h). 6 WD_FLT R/W 1h Watchdog Fault Mask Same as SD Fault Mask (default 1h). 5 VREF_FLT R/W 0h VREF Fault Mask Same as SD Fault Mask (default 0h). 4 ADC_AIN1_FLT R/W 1h ADC AIN1 Fault Mask Same as SD Fault Mask (default 1h). 3 ADC_AIN0_FLT R/W 1h ADC AIN0 Fault Mask Same as SD Fault Mask (default 1h). 2 ADC_TEMP_FLT R/W 1h ADC TEMP Fault Mask Same as SD Fault Mask (default 1h). 1 THERM_ERR_FLT R/W 1h Temperature > 130°C Error Mask Same as SD Fault Mask (default 1h). 0 THERM_WARN_FLT R/W 1h Temperature > 85°C Warning Mask Same as SD Fault Mask (default 1h). GEN_STATUS_MASK Register (Offset = 1Eh) [Reset = FFFFh] Return to the Register Map . GEN_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-11 RESERVED R 1Fh 10 BIST_DONE R/W 1h BIST Done Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 9 BIST_FAIL R/W 1h BIST Failed Fault Mask Same as BIST Done Mask (default 1h). 8 RESERVED R 1h 7 SR_BUSYn R/W 1h Slew Rate Not Busy Mask Same as BIST Done Mask (default 1h). 6 ADC_EOC R/W 1h ADC End Of Conversion Mask Same as BIST Done Mask (default 1h). 5-4 RESERVED R 3h 3 BREAK_FRAME_ERR R/W 1h Break Frame Error Fault Mask Same as BIST Done Mask (default 1h). 2 BREAK_PARITY_ERR R/W 1h Break Parity Error Fault Mask Same as BIST Done Mask (default 1h). 1 UART_FRAME_ERR R/W 1h UART Frame Error Fault Mask Same as BIST Done Mask (default 1h). 0 UART_PARITY_ERR R/W 1h UART Parity Error Fault Mask Same as BIST Done Mask (default 1h). MODEM_STATUS_MASK Register (Offset = 1Fh) [Reset = FFFFh] Return to the Register Map . MODEM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R 7h 12 GAP_ERR R/W 1h HART Gap Error Fault Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 11 FRAME_ERR R/W 1h HART Frame Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 10 PARITY_ERR R/W 1h HART Parity (ODD) Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 9 FIFO_H2U_LEVEL_FLAG R/W 1h FIFO_H2U Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 8 FIFO_H2U_FULL_FLAG R/W 1h FIFO_H2U Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 7 FIFO_H2U_EMPTY_FLAG R/W 1h FIFO_H2U Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 6 FIFO_U2H_LEVEL_FLAG R/W 1h FIFO_U2H Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 5 FIFO_U2H_FULL_FLAG R/W 1h FIFO_U2H Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 4 FIFO_U2H_EMPTY_FLAG R/W 1h FIFO_U2H Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 3 CD_DEASSERT R/W 1h CD Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 2 CD_ASSERT R/W 1h CD Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 1 CTS_DEASSERT R/W 1h CTS Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 0 CTS_ASSERT R/W 1h CTS Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). ALARM_STATUS Register (Offset = 20h) [Reset = 0200h] Return to the Register Map . ALARM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 SD_FLT R 0h Self Diagnostic (SD) Fault0h = All self diagnostic channels are within threshold limits 1h = At least one of the self diagnostic channels has failed 12 OSC_FAIL R 0h Oscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed IRQ.0h = Oscillator started; 1h = Oscillator has failed to start 11-10 CRC_CNT R 0h CRC Fault CounterIf counter limit ≤ 4 then bits[1:0] of the counter are shown here. If the counter limit = 8 then bits[2:1] of the counter are shown. 9 OTP_LOADEDn R 1h OTP NOT Loaded Clears when OTP has loaded at least once. Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ.0h = OTP has loaded at least once; 1h = OTP has not finished loading 8 OTP_CRC_ERR R 0h OTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation. Sticky, cleared by reading register, unless condition still persist.0h = No OTP CRC fault; 1h = OTP CRC fault 7 CRC_FLT R 0h CRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame. Sticky, cleared by reading register, unless condition still persist.0h = No CRC fault; 1h = CRC fault 6 WD_FLT R 0h Watchdog Timer Fault Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No watchdog fault; 1h = Watchdog fault 5 VREF_FLT R 0h Invalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Valid VREF voltage; 1h = Invalid VREF voltage 4 ADC_AIN1_FLT R 0h ADC AIN1 Fault. Maskable fault. 0h = AIN1 ADC measurement within threshold limits 1h = AIN1 ADC measurement outside threshold limits 3 ADC_AIN0_FLT R 0h ADC AIN0 Fault. Maskable fault. 0h = AIN0 ADC measurement within threshold limits 1h = AIN0 ADC measurement outside threshold limits 2 ADC_TEMP_FLT R 0h ADC Temp Fault. Maskable fault. 0h = TEMP ADC measurement within threshold limits 1h = TEMP ADC measurement outside threshold limits 1 THERM_ERR_FLT R 0h Temperature > 130°C error. Maskable fault. OR with FORCE_FAIL.THERM_ERR_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C 0 THERM_WARN_FLT R 0h Temperature > 85°C warning. Maskable fault. OR with FORCE_FAIL.THERM_WARN_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C GEN_STATUS Register (Offset = 21h) [Reset = 1180h] Return to the Register Map . GEN_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 RESERVED R 0h 12 OTP_BUSY R 1h OTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches.0h = OTP has completed loading into the device 1h = OTP is being loaded into the device 11 BIST_MODE R 0h Denotes which BIST is being run.0h = MBIST; 1h = RBIST 10 BIST_DONE R 0h BIST Completed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has not completed; 1h = BIST has completed 9 BIST_FAIL R 0h BIST Failed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has passed; 1h = BIST has failed 8 RESET R 1h Device Reset Occurred. Status only. Does not feed IRQ.Sticky, cleared by reading register, unless condition still persist. 0h = Device has not reset since last read of register 1h = Device has reset since last read of register 7 SR_BUSYn R 1h Slew Rate Not Busy. Maskable fault. 0h = DAC is slewing to the target code1h = DAC_OUT has reached the DAC_DATA. If slew rate is disabled, then this signal produces a rising edge within 3 internal clock cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can cause an unwanted fast transition on VOUT. 6 ADC_EOC R 0h ADC End of Conversion (EOC). Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No EOC since last read of register; 1h = ADC end of conversion 5 ADC_BUSY R 0h ADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true. 0h = No ADC activity; 1h = ADC is actively converting 4 PVDD_HI R 0h PVDD High. Status only. Does not feed IRQ. Set as long as condition is true. 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7 V 3 BREAK_FRAME_ERR R 0h Incorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break frame error; 1h = Break frame error 2 BREAK_PARITY_ERR R 0h Incorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break parity error; 1h = Break parity error 1 UART_FRAME_ERR R 0h Incorrect Stop Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART frame error; 1h = UART frame error 0 UART_PARITY_ERR R 0h Incorrect Parity (ODD) Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART parity error; 1h = UART parity error MODEM_STATUS Register (Offset = 22h) [Reset = 009Ah] Return to the Register Map . MODEM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 13 RESERVED R 0h 12 GAP_ERR R 0h HART Gap Error. Maskable fault. Applies to RX_IN/RX_INF. Too much time (11 bit times) between HART characters. Sticky, cleared by reading register, unless condition still persist. Fatal Fault.0h = No HART gap error; 1h = HART gap error 11 FRAME_ERR R 0h Incorrect Stop Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. Fatal Fault. 0h = No HART frame error; 1h = HART frame error 10 PARITY_ERR R 0h Incorrect Parity (ODD) Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. 0h = No HART parity error; 1h = HART parity error 9 FIFO_H2U_LEVEL_FLAG R 0h FIFO HART-to-µC Level Flag. Maskable fault. If the level of the FIFO_H2U is full, then the level flag is not asserted, but the full flag is, so no information is lost.0h = FIFO_H2U level ≤ {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 1h = FIFO_H2U level > {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 8 FIFO_H2U_FULL_FLAG R 0h FIFO HART-to-µC Full Flag. Maskable fault. 0h = FIFO_H2U is not full; 1h = FIFO_H2U is full 7 FIFO_H2U_EMPTY_FLAG R 1h FIFO HART-to-µC Empty Flag. Maskable fault. 0h = FIFO_H2U is not empty; 1h = FIFO_H2U is empty 6 FIFO_U2H_LEVEL_FLAG R 0h FIFO µC-to-HART Level Flag. Maskable fault. FIFO_U2H < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0}. When the FIFO_U2H is empty, this flag is set unless FIFO_CFG.U2H_LEVEL_SET = 0. This flag and the empty flag can be set at the same time.0h = FIFO_U2H level ≥ {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 1h = FIFO_U2H level < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 5 FIFO_U2H_FULL_FLAG R 0h FIFO µC-to-HART Full Flag. Maskable fault. 0h = FIFO_U2H is not full; 1h = FIFO_U2H is full 4 FIFO_U2H_EMPTY_FLAG R 1h FIFO µC-to-HART Empty Flag. Maskable fault. 0h = FIFO_U2H is not empty; 1h = FIFO_U2H is empty 3 CD_DEASSERT R 1h Carrier Detect Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is asserted; 1h = Carrier detect is deasserted 2 CD_ASSERT R 0h Carrier Detect Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is deasserted; 1h = Carrier detect is asserted 1 CTS_DEASSERT R 1h Clear To Send Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is asserted; 1h = Clear to send is deasserted 0 CTS_ASSERT R 0h Clear To Send Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is deasserted; 1h = Clear to send is asserted ADC_FLAGS Register (Offset = 23h) [Reset = 0000h] Return to the Register Map .The limits for Self Diagnostic (SD) Alarm ADC Thresholds are shown in . ADC_FLAGS Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h 8 SD4_FAIL R 0h SD4 (VOUT) Limit Fail 7 SD3_FAIL R 0h SD3 (ZTAT) Limit Fail 6 SD2_FAIL R 0h SD2 (VDD) Limit Fail 5 SD1_FAIL R 0h SD1 (PVDD) Limit Fail 4 SD0_FAIL R 0h SD0 (VREF) Limit Fail 3 TEMP_FAIL R 0h TEMP Limit Fail 2 AIN1_FAIL R 0h AIN1 Limit Fail 1 AIN0_FAIL R 0h AIN0 Limit Fail 0 RESERVED R 0h ADC_AIN0 Register (Offset = 24h) [Reset = 0000h] Return to the Register Map . ADC_AIN0 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN0 ADC_AIN1 Register (Offset = 25h) [Reset = 0000h] Return to the Register Map . ADC_AIN1 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN1 ADC_TEMP Register (Offset = 26h) [Reset = 0000h] Return to the Register Map . ADC_TEMP Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Temperature ADC_SD_MUX Register (Offset = 27h) [Reset = 0000h] Return to the Register Map . ADC_SD_MUX Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Self-Diagnostic (SD) MUX Input ADC_OFFSET Register (Offset = 28h) [Reset = 0000h] Return to the Register Map . ADC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Comparator Offset This value reports the offset measured in the device, and can be used to adjust each conversion value. If ADC_BYP.OFST_BYP_EN is set, then the value in ADC_BYP.DATA is used as the offset. This value is not affected by ADC_BYP. FIFO_H2U_RD Register (Offset = 2Ah) [Reset = 0200h] Return to the Register Map . FIFO_H2U_RD Register Field Descriptions Bit Field Type Reset Description 15-12 LEVEL R 0h LevelCurrent Level of FIFO_H2U, bits [4:1] represented as Level[3:0]. Pre-dequeue. 11 LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO_H2U Level > {Level,1b1}. Pre-dequeue.0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 FULL_FLAG R 0h HART-to-µC FIFO Full Flag. Pre-dequeue. 0h = FIFO_H2U is not full, pre-dequeue 1h = FIFO_H2U is full, pre-dequeue 9 EMPTY_FLAG R 1h HART-to-µC FIFO Empty Flag. Pre-dequeue. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 PARITY R 0h Parity Bit (ODD)Parity bit received with data on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. 7-0 DATA R 0h Data8-bit data received on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. FIFO_STATUS Register (Offset = 2Bh) [Reset = 0202h] Return to the Register Map . The FIFO_STATUS register is provided to allow the user to view the state of both FIFOs without enqueuing or dequeuing data in the FIFO. This also allows the flags to be viewed without disturbing other status bits in the MODEM_STATUS register. This register is provided to enable users to check the FIFO status register without disturbing other functions within the device. FIFO_STATUS Register Field Descriptions Bit Field Type Reset Description 15-12 H2U_LEVEL R 0h HART-to-µC FIFO LevelCurrent level of FIFO_H2U, right shifted 1 bit (>>1) so only even counts are represented. 11 H2U_LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO Level > {Level,1b1}. 0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 H2U_FULL_FLAG R 0h HART-to-µC FIFO Full FlagSet when FIFO is full. 0h = FIFO_H2U is not full 1h = FIFO_H2U is full 9 H2U_EMPTY_FLAG R 1h HART-to-µC Empty FlagSet when FIFO is empty. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 RESERVED R 0h 7-4 U2H_LEVEL R 0h µC-to-HART FIFO LevelCurrent level of FIFO_U2H, right shifted 1 bit (>>1) so only even counts are represented 3 U2H_LEVEL_FLAG R 0h µC-to-HART FIFO Level FlagSet when FIFO_U2H Level < {Level,1b0}. 0h = FIFO_U2H level ≥ {Level, 1b0} 1h = FIFO_U2H level < {Level, 1b0} 2 U2H_FULL_FLAG R 0h µC-to-HART Full FlagSet when FIFO_U2H is full. 0h = FIFO_U2H is not full 1h = FIFO_U2H is full 1 U2H_EMPTY_FLAG R 1h µC-to-HART Empty FlagSet when FIFO_U2H is empty. 0h = FIFO_U2H is not empty 1h = FIFO_U2H is empty 0 RESERVED R 0h DAC_OUT Register (Offset = 2Ch) [Reset = 0000h] Return to the Register Map . DAC_OUT Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R 0h DAC Code Applied to the Analog Circuit ADC_OUT Register (Offset = 2Dh) [Reset = 0000h] Return to the Register Map . ADC_OUT Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Data for Each Conversion Does not include ADC_OFFSET.DATA adjustment. Is not affected by ADC_BYP.DATA. ADC_BYP Register (Offset = 2Eh) [Reset = 0000h] Return to the Register Map . ADC_BYP is shown in ADC_BYP Register Field Descriptions . ADC_BYP Register Field Descriptions Bit Field Type Reset Description 15 DATA_BYP_EN R/W 0h Data Bypass EnableApplies ADC_BYP.DATA to the ADC channel being converted. ADC_OFFSET is ignored. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. If OFST_BYP_EN is also set, DATA_BYP_EN takes priority over OFST_BYP_EN. After a channel is converted, the ADC_BYP.DATA value appears in the readback register for the converted channel and is used to calculate faults. 0h = Data bypass disabled (default) 1h = Data bypass enabled 14 OFST_BYP_EN R/W 0h Offset Bypass EnableOverrides the offset register with the ADC_BYP.DATA value. When using this bit, the ADC_BYP.DATA field is processed as 2's complement. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time.0h = Offset bypass disabled (default) 1h = Offset bypass enabled 13 DIS_GND_SAMP R/W 0h Disable GND SamplingThis bit disables the sampling of GND during SAR activity. The sampling of GND is used to fully discharge the sampling CAP to reduce channel crosstalk. 0h = GND sampling enabled (default) 1h = GND sampling disabled 12 RESERVED R 0h 11-0 DATA R/W 0h Bypass Data FORCE_FAIL Register (Offset = 2Fh) [Reset = 0000h] Return to the Register Map . Force failures for fault detection. FORCE_FAIL Register Field Descriptions Bit Field Type Reset Description 15 CRC_FLT R/W 0h Force CRC Failure on SDO by Inverting the CRC Byte 0h = No force failure of CRC (default) 1h = Force failure of CRC 14 VREF_FLT R/W 0h Force Reference Voltage Failure. Analog signal.0h = No force failure of VREF (default) 1h = Force failure of VREF 13 THERM_ERR_FLT R/W 0h Force Temperature > 130°C Thermal Error. Analog signal.0h = No force temperature > 130°C error (default) 1h = Force temperature > 130°C error 12 THERM_WARN_FLT R/W 0h Force Temperature > 85°C thermal Warning. Analog signal.0h = No force temperature > 85°C warning (default) 1h = Force temperature > 85°C warning 11-10 RESERVED R/W 0h 9 SD4_HI_FLT R/W 0h SD4 (VOUT) High Limit Failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 8 SD4_LO_FLT R/W 0h SD4 (VOUT) Low limit failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 7 SD3_HI_FLT R/W 0h SD3 (ZTAT) High Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 6 SD3_LO_FLT R/W 0h SD3 (ZTAT) Low Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 5 SD2_HI_FLT R/W 0h SD2 (VDD) High Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 4 SD2_LO_FLT R/W 0h SD2 (VDD) Low Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 3 SD1_HI_FLT R/W 0h SD1 (PVDD) High Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 2 SD1_LO_FLT R/W 0h SD1 (PVDD) Low Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 1 SD0_HI_FLT R/W 0h SD0 (VREF) High Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 0 SD0_LO_FLT R/W 0h SD0 (VREF) Low Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) TIMER_CFG_0 Register (Offset = 3Bh) [Reset = 0000h] Return to the Register Map . TIMER Configuration 0. TIMER CONFIG 0 Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED TO 0h 3-2 CLK_SEL R/W 0h Clock SelectSelects the timer clock frequency. 0h = None (default) 1h = 1.2288 MHz 2h = 1.200 kHz 3h = 1.171 Hz 1 INVERT R/W 0h Invert OutputInvert the Timer output. By default, the output is set to 1 when the counter is ≥ SET_TIME (3Dh). 0 ENABLE R/W 0h Timer Enable The CLK_OUT pin must also be configured to output the Timer. TIMER_CFG_1 Register (Offset = 3Ch) [Reset = 0000h] Return to the Register Map . TIMER Configuration 1. TIMER CONFIG 1 Register Field Descriptions Bit Field Type Reset Description 15-0 PERIOD R/W 0h This field defines the period of the timer. The period is the product of (PERIOD + 1) and the clock period of CLK_SEL. For example, CLK_SEL = 2h (1200 Hz), The period is (PERIOD + 1) × 853 ms. TIMER_CFG_2 Register (Offset = 3Dh) [Reset = 0000h] Return to the Register Map . TIMER Configuration 2. TIMER CONFIG 2 Register Field Descriptions Bit Field Type Reset Description 15-0 SET_TIME R/W 0h The SET_TIME determine when the output of the timer goes high. The bits define the duty cycle of the timer (PERIOD – SET_TIME). The timer starts out as 0 and transitions to 1 when the SET_TIME is met. The polarity of the timer can be inverted using the TIMER_CFG_0.INVERT bit. CRC_RD Register (Offset = 3Eh) [Reset = 0000h] Return to the Register Map . CRC read. CRC Read Register Field Descriptions Bit Field Type Reset Description 15-0 CRC R/O 0h Calculated CRC for RBIST or SHADOWLOAD. Final value is calculated internally. This value changes while RBIST or shadow load are running. RBIST_CRC Register (Offset = 3Fh) [Reset = 0000h] Return to the Register Map . RBIST CRC. RBIST CRC Register Field Descriptions Bit Field Type Reset Description 15-0 RBIST CRC R/W 0h Calculated CRC for Register RBIST AFEx82H1 RegistersAFEx82H1 Complex bit access types are encoded to fit into small table cells. The following table shows the codes that are used for access types in this section. AFEx82H1 Access-Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W WO Write only W WSC Write self clear Reset or Default Value -n Value after reset or the default value Register Array Variables i,j,k,l,m,n When used in a register name, an offset, or an address, these variables refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. y When used in a register name, an offset, or an address, this variable refers to the value of a register array. NOP Register (Offset = 0h) [Reset = 0000h] Return to the Register Map . NOP Register Field Descriptions Bit Field Type Reset Description 15-0 NOP WO 0h No operation. Data written to this field have no effect. Always reads zeros. DAC_DATA Register (Offset = 1h) [Reset = 0000h] Return to the Register Map . DAC code for VOUT. DAC_DATA Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W 0h Data. DAC code for VOUT. CONFIG Register (Offset = 2h) [Reset = 0036h] Return to the Register Map . CONFIG Register Field Descriptions Bit Field Type Reset Description 15-14 CRC_ERR_CNT R/W 0h CRC Errors Count LimitSets the numbers of consecutive SPI CRC frames that must have errors before the status bits is set. 0h = 1 (default); 1h = 2; 2h = 4; 3h = 8 13-10 CLKO R/W 0h CLKO EnableEnable the CLK_OUT pin and set the divider value. 0h = CLKO disabled (default); 1h = 1.2288 MHz; 2h = 1.2288 / 2 MHz; 3h = 1.2288 / 4 MHz; 4h = 1.2288 / 8 MHz; 5h = 1.2288 / 16 MHz; 6h =1.2288 / 32 MHz; 7h = 1.2288 / 64 MHz; 8h = 1.2288 / 128 MHz; 9h = 1.2288 / 256 MHz; Ah = 1.2288 / 512 MHz; Bh = 1.2288 / 1024 MHz; Ch = 1'b0; Dh = 1'b0; Eh = 1'b0; Fh = Timer 9 UBM_IRQ_EN R/W 0h UBM IRQ EnableEnable IRQ to be sent on UARTOUT through UBM.0h = Disabled (default); 1h = Enabled 8 IRQ_PIN_EN R/W 0h IRQ Pin EnableEnable IRQ pin functionality.0h = Disabled (default); 1h = Enabled 7 CLR_PIN_EN R/W 0h Clear Input Pin EnableEnable pin-based transition to the CLEAR state in UBM.0h = Disabled (default); 1h = SDI pin configured as clear input pin 6 UART_DIS R/W 0h UART DisableDisable UART functionality.0h = UART Enabled (default); 1h = UART Disabled 5 UART_BAUD R/W 1h UART BaudConfigure BAUD rate for UART.0h = 1200 baud (no break); 1h = 9600 baud (Break mode) (default) 4 CRC_EN R/W 1h CRC EnableEnable CRC for SPI.0h = Disabled; 1h = Enabled (default) 3 IRQ_POL R/W 0h IRQ Polarity0h = Active low (default); 1h = Active high 2 IRQ_LVL R/W 1h IRQ Level0h = Edge sensitive; 1h = Level sensitive (default) 1 DSDO R/W 1h SDO Hi-Z0h = Drive SDO during CS = 0; 1h = SDO always Hi-Z (default) 0 FSDO R/W 0h Fast SDOSDO is driven on negative edge of SCLK.0h = drive SDO on rising edge of SCLK (launching edge) (default) 1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock early) DAC_CFG Register (Offset = 3h) [Reset = 0B00h] Return to the Register Map . DAC_CFG Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R/W 0h 12 PD R/W 0h DAC Output Buffer Power-down DAC output set to Hi-Z in power-down. 0h = DAC output buffer enabled (default) 1h = DAC output buffer disabled 11-9 SR_CLK R/W 5h Slew Clock Rate 0h = 307.2 kHz 1h = 153.6 kHz 2h = 76.8 kHz 3h = 38.4 kHz 4h = 19.2 kHz 5h = 9600 Hz (default) 6h = 4800 Hz 7h = 2400 Hz 8-6 SR_STEP R/W 4h Slew Step Size 0h = 1 code 1h = 2 codes 2h = 4 codes 3h = 8 codes 4h = 16 codes (default) 5h = 32 codes 6h = 64 codes 7h = 128 codes 5 SR_EN R/W 0h Slew Enable Enables slew on the output voltage. 0h = Disabled (default) 1h = Enabled 4 SR_MODE R/W 0h Slew Mode Output slew rate mode select. 0h = Linear Slew (default) 1h = Sinusoidal Slew 3 RESERVED R 0h 2 CLR R/W 0h CLEAR State 0h = Normal operation (default) 1h = Force the DAC to the CLEAR state 1-0 RESERVED R 0h DAC_GAIN Register (Offset = 4h) [Reset = 8000h] Return to the Register Map . DAC_GAIN Register Field Descriptions Bit Field Type Reset Description 15-0 GAIN R/W 8000h GainSet the gain of the DAC output from 0.5 – 1.499985. For example: 0000h = 0.5 8000h = 1.0 (default) FFFFh = 1.499985 DAC_OFFSET Register (Offset = 5h) [Reset = 0000h] Return to the Register Map . DAC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-0 OFFSET R/W 0h OffsetAdjust the offset of the DAC output, 2's complement number. For example: 0000h = 0 (default) FFFFh = –1 DAC_CLR_CODE Register (Offset = 6h) [Reset = 0000h] Return to the Register Map . DAC_CLR_CODE Register Field Descriptions Bit Field Type Reset Description 15-0 CODE R/W 0h CLEAR State DAC CodeDAC code applied in the CLEAR state. See . RESET Register (Offset = 7h) [Reset = 0000h] Return to the Register Map . RESET Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-0 SW_RST WSC 0h Software Reset Write ADh to initiate software reset. ADC_CFG Register (Offset = 8h) [Reset = 8810h] Return to the Register Map . ADC_CFG Register Field Descriptions Bit Field Type Reset Description 15 BUF_PD R/W 1h ADC Buffer Power-Down 0h = ADC buffer enabled; 1h = ADC buffer powered down (default) 14-8 HYST R/W 8h HysteresisThe number of codes of hysteresis used when a threshold is exceeded for an ADC measurement of AIN0/AIN1/TEMP. 7-5 FLT_CNT R/W 0h Fault Count Number of successive faults to trip an alarm.Number of successive faults is programmed value + 1 (1-8 faults). 4 AIN_RANGE R/W 1h ADC Analog Input Range Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs. 0h = 2 × VREF; 1h = 1 × VREF (default) 3 EOC_PER_CH R/W 0h ADC End-of-Conversion for Every ChannelSends an EOC pulse at the end of each channel instead of at the end of all the channels.0h = EOC after last channel (default); 1h = EOC for every channel 2-1 CONV_RATE R/W 0h ADC Conversion RateThis setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based on a 76.8-kHz ADC clock. All other channels use 2560 Hz. 0h = 3840 Hz (default) 1h = 2560 Hz 2h = 1280 Hz 3h = 640 Hz 0 DIRECT_MODE R/W 0h Direct Mode Enable 0h = Auto mode (default); 1h = Direct mode ADC_INDEX_CFG Register (Offset = 9h) [Reset = 0080h] Return to the Register Map . The ADC custom channel sequencing configuration is shown in #GUID-121F6531-236F-4BFA-AA11-8CC4C580B655/GUID-84429441-E2D5-4137-992B-F0A3EE3367A1. ADC_INDEX_CFG Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-4 STOP R/W 8h Custom Channel Sequencer Stop IndexCCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START. 0h = OFFSET 1h = AIN0 2h = AIN1 3h = TEMP 4h = SD0 (VREF) 5h = SD1 (PVDD) 6h = SD2 (VDD) 7h = SD3 (ZTAT) 8h = SD4 (VOUT) (default) 9h through Fh = GND 3-0 START R/W 0h Custom Channel Sequencer Start IndexCCS index to start ADC sequence.0h through Fh = Same as STOP field (0h is default) TRIGGER Register (Offset = Ah) [Reset = 0000h] Return to the Register Map . TRIGGER Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED R 0h 3 RBIST WSC 0h RBIST Trigger This trigger initiates a Register BIST. This BIST runs a CRC calculation through the configuration registers () and compares the result to a stored CRC value in the RBIST_CRC register. 2 MBIST WSC 0h Memory Built-In Self-Test Trigger This trigger initiates an MBIST on the SRAM that is used for the FIFO. During this time communication to/from HART does not work as MBIST takes over the control of the SRAM. 1 SHADOWLOAD WSC 0h Shadow Load TriggerThis trigger initiates the loading of the OTP array into the parallel latches. If an OTP CRC error is detected, assert this trigger to try and reload the OTP into the memory locations. 0 ADC WSC 0h ADC TriggerIn auto mode, this bit enables or disables the conversions. Manually set to 1 (enable) or 0 (disable). In direct mode, set this bit to start a conversion sequence. The bit is cleared at the end of the sequence. To stop a sequence prematurely, manually clear this bit. SPECIAL_CFG Register (Offset = Bh) [Reset = 0000h] Return to the Register Map . SPECIAL_CFG Register Field Descriptions Bit Field Type Reset Description 15-3 RESERVED R 0h 2 OTP_LOAD_SW_RST R/W 0h OTP (One Time Programmable Factory Trimmed Registers) LOAD with SW RESETOTP reloads with the assertion of a software reset (SW_RST). 0h = No reload with SW_RST 1h = Reload with SW_RST 1 ALMV_POL R/W 0h Alarm Voltage PolarityThis register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB bit is low) to control the VOUT during a hardware reset condition or if alarm is active and alarm action is set appropriately. The following Boolean function is implemented for the internal signal ALMV_POL_o that sets the VOUT voltage:ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT AIN1_ENB) 0h = Low (0 V) 1h = High (2.5 V) 0 AIN1_ENB R/W 0h AIN1 Pin EnableThis bit determines whether the POL_SEL/AIN1 pin acts as alarm voltage polarity control bit or an input channel to the ADC. 0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts GND 1h = AIN1 pin is an active channel to the ADC MODEM_CFG Register (Offset = Eh) [Reset = 0040h] Return to the Register Map . MODEM_CFG Register Field Descriptions Bit Field Type Reset Description 15 Tx2200Hz R/W 0h Transmit 2200 Hz OnlyBy not sending data to the FIFO buffer and asserting RTS, the user can transmit multiples of 1200 Hz as long as RTS is asserted. By setting this bit the user can transmit multiples of 2200 Hz. Setting this bit prevents data in the FIFO buffer from being correctly transmitted. If using this bit there is no need to use the FIFO buffer. 0h = Transmit 1200 Hz and 2200 Hz (default) 1h = Transmit only 2200 Hz 14-13 RESERVED R 0h 12 DUPLEX_EXT R/W 0h Duplex External ModeAllows full duplex mode but expects the connection of MOD_OUT to RX_IN to be made externally. 0h = Internal duplex connection (default) 1h = External duplex connection 11 RX_HORD_EN R/W 0h High Order Filter EnableEnables a higher order filter on HART_RX. 0h = Disable (default); 1h = Enable 10 RX_EXTFILT_EN R/W 0h External Filter EnableEnables the use of an external filter for HART_RX. If enabled, then connect the HART signal to RX_INF. 0h = Use internal filter (default); 1h = Use external filter 9 TxRES R/W 0h HART Transmit Resolution0h = 32 steps per period (default) at 38.4 kHz update rate for 1200 baud 1h = 128 steps per period at 153.6 kHz update rate for 1200 baud 128-step per period waveform consumes more power. 8-4 TxAMP R/W 4h Transmit AmplitudeHART Tx amplitude. 00h = 400 mVPP; 01h = 425 mVPP 02h = 450 mVPP; 03h = 475 mVPP 04h = 500 mVPP (default); 05h = 525 mVPP 06h = 550 mVPP; 07h = 575 mVPP 08h = 600 mVPP; 09h = 625 mVPP 0Ah = 650 mVPP; 0Bh = 675 mVPP 0Ch = 700 mVPP; 0Dh = 725 mVPP 0Eh = 750 mVPP; 0Fh = 775 mVPP 10h through 1Fh = 800 mVPP 3 HART_EN R/W 0h HART EnableEnable the HART Tx and Rx.0h = Disable (default); 1h = Enable 2 DUPLEX R/W 0h Duplex ModeEnable internal connection of Tx to Rx for debug and testing.0h = Normal operation (default); 1h = Duplex enabled 1 TxHPD R/W 0h HART Tx DAC Output Buffer Hi-Z in Rx Mode or When Disabled0h = HART Tx DAC output is set to midcode with 50 kΩ output impedance (default) 1h = HART Tx DAC is Hi-Z in Rx mode or when disabled. Users can set the default voltage level with an external circuit. 0 RTS R/W 0h Request To Send Starts transmitting a carrier on MOD_OUT pin.0h = No action (default) 1h = Request to send. Device starts modulating the MOD_OUT pin if CD = 0. FIFO_CFG Register (Offset = Fh) [Reset = 00F0h] Return to the Register Map . FIFO_CFG Register Field Descriptions Bit Field Type Reset Description 15-10 RESERVED R 0h 9 FIFO_H2U_FLUSH WSC 0h Flush HART-to-µC FIFO (FIFO_H2U) Clear the pointers for the FIFO_H2U. 8 FIFO_U2H_FLUSH WSC 0h Flush µC-to-HART FIFO (FIFO_U2H) Clear the pointers for the FIFO_U2H. 7-4 H2U_LEVEL_SET R/W Fh FIFO_H2U FIFO Level Flag Trip SetSets the level for FIFO_H2U at which the Level Flag trips. This is a (>) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. 3-0 U2H_LEVEL_SET R/W 0h FIFO_U2H FIFO Level Flag Trip SetSets the level for FIFO_U2H at which the Level Flag trips. This is a (<) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. ALARM_ACT Register (Offset = 10h) [Reset = 8020h] Return to the Register Map . ALARM_ACT Register Field Descriptions Bit Field Type Reset Description 15-14 SD_FLT R/W 2h Self-Diagnostic Fault Action These bits set the device action after a self-diagnostic fault. 0h = No Action 1h = Set DAC to CLEAR state 2h = Switch to alarm voltage determined by ALMV_POL (default) 3h = Place DAC into Hi-Z (power-down) 13-12 TEMP_FLT R/W 0h TEMP Fault ActionThese bits set the device action if the ADC temperature is outside the TEMP_THRESHOLD Hi or Lo thresholds.0h through 3h = Same as SD_FLT field (default 0h) 11-10 AIN1_FLT R/W 0h AIN1 Fault ActionThese bits set the device action if the ADC AIN1 channel is outside the AIN1_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 9-8 AIN0_FLT R/W 0h AIN0 Fault Action These bits set the device action if the ADC AIN0 channel is outside the AIN0_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 7-6 CRC_WDT_FLT R/W 0h CRC and WDT Fault ActionThese bits set the device action when a SPI CRC or SPI Watchdog Timeout error occurs. 0h through 3h = Same as SD_FLT field (default 0h) 5-4 VREF_FLT R/W 2h VREF Fault ActionThese bits set the device action when a fault is detected on VREF. 0h through 3h = Same as SD_FLT field a 3-2 THERM_ERR_FLT R/W 0h Thermal Error Fault ActionThese bits set the device action when a high temperature error occurs (> 130°C). 0h through 3h = Same as SD_FLT field (default 0h) 1-0 THERM_WARN_FLT R/W 0h Thermal Warning Fault ActionThese bits set the device action when a high temperature warning occurs (> 85°C). 0h through 3h = Same as SD_FLT field (default 0h) WDT Register (Offset = 11h) [Reset = 0018h] Return to the Register Map . WDT Register Field Descriptions Bit Field Type Reset Description 15-6 RESERVED R 0h 5-3 WDT_UP R/W 3h Watchdog Timer (WDT) Upper LimitIf the WDT is enabled and the timer exceeds the programmed value, a WDT error is asserted. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = 53 ms (64 clocks) 1h = 106 ms (128 clocks) 2h = 427 ms (512 clocks) 3h = 853 ms (1024 clocks, default) 4h = 1.7 s (2048 clocks) 5h = 2.56 s (3072 clocks) 6h = 3.41 s (4096 clocks) 7h = 5.12 s (6144 clocks) 2-1 WDT_LO R/W 0h WDT Lower LimitIf the WDT is enabled and the WDT Lower Limit is enabled, then only a write to this register resets the WDT timer. If the write occurs before the WDT Lower Limit time, or after the WDT Upper Limit time, then a WDT error is asserted. If WDT Lower Limit is disabled, then a write to any register resets the timer. This is true for both SPI and UART Break modes. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = Disabled (default) 1h = 53 ms (64 clocks) 2h = 106 ms (128 clocks) 3h = 427 ms (512 clocks) 0 WDT_EN R/W 0h WDT Enable 0h = Disabled (default); 1h = Enabled AIN0_THRESHOLD Register (Offset = 12h) [Reset = FF00h] Return to the Register Map . AIN0_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN0 {[11:4],4b1111} This value is compared (>) against AIN0 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN0 {[11:4],4b0000} This value is compared (<) against AIN0 data bits[11:0]. AIN1_THRESHOLD Register (Offset = 13h) [Reset = FF00h] Return to the Register Map . AIN1_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN1 {[11:4],4b1111} This value is compared (>) against AIN1 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN1 {[11:4],4b0000} This value is compared (<) against AIN1 data bits[11:0]. TEMP_THRESHOLD Register (Offset = 14h) [Reset = FF00h] Return to the Register Map . TEMP_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel TEMP {[11:4],4b1111} This value is compared (>) against TEMP data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel TEMP {[11:4],4b0000} This value is compared (<) against TEMP data bits[11:0]. FIFO_U2H_WR Register (Offset = 15h) [Reset = 0000h] Return to the Register Map . This register controls the HART to microcontroller FIFO buffer. FIFO_U2H_WR Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h 8 PARITY WO 0h ParityOdd parity bit to be transmitted with data. This field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. 7-0 DATA WO 0h Data ByteThis field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. UBM Register (Offset = 16h) [Reset = 0000h] Return to the Register Map . UBM Register Field Descriptions Bit Field Type Reset Description 15-1 RESERVED R 0h 0 REG_MODE R/W 0h Register ModeConfigure the rest of the Register Map to be accessed by UART break mode (UBM) or SPI. This register can only be written by the UART Break communication.0h = SPI Mode (default) 1h = UART Break Mode SCRATCH Register (Offset = 18h) [Reset = FFFFh] Return to the Register Map . SCRATCH Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W FFFFh Scratch Data Data written is read back as the inverted value. For example, writing 0xAAAA is read back as 0x5555. CHIP_ID_LSB Register (Offset = 19h) Return to the Register Map . CHIP ID LSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Unique part number within each lot CHIP_ID_MSB Register (Offset = 1Ah) Return to the Register Map . CHIP ID MSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Encoded lot identification number GPIO_CFG Register (Offset = 1Bh) [Reset = 00FFh] Return to the Register Map . GPIO CONFIG Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R 0h 14-8 EN R/W 00h GPIO per Pin Enable. (See for additional configuration required specific to each pin and communication mode) [14] = GPIO6 [13] = GPIO5 [12] = GPIO4 [11] = GPIO3 [10] = GPIO2 [9] = GPIO1 [8] = GPIO00h = GPIO function disable1h = GPIO function enabledFor any pin used either for the communication function or not used as an active GPIO, set this bit to 0h. 7 RESERVED R 0h 6-0 ODE R/W FFh Pseudo Open Drain EnableGPIO output enable and pseudo open drain functionality on the GPIO pins. (See for additional configuration required specific to each pin and communication mode.) [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO00h = Push-pull output enabled1h = Pseudo open-drain output enabled GPIO Register (Offset = 1Ch) [Reset = 007Fh] Return to the Register Map . GPIO Register Field Descriptions Bit Field Type Reset Description 15-7 RESERVED R 0h 6-0 DATA R/W 7Fh GPIO pin data. For GPIO input this bit must be written as 1 and GPIO_CFG.ODE = 1 and GPIO_CFG.EN = 1. Reading this register reads the pin value when the pin is correctly enabled. (See for additional configuration required specific to each pin and communication mode) For GPIO output this bit sets the pin value. [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO0 ALARM_STATUS_MASK Register (Offset = 1Dh) [Reset = EFDFh] Return to the Register Map . ALARM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-14 RESERVED R 3h 13 SD_FLT R/W 1h SD Fault Mask0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 12 OSC_FAIL R/W 0h OSC_FAIL Fault Mask Same as SD Fault Mask (default 0h). 11-9 RESERVED R 7h 8 OTP_CRC_ERR R/W 1h OTP CRC Error Mask Same as SD Fault Mask (default 1h). 7 CRC_FLT R/W 1h SPI CRC Fault Mask Same as SD Fault Mask (default 1h). 6 WD_FLT R/W 1h Watchdog Fault Mask Same as SD Fault Mask (default 1h). 5 VREF_FLT R/W 0h VREF Fault Mask Same as SD Fault Mask (default 0h). 4 ADC_AIN1_FLT R/W 1h ADC AIN1 Fault Mask Same as SD Fault Mask (default 1h). 3 ADC_AIN0_FLT R/W 1h ADC AIN0 Fault Mask Same as SD Fault Mask (default 1h). 2 ADC_TEMP_FLT R/W 1h ADC TEMP Fault Mask Same as SD Fault Mask (default 1h). 1 THERM_ERR_FLT R/W 1h Temperature > 130°C Error Mask Same as SD Fault Mask (default 1h). 0 THERM_WARN_FLT R/W 1h Temperature > 85°C Warning Mask Same as SD Fault Mask (default 1h). GEN_STATUS_MASK Register (Offset = 1Eh) [Reset = FFFFh] Return to the Register Map . GEN_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-11 RESERVED R 1Fh 10 BIST_DONE R/W 1h BIST Done Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 9 BIST_FAIL R/W 1h BIST Failed Fault Mask Same as BIST Done Mask (default 1h). 8 RESERVED R 1h 7 SR_BUSYn R/W 1h Slew Rate Not Busy Mask Same as BIST Done Mask (default 1h). 6 ADC_EOC R/W 1h ADC End Of Conversion Mask Same as BIST Done Mask (default 1h). 5-4 RESERVED R 3h 3 BREAK_FRAME_ERR R/W 1h Break Frame Error Fault Mask Same as BIST Done Mask (default 1h). 2 BREAK_PARITY_ERR R/W 1h Break Parity Error Fault Mask Same as BIST Done Mask (default 1h). 1 UART_FRAME_ERR R/W 1h UART Frame Error Fault Mask Same as BIST Done Mask (default 1h). 0 UART_PARITY_ERR R/W 1h UART Parity Error Fault Mask Same as BIST Done Mask (default 1h). MODEM_STATUS_MASK Register (Offset = 1Fh) [Reset = FFFFh] Return to the Register Map . MODEM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R 7h 12 GAP_ERR R/W 1h HART Gap Error Fault Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 11 FRAME_ERR R/W 1h HART Frame Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 10 PARITY_ERR R/W 1h HART Parity (ODD) Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 9 FIFO_H2U_LEVEL_FLAG R/W 1h FIFO_H2U Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 8 FIFO_H2U_FULL_FLAG R/W 1h FIFO_H2U Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 7 FIFO_H2U_EMPTY_FLAG R/W 1h FIFO_H2U Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 6 FIFO_U2H_LEVEL_FLAG R/W 1h FIFO_U2H Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 5 FIFO_U2H_FULL_FLAG R/W 1h FIFO_U2H Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 4 FIFO_U2H_EMPTY_FLAG R/W 1h FIFO_U2H Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 3 CD_DEASSERT R/W 1h CD Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 2 CD_ASSERT R/W 1h CD Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 1 CTS_DEASSERT R/W 1h CTS Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 0 CTS_ASSERT R/W 1h CTS Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). ALARM_STATUS Register (Offset = 20h) [Reset = 0200h] Return to the Register Map . ALARM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 SD_FLT R 0h Self Diagnostic (SD) Fault0h = All self diagnostic channels are within threshold limits 1h = At least one of the self diagnostic channels has failed 12 OSC_FAIL R 0h Oscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed IRQ.0h = Oscillator started; 1h = Oscillator has failed to start 11-10 CRC_CNT R 0h CRC Fault CounterIf counter limit ≤ 4 then bits[1:0] of the counter are shown here. If the counter limit = 8 then bits[2:1] of the counter are shown. 9 OTP_LOADEDn R 1h OTP NOT Loaded Clears when OTP has loaded at least once. Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ.0h = OTP has loaded at least once; 1h = OTP has not finished loading 8 OTP_CRC_ERR R 0h OTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation. Sticky, cleared by reading register, unless condition still persist.0h = No OTP CRC fault; 1h = OTP CRC fault 7 CRC_FLT R 0h CRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame. Sticky, cleared by reading register, unless condition still persist.0h = No CRC fault; 1h = CRC fault 6 WD_FLT R 0h Watchdog Timer Fault Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No watchdog fault; 1h = Watchdog fault 5 VREF_FLT R 0h Invalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Valid VREF voltage; 1h = Invalid VREF voltage 4 ADC_AIN1_FLT R 0h ADC AIN1 Fault. Maskable fault. 0h = AIN1 ADC measurement within threshold limits 1h = AIN1 ADC measurement outside threshold limits 3 ADC_AIN0_FLT R 0h ADC AIN0 Fault. Maskable fault. 0h = AIN0 ADC measurement within threshold limits 1h = AIN0 ADC measurement outside threshold limits 2 ADC_TEMP_FLT R 0h ADC Temp Fault. Maskable fault. 0h = TEMP ADC measurement within threshold limits 1h = TEMP ADC measurement outside threshold limits 1 THERM_ERR_FLT R 0h Temperature > 130°C error. Maskable fault. OR with FORCE_FAIL.THERM_ERR_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C 0 THERM_WARN_FLT R 0h Temperature > 85°C warning. Maskable fault. OR with FORCE_FAIL.THERM_WARN_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C GEN_STATUS Register (Offset = 21h) [Reset = 1180h] Return to the Register Map . GEN_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 RESERVED R 0h 12 OTP_BUSY R 1h OTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches.0h = OTP has completed loading into the device 1h = OTP is being loaded into the device 11 BIST_MODE R 0h Denotes which BIST is being run.0h = MBIST; 1h = RBIST 10 BIST_DONE R 0h BIST Completed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has not completed; 1h = BIST has completed 9 BIST_FAIL R 0h BIST Failed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has passed; 1h = BIST has failed 8 RESET R 1h Device Reset Occurred. Status only. Does not feed IRQ.Sticky, cleared by reading register, unless condition still persist. 0h = Device has not reset since last read of register 1h = Device has reset since last read of register 7 SR_BUSYn R 1h Slew Rate Not Busy. Maskable fault. 0h = DAC is slewing to the target code1h = DAC_OUT has reached the DAC_DATA. If slew rate is disabled, then this signal produces a rising edge within 3 internal clock cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can cause an unwanted fast transition on VOUT. 6 ADC_EOC R 0h ADC End of Conversion (EOC). Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No EOC since last read of register; 1h = ADC end of conversion 5 ADC_BUSY R 0h ADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true. 0h = No ADC activity; 1h = ADC is actively converting 4 PVDD_HI R 0h PVDD High. Status only. Does not feed IRQ. Set as long as condition is true. 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7 V 3 BREAK_FRAME_ERR R 0h Incorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break frame error; 1h = Break frame error 2 BREAK_PARITY_ERR R 0h Incorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break parity error; 1h = Break parity error 1 UART_FRAME_ERR R 0h Incorrect Stop Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART frame error; 1h = UART frame error 0 UART_PARITY_ERR R 0h Incorrect Parity (ODD) Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART parity error; 1h = UART parity error MODEM_STATUS Register (Offset = 22h) [Reset = 009Ah] Return to the Register Map . MODEM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 13 RESERVED R 0h 12 GAP_ERR R 0h HART Gap Error. Maskable fault. Applies to RX_IN/RX_INF. Too much time (11 bit times) between HART characters. Sticky, cleared by reading register, unless condition still persist. Fatal Fault.0h = No HART gap error; 1h = HART gap error 11 FRAME_ERR R 0h Incorrect Stop Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. Fatal Fault. 0h = No HART frame error; 1h = HART frame error 10 PARITY_ERR R 0h Incorrect Parity (ODD) Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. 0h = No HART parity error; 1h = HART parity error 9 FIFO_H2U_LEVEL_FLAG R 0h FIFO HART-to-µC Level Flag. Maskable fault. If the level of the FIFO_H2U is full, then the level flag is not asserted, but the full flag is, so no information is lost.0h = FIFO_H2U level ≤ {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 1h = FIFO_H2U level > {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 8 FIFO_H2U_FULL_FLAG R 0h FIFO HART-to-µC Full Flag. Maskable fault. 0h = FIFO_H2U is not full; 1h = FIFO_H2U is full 7 FIFO_H2U_EMPTY_FLAG R 1h FIFO HART-to-µC Empty Flag. Maskable fault. 0h = FIFO_H2U is not empty; 1h = FIFO_H2U is empty 6 FIFO_U2H_LEVEL_FLAG R 0h FIFO µC-to-HART Level Flag. Maskable fault. FIFO_U2H < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0}. When the FIFO_U2H is empty, this flag is set unless FIFO_CFG.U2H_LEVEL_SET = 0. This flag and the empty flag can be set at the same time.0h = FIFO_U2H level ≥ {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 1h = FIFO_U2H level < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 5 FIFO_U2H_FULL_FLAG R 0h FIFO µC-to-HART Full Flag. Maskable fault. 0h = FIFO_U2H is not full; 1h = FIFO_U2H is full 4 FIFO_U2H_EMPTY_FLAG R 1h FIFO µC-to-HART Empty Flag. Maskable fault. 0h = FIFO_U2H is not empty; 1h = FIFO_U2H is empty 3 CD_DEASSERT R 1h Carrier Detect Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is asserted; 1h = Carrier detect is deasserted 2 CD_ASSERT R 0h Carrier Detect Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is deasserted; 1h = Carrier detect is asserted 1 CTS_DEASSERT R 1h Clear To Send Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is asserted; 1h = Clear to send is deasserted 0 CTS_ASSERT R 0h Clear To Send Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is deasserted; 1h = Clear to send is asserted ADC_FLAGS Register (Offset = 23h) [Reset = 0000h] Return to the Register Map .The limits for Self Diagnostic (SD) Alarm ADC Thresholds are shown in . ADC_FLAGS Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h 8 SD4_FAIL R 0h SD4 (VOUT) Limit Fail 7 SD3_FAIL R 0h SD3 (ZTAT) Limit Fail 6 SD2_FAIL R 0h SD2 (VDD) Limit Fail 5 SD1_FAIL R 0h SD1 (PVDD) Limit Fail 4 SD0_FAIL R 0h SD0 (VREF) Limit Fail 3 TEMP_FAIL R 0h TEMP Limit Fail 2 AIN1_FAIL R 0h AIN1 Limit Fail 1 AIN0_FAIL R 0h AIN0 Limit Fail 0 RESERVED R 0h ADC_AIN0 Register (Offset = 24h) [Reset = 0000h] Return to the Register Map . ADC_AIN0 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN0 ADC_AIN1 Register (Offset = 25h) [Reset = 0000h] Return to the Register Map . ADC_AIN1 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN1 ADC_TEMP Register (Offset = 26h) [Reset = 0000h] Return to the Register Map . ADC_TEMP Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Temperature ADC_SD_MUX Register (Offset = 27h) [Reset = 0000h] Return to the Register Map . ADC_SD_MUX Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Self-Diagnostic (SD) MUX Input ADC_OFFSET Register (Offset = 28h) [Reset = 0000h] Return to the Register Map . ADC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Comparator Offset This value reports the offset measured in the device, and can be used to adjust each conversion value. If ADC_BYP.OFST_BYP_EN is set, then the value in ADC_BYP.DATA is used as the offset. This value is not affected by ADC_BYP. FIFO_H2U_RD Register (Offset = 2Ah) [Reset = 0200h] Return to the Register Map . FIFO_H2U_RD Register Field Descriptions Bit Field Type Reset Description 15-12 LEVEL R 0h LevelCurrent Level of FIFO_H2U, bits [4:1] represented as Level[3:0]. Pre-dequeue. 11 LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO_H2U Level > {Level,1b1}. Pre-dequeue.0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 FULL_FLAG R 0h HART-to-µC FIFO Full Flag. Pre-dequeue. 0h = FIFO_H2U is not full, pre-dequeue 1h = FIFO_H2U is full, pre-dequeue 9 EMPTY_FLAG R 1h HART-to-µC FIFO Empty Flag. Pre-dequeue. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 PARITY R 0h Parity Bit (ODD)Parity bit received with data on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. 7-0 DATA R 0h Data8-bit data received on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. FIFO_STATUS Register (Offset = 2Bh) [Reset = 0202h] Return to the Register Map . The FIFO_STATUS register is provided to allow the user to view the state of both FIFOs without enqueuing or dequeuing data in the FIFO. This also allows the flags to be viewed without disturbing other status bits in the MODEM_STATUS register. This register is provided to enable users to check the FIFO status register without disturbing other functions within the device. FIFO_STATUS Register Field Descriptions Bit Field Type Reset Description 15-12 H2U_LEVEL R 0h HART-to-µC FIFO LevelCurrent level of FIFO_H2U, right shifted 1 bit (>>1) so only even counts are represented. 11 H2U_LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO Level > {Level,1b1}. 0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 H2U_FULL_FLAG R 0h HART-to-µC FIFO Full FlagSet when FIFO is full. 0h = FIFO_H2U is not full 1h = FIFO_H2U is full 9 H2U_EMPTY_FLAG R 1h HART-to-µC Empty FlagSet when FIFO is empty. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 RESERVED R 0h 7-4 U2H_LEVEL R 0h µC-to-HART FIFO LevelCurrent level of FIFO_U2H, right shifted 1 bit (>>1) so only even counts are represented 3 U2H_LEVEL_FLAG R 0h µC-to-HART FIFO Level FlagSet when FIFO_U2H Level < {Level,1b0}. 0h = FIFO_U2H level ≥ {Level, 1b0} 1h = FIFO_U2H level < {Level, 1b0} 2 U2H_FULL_FLAG R 0h µC-to-HART Full FlagSet when FIFO_U2H is full. 0h = FIFO_U2H is not full 1h = FIFO_U2H is full 1 U2H_EMPTY_FLAG R 1h µC-to-HART Empty FlagSet when FIFO_U2H is empty. 0h = FIFO_U2H is not empty 1h = FIFO_U2H is empty 0 RESERVED R 0h DAC_OUT Register (Offset = 2Ch) [Reset = 0000h] Return to the Register Map . DAC_OUT Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R 0h DAC Code Applied to the Analog Circuit ADC_OUT Register (Offset = 2Dh) [Reset = 0000h] Return to the Register Map . ADC_OUT Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Data for Each Conversion Does not include ADC_OFFSET.DATA adjustment. Is not affected by ADC_BYP.DATA. ADC_BYP Register (Offset = 2Eh) [Reset = 0000h] Return to the Register Map . ADC_BYP is shown in ADC_BYP Register Field Descriptions . ADC_BYP Register Field Descriptions Bit Field Type Reset Description 15 DATA_BYP_EN R/W 0h Data Bypass EnableApplies ADC_BYP.DATA to the ADC channel being converted. ADC_OFFSET is ignored. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. If OFST_BYP_EN is also set, DATA_BYP_EN takes priority over OFST_BYP_EN. After a channel is converted, the ADC_BYP.DATA value appears in the readback register for the converted channel and is used to calculate faults. 0h = Data bypass disabled (default) 1h = Data bypass enabled 14 OFST_BYP_EN R/W 0h Offset Bypass EnableOverrides the offset register with the ADC_BYP.DATA value. When using this bit, the ADC_BYP.DATA field is processed as 2's complement. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time.0h = Offset bypass disabled (default) 1h = Offset bypass enabled 13 DIS_GND_SAMP R/W 0h Disable GND SamplingThis bit disables the sampling of GND during SAR activity. The sampling of GND is used to fully discharge the sampling CAP to reduce channel crosstalk. 0h = GND sampling enabled (default) 1h = GND sampling disabled 12 RESERVED R 0h 11-0 DATA R/W 0h Bypass Data FORCE_FAIL Register (Offset = 2Fh) [Reset = 0000h] Return to the Register Map . Force failures for fault detection. FORCE_FAIL Register Field Descriptions Bit Field Type Reset Description 15 CRC_FLT R/W 0h Force CRC Failure on SDO by Inverting the CRC Byte 0h = No force failure of CRC (default) 1h = Force failure of CRC 14 VREF_FLT R/W 0h Force Reference Voltage Failure. Analog signal.0h = No force failure of VREF (default) 1h = Force failure of VREF 13 THERM_ERR_FLT R/W 0h Force Temperature > 130°C Thermal Error. Analog signal.0h = No force temperature > 130°C error (default) 1h = Force temperature > 130°C error 12 THERM_WARN_FLT R/W 0h Force Temperature > 85°C thermal Warning. Analog signal.0h = No force temperature > 85°C warning (default) 1h = Force temperature > 85°C warning 11-10 RESERVED R/W 0h 9 SD4_HI_FLT R/W 0h SD4 (VOUT) High Limit Failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 8 SD4_LO_FLT R/W 0h SD4 (VOUT) Low limit failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 7 SD3_HI_FLT R/W 0h SD3 (ZTAT) High Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 6 SD3_LO_FLT R/W 0h SD3 (ZTAT) Low Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 5 SD2_HI_FLT R/W 0h SD2 (VDD) High Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 4 SD2_LO_FLT R/W 0h SD2 (VDD) Low Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 3 SD1_HI_FLT R/W 0h SD1 (PVDD) High Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 2 SD1_LO_FLT R/W 0h SD1 (PVDD) Low Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 1 SD0_HI_FLT R/W 0h SD0 (VREF) High Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 0 SD0_LO_FLT R/W 0h SD0 (VREF) Low Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) TIMER_CFG_0 Register (Offset = 3Bh) [Reset = 0000h] Return to the Register Map . TIMER Configuration 0. TIMER CONFIG 0 Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED TO 0h 3-2 CLK_SEL R/W 0h Clock SelectSelects the timer clock frequency. 0h = None (default) 1h = 1.2288 MHz 2h = 1.200 kHz 3h = 1.171 Hz 1 INVERT R/W 0h Invert OutputInvert the Timer output. By default, the output is set to 1 when the counter is ≥ SET_TIME (3Dh). 0 ENABLE R/W 0h Timer Enable The CLK_OUT pin must also be configured to output the Timer. TIMER_CFG_1 Register (Offset = 3Ch) [Reset = 0000h] Return to the Register Map . TIMER Configuration 1. TIMER CONFIG 1 Register Field Descriptions Bit Field Type Reset Description 15-0 PERIOD R/W 0h This field defines the period of the timer. The period is the product of (PERIOD + 1) and the clock period of CLK_SEL. For example, CLK_SEL = 2h (1200 Hz), The period is (PERIOD + 1) × 853 ms. TIMER_CFG_2 Register (Offset = 3Dh) [Reset = 0000h] Return to the Register Map . TIMER Configuration 2. TIMER CONFIG 2 Register Field Descriptions Bit Field Type Reset Description 15-0 SET_TIME R/W 0h The SET_TIME determine when the output of the timer goes high. The bits define the duty cycle of the timer (PERIOD – SET_TIME). The timer starts out as 0 and transitions to 1 when the SET_TIME is met. The polarity of the timer can be inverted using the TIMER_CFG_0.INVERT bit. CRC_RD Register (Offset = 3Eh) [Reset = 0000h] Return to the Register Map . CRC read. CRC Read Register Field Descriptions Bit Field Type Reset Description 15-0 CRC R/O 0h Calculated CRC for RBIST or SHADOWLOAD. Final value is calculated internally. This value changes while RBIST or shadow load are running. RBIST_CRC Register (Offset = 3Fh) [Reset = 0000h] Return to the Register Map . RBIST CRC. RBIST CRC Register Field Descriptions Bit Field Type Reset Description 15-0 RBIST CRC R/W 0h Calculated CRC for Register RBIST Complex bit access types are encoded to fit into small table cells. The following table shows the codes that are used for access types in this section. AFEx82H1 Access-Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W WO Write only W WSC Write self clear Reset or Default Value -n Value after reset or the default value Register Array Variables i,j,k,l,m,n When used in a register name, an offset, or an address, these variables refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. y When used in a register name, an offset, or an address, this variable refers to the value of a register array. Complex bit access types are encoded to fit into small table cells. The following table shows the codes that are used for access types in this section. AFEx82H1 Access-Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W WO Write only W WSC Write self clear Reset or Default Value -n Value after reset or the default value Register Array Variables i,j,k,l,m,n When used in a register name, an offset, or an address, these variables refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. y When used in a register name, an offset, or an address, this variable refers to the value of a register array. AFEx82H1 Access-Type CodesAFEx82H1 Access Type Code Description Read Type R R Read Write Type W W Write W WO Write only W WSC Write self clear Reset or Default Value -n Value after reset or the default value Register Array Variables i,j,k,l,m,n When used in a register name, an offset, or an address, these variables refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. y When used in a register name, an offset, or an address, this variable refers to the value of a register array. Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write W WO Write only W WSC Write self clear Reset or Default Value -n Value after reset or the default value Register Array Variables i,j,k,l,m,n When used in a register name, an offset, or an address, these variables refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. y When used in a register name, an offset, or an address, this variable refers to the value of a register array. Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite W WO Write only WWOWrite only W WSC Write self clear WWSCWrite self clear Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value Register Array Variables Register Array Variables i,j,k,l,m,n When used in a register name, an offset, or an address, these variables refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. i,j,k,l,m,nWhen used in a register name, an offset, or an address, these variables refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. y When used in a register name, an offset, or an address, this variable refers to the value of a register array. yWhen used in a register name, an offset, or an address, this variable refers to the value of a register array. NOP Register (Offset = 0h) [Reset = 0000h] Return to the Register Map . NOP Register Field Descriptions Bit Field Type Reset Description 15-0 NOP WO 0h No operation. Data written to this field have no effect. Always reads zeros. NOP Register (Offset = 0h) [Reset = 0000h] NOPReturn to the Register Map . Register Map Register Map NOP Register Field Descriptions Bit Field Type Reset Description 15-0 NOP WO 0h No operation. Data written to this field have no effect. Always reads zeros. NOP Register Field Descriptions Bit Field Type Reset Description 15-0 NOP WO 0h No operation. Data written to this field have no effect. Always reads zeros. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 NOP WO 0h No operation. Data written to this field have no effect. Always reads zeros. 15-0 NOP WO 0h No operation. Data written to this field have no effect. Always reads zeros. 15-0NOPWO0h No operation. Data written to this field have no effect. Always reads zeros. DAC_DATA Register (Offset = 1h) [Reset = 0000h] Return to the Register Map . DAC code for VOUT. DAC_DATA Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W 0h Data. DAC code for VOUT. DAC_DATA Register (Offset = 1h) [Reset = 0000h] DAC_DATAReturn to the Register Map . Register Map Register MapDAC code for VOUT. DAC_DATA Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W 0h Data. DAC code for VOUT. DAC_DATA Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W 0h Data. DAC code for VOUT. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 DATA R/W 0h Data. DAC code for VOUT. 15-0 DATA R/W 0h Data. DAC code for VOUT. 15-0DATAR/W0hData. DAC code for VOUT. CONFIG Register (Offset = 2h) [Reset = 0036h] Return to the Register Map . CONFIG Register Field Descriptions Bit Field Type Reset Description 15-14 CRC_ERR_CNT R/W 0h CRC Errors Count LimitSets the numbers of consecutive SPI CRC frames that must have errors before the status bits is set. 0h = 1 (default); 1h = 2; 2h = 4; 3h = 8 13-10 CLKO R/W 0h CLKO EnableEnable the CLK_OUT pin and set the divider value. 0h = CLKO disabled (default); 1h = 1.2288 MHz; 2h = 1.2288 / 2 MHz; 3h = 1.2288 / 4 MHz; 4h = 1.2288 / 8 MHz; 5h = 1.2288 / 16 MHz; 6h =1.2288 / 32 MHz; 7h = 1.2288 / 64 MHz; 8h = 1.2288 / 128 MHz; 9h = 1.2288 / 256 MHz; Ah = 1.2288 / 512 MHz; Bh = 1.2288 / 1024 MHz; Ch = 1'b0; Dh = 1'b0; Eh = 1'b0; Fh = Timer 9 UBM_IRQ_EN R/W 0h UBM IRQ EnableEnable IRQ to be sent on UARTOUT through UBM.0h = Disabled (default); 1h = Enabled 8 IRQ_PIN_EN R/W 0h IRQ Pin EnableEnable IRQ pin functionality.0h = Disabled (default); 1h = Enabled 7 CLR_PIN_EN R/W 0h Clear Input Pin EnableEnable pin-based transition to the CLEAR state in UBM.0h = Disabled (default); 1h = SDI pin configured as clear input pin 6 UART_DIS R/W 0h UART DisableDisable UART functionality.0h = UART Enabled (default); 1h = UART Disabled 5 UART_BAUD R/W 1h UART BaudConfigure BAUD rate for UART.0h = 1200 baud (no break); 1h = 9600 baud (Break mode) (default) 4 CRC_EN R/W 1h CRC EnableEnable CRC for SPI.0h = Disabled; 1h = Enabled (default) 3 IRQ_POL R/W 0h IRQ Polarity0h = Active low (default); 1h = Active high 2 IRQ_LVL R/W 1h IRQ Level0h = Edge sensitive; 1h = Level sensitive (default) 1 DSDO R/W 1h SDO Hi-Z0h = Drive SDO during CS = 0; 1h = SDO always Hi-Z (default) 0 FSDO R/W 0h Fast SDOSDO is driven on negative edge of SCLK.0h = drive SDO on rising edge of SCLK (launching edge) (default) 1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock early) CONFIG Register (Offset = 2h) [Reset = 0036h] CONFIGReturn to the Register Map . Register Map Register Map CONFIG Register Field Descriptions Bit Field Type Reset Description 15-14 CRC_ERR_CNT R/W 0h CRC Errors Count LimitSets the numbers of consecutive SPI CRC frames that must have errors before the status bits is set. 0h = 1 (default); 1h = 2; 2h = 4; 3h = 8 13-10 CLKO R/W 0h CLKO EnableEnable the CLK_OUT pin and set the divider value. 0h = CLKO disabled (default); 1h = 1.2288 MHz; 2h = 1.2288 / 2 MHz; 3h = 1.2288 / 4 MHz; 4h = 1.2288 / 8 MHz; 5h = 1.2288 / 16 MHz; 6h =1.2288 / 32 MHz; 7h = 1.2288 / 64 MHz; 8h = 1.2288 / 128 MHz; 9h = 1.2288 / 256 MHz; Ah = 1.2288 / 512 MHz; Bh = 1.2288 / 1024 MHz; Ch = 1'b0; Dh = 1'b0; Eh = 1'b0; Fh = Timer 9 UBM_IRQ_EN R/W 0h UBM IRQ EnableEnable IRQ to be sent on UARTOUT through UBM.0h = Disabled (default); 1h = Enabled 8 IRQ_PIN_EN R/W 0h IRQ Pin EnableEnable IRQ pin functionality.0h = Disabled (default); 1h = Enabled 7 CLR_PIN_EN R/W 0h Clear Input Pin EnableEnable pin-based transition to the CLEAR state in UBM.0h = Disabled (default); 1h = SDI pin configured as clear input pin 6 UART_DIS R/W 0h UART DisableDisable UART functionality.0h = UART Enabled (default); 1h = UART Disabled 5 UART_BAUD R/W 1h UART BaudConfigure BAUD rate for UART.0h = 1200 baud (no break); 1h = 9600 baud (Break mode) (default) 4 CRC_EN R/W 1h CRC EnableEnable CRC for SPI.0h = Disabled; 1h = Enabled (default) 3 IRQ_POL R/W 0h IRQ Polarity0h = Active low (default); 1h = Active high 2 IRQ_LVL R/W 1h IRQ Level0h = Edge sensitive; 1h = Level sensitive (default) 1 DSDO R/W 1h SDO Hi-Z0h = Drive SDO during CS = 0; 1h = SDO always Hi-Z (default) 0 FSDO R/W 0h Fast SDOSDO is driven on negative edge of SCLK.0h = drive SDO on rising edge of SCLK (launching edge) (default) 1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock early) CONFIG Register Field Descriptions Bit Field Type Reset Description 15-14 CRC_ERR_CNT R/W 0h CRC Errors Count LimitSets the numbers of consecutive SPI CRC frames that must have errors before the status bits is set. 0h = 1 (default); 1h = 2; 2h = 4; 3h = 8 13-10 CLKO R/W 0h CLKO EnableEnable the CLK_OUT pin and set the divider value. 0h = CLKO disabled (default); 1h = 1.2288 MHz; 2h = 1.2288 / 2 MHz; 3h = 1.2288 / 4 MHz; 4h = 1.2288 / 8 MHz; 5h = 1.2288 / 16 MHz; 6h =1.2288 / 32 MHz; 7h = 1.2288 / 64 MHz; 8h = 1.2288 / 128 MHz; 9h = 1.2288 / 256 MHz; Ah = 1.2288 / 512 MHz; Bh = 1.2288 / 1024 MHz; Ch = 1'b0; Dh = 1'b0; Eh = 1'b0; Fh = Timer 9 UBM_IRQ_EN R/W 0h UBM IRQ EnableEnable IRQ to be sent on UARTOUT through UBM.0h = Disabled (default); 1h = Enabled 8 IRQ_PIN_EN R/W 0h IRQ Pin EnableEnable IRQ pin functionality.0h = Disabled (default); 1h = Enabled 7 CLR_PIN_EN R/W 0h Clear Input Pin EnableEnable pin-based transition to the CLEAR state in UBM.0h = Disabled (default); 1h = SDI pin configured as clear input pin 6 UART_DIS R/W 0h UART DisableDisable UART functionality.0h = UART Enabled (default); 1h = UART Disabled 5 UART_BAUD R/W 1h UART BaudConfigure BAUD rate for UART.0h = 1200 baud (no break); 1h = 9600 baud (Break mode) (default) 4 CRC_EN R/W 1h CRC EnableEnable CRC for SPI.0h = Disabled; 1h = Enabled (default) 3 IRQ_POL R/W 0h IRQ Polarity0h = Active low (default); 1h = Active high 2 IRQ_LVL R/W 1h IRQ Level0h = Edge sensitive; 1h = Level sensitive (default) 1 DSDO R/W 1h SDO Hi-Z0h = Drive SDO during CS = 0; 1h = SDO always Hi-Z (default) 0 FSDO R/W 0h Fast SDOSDO is driven on negative edge of SCLK.0h = drive SDO on rising edge of SCLK (launching edge) (default) 1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock early) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-14 CRC_ERR_CNT R/W 0h CRC Errors Count LimitSets the numbers of consecutive SPI CRC frames that must have errors before the status bits is set. 0h = 1 (default); 1h = 2; 2h = 4; 3h = 8 13-10 CLKO R/W 0h CLKO EnableEnable the CLK_OUT pin and set the divider value. 0h = CLKO disabled (default); 1h = 1.2288 MHz; 2h = 1.2288 / 2 MHz; 3h = 1.2288 / 4 MHz; 4h = 1.2288 / 8 MHz; 5h = 1.2288 / 16 MHz; 6h =1.2288 / 32 MHz; 7h = 1.2288 / 64 MHz; 8h = 1.2288 / 128 MHz; 9h = 1.2288 / 256 MHz; Ah = 1.2288 / 512 MHz; Bh = 1.2288 / 1024 MHz; Ch = 1'b0; Dh = 1'b0; Eh = 1'b0; Fh = Timer 9 UBM_IRQ_EN R/W 0h UBM IRQ EnableEnable IRQ to be sent on UARTOUT through UBM.0h = Disabled (default); 1h = Enabled 8 IRQ_PIN_EN R/W 0h IRQ Pin EnableEnable IRQ pin functionality.0h = Disabled (default); 1h = Enabled 7 CLR_PIN_EN R/W 0h Clear Input Pin EnableEnable pin-based transition to the CLEAR state in UBM.0h = Disabled (default); 1h = SDI pin configured as clear input pin 6 UART_DIS R/W 0h UART DisableDisable UART functionality.0h = UART Enabled (default); 1h = UART Disabled 5 UART_BAUD R/W 1h UART BaudConfigure BAUD rate for UART.0h = 1200 baud (no break); 1h = 9600 baud (Break mode) (default) 4 CRC_EN R/W 1h CRC EnableEnable CRC for SPI.0h = Disabled; 1h = Enabled (default) 3 IRQ_POL R/W 0h IRQ Polarity0h = Active low (default); 1h = Active high 2 IRQ_LVL R/W 1h IRQ Level0h = Edge sensitive; 1h = Level sensitive (default) 1 DSDO R/W 1h SDO Hi-Z0h = Drive SDO during CS = 0; 1h = SDO always Hi-Z (default) 0 FSDO R/W 0h Fast SDOSDO is driven on negative edge of SCLK.0h = drive SDO on rising edge of SCLK (launching edge) (default) 1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock early) 15-14 CRC_ERR_CNT R/W 0h CRC Errors Count LimitSets the numbers of consecutive SPI CRC frames that must have errors before the status bits is set. 0h = 1 (default); 1h = 2; 2h = 4; 3h = 8 15-14CRC_ERR_CNTR/W0hCRC Errors Count LimitSets the numbers of consecutive SPI CRC frames that must have errors before the status bits is set. 0h = 1 (default); 1h = 2; 2h = 4; 3h = 8 13-10 CLKO R/W 0h CLKO EnableEnable the CLK_OUT pin and set the divider value. 0h = CLKO disabled (default); 1h = 1.2288 MHz; 2h = 1.2288 / 2 MHz; 3h = 1.2288 / 4 MHz; 4h = 1.2288 / 8 MHz; 5h = 1.2288 / 16 MHz; 6h =1.2288 / 32 MHz; 7h = 1.2288 / 64 MHz; 8h = 1.2288 / 128 MHz; 9h = 1.2288 / 256 MHz; Ah = 1.2288 / 512 MHz; Bh = 1.2288 / 1024 MHz; Ch = 1'b0; Dh = 1'b0; Eh = 1'b0; Fh = Timer 13-10CLKOR/W0hCLKO EnableEnable the CLK_OUT pin and set the divider value. 0h = CLKO disabled (default); 1h = 1.2288 MHz; 2h = 1.2288 / 2 MHz; 3h = 1.2288 / 4 MHz; 4h = 1.2288 / 8 MHz; 5h = 1.2288 / 16 MHz; 6h =1.2288 / 32 MHz; 7h = 1.2288 / 64 MHz; 8h = 1.2288 / 128 MHz; 9h = 1.2288 / 256 MHz; Ah = 1.2288 / 512 MHz; Bh = 1.2288 / 1024 MHz; Ch = 1'b0; Dh = 1'b0; Eh = 1'b0; Fh = Timer 9 UBM_IRQ_EN R/W 0h UBM IRQ EnableEnable IRQ to be sent on UARTOUT through UBM.0h = Disabled (default); 1h = Enabled 9UBM_IRQ_ENR/W0hUBM IRQ EnableEnable IRQ to be sent on UARTOUT through UBM.0h = Disabled (default); 1h = Enabled 8 IRQ_PIN_EN R/W 0h IRQ Pin EnableEnable IRQ pin functionality.0h = Disabled (default); 1h = Enabled 8IRQ_PIN_ENR/W0hIRQ Pin EnableEnable IRQ pin functionality.0h = Disabled (default); 1h = Enabled 7 CLR_PIN_EN R/W 0h Clear Input Pin EnableEnable pin-based transition to the CLEAR state in UBM.0h = Disabled (default); 1h = SDI pin configured as clear input pin 7CLR_PIN_ENR/W0hClear Input Pin EnableEnable pin-based transition to the CLEAR state in UBM.0h = Disabled (default); 1h = SDI pin configured as clear input pin 6 UART_DIS R/W 0h UART DisableDisable UART functionality.0h = UART Enabled (default); 1h = UART Disabled 6UART_DISR/W0hUART DisableDisable UART functionality.0h = UART Enabled (default); 1h = UART Disabled 5 UART_BAUD R/W 1h UART BaudConfigure BAUD rate for UART.0h = 1200 baud (no break); 1h = 9600 baud (Break mode) (default) 5UART_BAUDR/W1hUART BaudConfigure BAUD rate for UART.0h = 1200 baud (no break); 1h = 9600 baud (Break mode) (default) 4 CRC_EN R/W 1h CRC EnableEnable CRC for SPI.0h = Disabled; 1h = Enabled (default) 4CRC_ENR/W1hCRC EnableEnable CRC for SPI.0h = Disabled; 1h = Enabled (default) 3 IRQ_POL R/W 0h IRQ Polarity0h = Active low (default); 1h = Active high 3IRQ_POLR/W0hIRQ Polarity0h = Active low (default); 1h = Active high 2 IRQ_LVL R/W 1h IRQ Level0h = Edge sensitive; 1h = Level sensitive (default) 2IRQ_LVLR/W1hIRQ Level0h = Edge sensitive; 1h = Level sensitive (default) 1 DSDO R/W 1h SDO Hi-Z0h = Drive SDO during CS = 0; 1h = SDO always Hi-Z (default) 1DSDOR/W1hSDO Hi-Z0h = Drive SDO during CS = 0; 1h = SDO always Hi-Z (default)CS 0 FSDO R/W 0h Fast SDOSDO is driven on negative edge of SCLK.0h = drive SDO on rising edge of SCLK (launching edge) (default) 1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock early) 0FSDOR/W0hFast SDOSDO is driven on negative edge of SCLK.0h = drive SDO on rising edge of SCLK (launching edge) (default) 1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock early) DAC_CFG Register (Offset = 3h) [Reset = 0B00h] Return to the Register Map . DAC_CFG Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R/W 0h 12 PD R/W 0h DAC Output Buffer Power-down DAC output set to Hi-Z in power-down. 0h = DAC output buffer enabled (default) 1h = DAC output buffer disabled 11-9 SR_CLK R/W 5h Slew Clock Rate 0h = 307.2 kHz 1h = 153.6 kHz 2h = 76.8 kHz 3h = 38.4 kHz 4h = 19.2 kHz 5h = 9600 Hz (default) 6h = 4800 Hz 7h = 2400 Hz 8-6 SR_STEP R/W 4h Slew Step Size 0h = 1 code 1h = 2 codes 2h = 4 codes 3h = 8 codes 4h = 16 codes (default) 5h = 32 codes 6h = 64 codes 7h = 128 codes 5 SR_EN R/W 0h Slew Enable Enables slew on the output voltage. 0h = Disabled (default) 1h = Enabled 4 SR_MODE R/W 0h Slew Mode Output slew rate mode select. 0h = Linear Slew (default) 1h = Sinusoidal Slew 3 RESERVED R 0h 2 CLR R/W 0h CLEAR State 0h = Normal operation (default) 1h = Force the DAC to the CLEAR state 1-0 RESERVED R 0h DAC_CFG Register (Offset = 3h) [Reset = 0B00h] DAC_CFGReturn to the Register Map . Register Map Register Map DAC_CFG Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R/W 0h 12 PD R/W 0h DAC Output Buffer Power-down DAC output set to Hi-Z in power-down. 0h = DAC output buffer enabled (default) 1h = DAC output buffer disabled 11-9 SR_CLK R/W 5h Slew Clock Rate 0h = 307.2 kHz 1h = 153.6 kHz 2h = 76.8 kHz 3h = 38.4 kHz 4h = 19.2 kHz 5h = 9600 Hz (default) 6h = 4800 Hz 7h = 2400 Hz 8-6 SR_STEP R/W 4h Slew Step Size 0h = 1 code 1h = 2 codes 2h = 4 codes 3h = 8 codes 4h = 16 codes (default) 5h = 32 codes 6h = 64 codes 7h = 128 codes 5 SR_EN R/W 0h Slew Enable Enables slew on the output voltage. 0h = Disabled (default) 1h = Enabled 4 SR_MODE R/W 0h Slew Mode Output slew rate mode select. 0h = Linear Slew (default) 1h = Sinusoidal Slew 3 RESERVED R 0h 2 CLR R/W 0h CLEAR State 0h = Normal operation (default) 1h = Force the DAC to the CLEAR state 1-0 RESERVED R 0h DAC_CFG Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R/W 0h 12 PD R/W 0h DAC Output Buffer Power-down DAC output set to Hi-Z in power-down. 0h = DAC output buffer enabled (default) 1h = DAC output buffer disabled 11-9 SR_CLK R/W 5h Slew Clock Rate 0h = 307.2 kHz 1h = 153.6 kHz 2h = 76.8 kHz 3h = 38.4 kHz 4h = 19.2 kHz 5h = 9600 Hz (default) 6h = 4800 Hz 7h = 2400 Hz 8-6 SR_STEP R/W 4h Slew Step Size 0h = 1 code 1h = 2 codes 2h = 4 codes 3h = 8 codes 4h = 16 codes (default) 5h = 32 codes 6h = 64 codes 7h = 128 codes 5 SR_EN R/W 0h Slew Enable Enables slew on the output voltage. 0h = Disabled (default) 1h = Enabled 4 SR_MODE R/W 0h Slew Mode Output slew rate mode select. 0h = Linear Slew (default) 1h = Sinusoidal Slew 3 RESERVED R 0h 2 CLR R/W 0h CLEAR State 0h = Normal operation (default) 1h = Force the DAC to the CLEAR state 1-0 RESERVED R 0h Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-13 RESERVED R/W 0h 12 PD R/W 0h DAC Output Buffer Power-down DAC output set to Hi-Z in power-down. 0h = DAC output buffer enabled (default) 1h = DAC output buffer disabled 11-9 SR_CLK R/W 5h Slew Clock Rate 0h = 307.2 kHz 1h = 153.6 kHz 2h = 76.8 kHz 3h = 38.4 kHz 4h = 19.2 kHz 5h = 9600 Hz (default) 6h = 4800 Hz 7h = 2400 Hz 8-6 SR_STEP R/W 4h Slew Step Size 0h = 1 code 1h = 2 codes 2h = 4 codes 3h = 8 codes 4h = 16 codes (default) 5h = 32 codes 6h = 64 codes 7h = 128 codes 5 SR_EN R/W 0h Slew Enable Enables slew on the output voltage. 0h = Disabled (default) 1h = Enabled 4 SR_MODE R/W 0h Slew Mode Output slew rate mode select. 0h = Linear Slew (default) 1h = Sinusoidal Slew 3 RESERVED R 0h 2 CLR R/W 0h CLEAR State 0h = Normal operation (default) 1h = Force the DAC to the CLEAR state 1-0 RESERVED R 0h 15-13 RESERVED R/W 0h 15-13RESERVEDR/W0h 12 PD R/W 0h DAC Output Buffer Power-down DAC output set to Hi-Z in power-down. 0h = DAC output buffer enabled (default) 1h = DAC output buffer disabled 12PDR/W0hDAC Output Buffer Power-down DAC output set to Hi-Z in power-down. 0h = DAC output buffer enabled (default) 1h = DAC output buffer disabled DAC output set to Hi-Z in power-down.0h = DAC output buffer enabled (default)1h = DAC output buffer disabled 11-9 SR_CLK R/W 5h Slew Clock Rate 0h = 307.2 kHz 1h = 153.6 kHz 2h = 76.8 kHz 3h = 38.4 kHz 4h = 19.2 kHz 5h = 9600 Hz (default) 6h = 4800 Hz 7h = 2400 Hz 11-9SR_CLKR/W5hSlew Clock Rate 0h = 307.2 kHz 1h = 153.6 kHz 2h = 76.8 kHz 3h = 38.4 kHz 4h = 19.2 kHz 5h = 9600 Hz (default) 6h = 4800 Hz 7h = 2400 Hz 0h = 307.2 kHz 1h = 153.6 kHz 2h = 76.8 kHz 3h = 38.4 kHz 4h = 19.2 kHz 5h = 9600 Hz (default)6h = 4800 Hz 7h = 2400 Hz 8-6 SR_STEP R/W 4h Slew Step Size 0h = 1 code 1h = 2 codes 2h = 4 codes 3h = 8 codes 4h = 16 codes (default) 5h = 32 codes 6h = 64 codes 7h = 128 codes 8-6SR_STEPR/W4hSlew Step Size 0h = 1 code 1h = 2 codes 2h = 4 codes 3h = 8 codes 4h = 16 codes (default) 5h = 32 codes 6h = 64 codes 7h = 128 codes 0h = 1 code 1h = 2 codes 2h = 4 codes 3h = 8 codes 4h = 16 codes (default)5h = 32 codes 6h = 64 codes 7h = 128 codes 5 SR_EN R/W 0h Slew Enable Enables slew on the output voltage. 0h = Disabled (default) 1h = Enabled 5SR_ENR/W0hSlew Enable Enables slew on the output voltage. 0h = Disabled (default) 1h = Enabled Enables slew on the output voltage.0h = Disabled (default)1h = Enabled 4 SR_MODE R/W 0h Slew Mode Output slew rate mode select. 0h = Linear Slew (default) 1h = Sinusoidal Slew 4SR_MODER/W0hSlew Mode Output slew rate mode select. 0h = Linear Slew (default) 1h = Sinusoidal Slew Output slew rate mode select.0h = Linear Slew (default)1h = Sinusoidal Slew 3 RESERVED R 0h 3RESERVEDR0h 2 CLR R/W 0h CLEAR State 0h = Normal operation (default) 1h = Force the DAC to the CLEAR state 2CLRR/W0hCLEAR State 0h = Normal operation (default) 1h = Force the DAC to the CLEAR state 0h = Normal operation (default)1h = Force the DAC to the CLEAR state 1-0 RESERVED R 0h 1-0RESERVEDR0h DAC_GAIN Register (Offset = 4h) [Reset = 8000h] Return to the Register Map . DAC_GAIN Register Field Descriptions Bit Field Type Reset Description 15-0 GAIN R/W 8000h GainSet the gain of the DAC output from 0.5 – 1.499985. For example: 0000h = 0.5 8000h = 1.0 (default) FFFFh = 1.499985 DAC_GAIN Register (Offset = 4h) [Reset = 8000h] DAC_GAINReturn to the Register Map . Register Map Register Map DAC_GAIN Register Field Descriptions Bit Field Type Reset Description 15-0 GAIN R/W 8000h GainSet the gain of the DAC output from 0.5 – 1.499985. For example: 0000h = 0.5 8000h = 1.0 (default) FFFFh = 1.499985 DAC_GAIN Register Field Descriptions Bit Field Type Reset Description 15-0 GAIN R/W 8000h GainSet the gain of the DAC output from 0.5 – 1.499985. For example: 0000h = 0.5 8000h = 1.0 (default) FFFFh = 1.499985 Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 GAIN R/W 8000h GainSet the gain of the DAC output from 0.5 – 1.499985. For example: 0000h = 0.5 8000h = 1.0 (default) FFFFh = 1.499985 15-0 GAIN R/W 8000h GainSet the gain of the DAC output from 0.5 – 1.499985. For example: 0000h = 0.5 8000h = 1.0 (default) FFFFh = 1.499985 15-0GAINR/W8000hGainSet the gain of the DAC output from 0.5 – 1.499985. For example: 0000h = 0.5 8000h = 1.0 (default) FFFFh = 1.499985 0000h = 0.58000h = 1.0 (default)FFFFh = 1.499985 DAC_OFFSET Register (Offset = 5h) [Reset = 0000h] Return to the Register Map . DAC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-0 OFFSET R/W 0h OffsetAdjust the offset of the DAC output, 2's complement number. For example: 0000h = 0 (default) FFFFh = –1 DAC_OFFSET Register (Offset = 5h) [Reset = 0000h] DAC_OFFSETReturn to the Register Map . Register Map Register Map DAC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-0 OFFSET R/W 0h OffsetAdjust the offset of the DAC output, 2's complement number. For example: 0000h = 0 (default) FFFFh = –1 DAC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-0 OFFSET R/W 0h OffsetAdjust the offset of the DAC output, 2's complement number. For example: 0000h = 0 (default) FFFFh = –1 Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 OFFSET R/W 0h OffsetAdjust the offset of the DAC output, 2's complement number. For example: 0000h = 0 (default) FFFFh = –1 15-0 OFFSET R/W 0h OffsetAdjust the offset of the DAC output, 2's complement number. For example: 0000h = 0 (default) FFFFh = –1 15-0OFFSETR/W0hOffsetAdjust the offset of the DAC output, 2's complement number. For example: 0000h = 0 (default) FFFFh = –1 0000h = 0 (default)FFFFh = –1 DAC_CLR_CODE Register (Offset = 6h) [Reset = 0000h] Return to the Register Map . DAC_CLR_CODE Register Field Descriptions Bit Field Type Reset Description 15-0 CODE R/W 0h CLEAR State DAC CodeDAC code applied in the CLEAR state. See . DAC_CLR_CODE Register (Offset = 6h) [Reset = 0000h] DAC_CLR_CODEReturn to the Register Map . Register Map Register Map DAC_CLR_CODE Register Field Descriptions Bit Field Type Reset Description 15-0 CODE R/W 0h CLEAR State DAC CodeDAC code applied in the CLEAR state. See . DAC_CLR_CODE Register Field Descriptions Bit Field Type Reset Description 15-0 CODE R/W 0h CLEAR State DAC CodeDAC code applied in the CLEAR state. See . Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 CODE R/W 0h CLEAR State DAC CodeDAC code applied in the CLEAR state. See . 15-0 CODE R/W 0h CLEAR State DAC CodeDAC code applied in the CLEAR state. See . 15-0CODER/W0hCLEAR State DAC CodeDAC code applied in the CLEAR state. See . RESET Register (Offset = 7h) [Reset = 0000h] Return to the Register Map . RESET Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-0 SW_RST WSC 0h Software Reset Write ADh to initiate software reset. RESET Register (Offset = 7h) [Reset = 0000h] RESETReturn to the Register Map . Register Map Register Map RESET Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-0 SW_RST WSC 0h Software Reset Write ADh to initiate software reset. RESET Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-0 SW_RST WSC 0h Software Reset Write ADh to initiate software reset. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-8 RESERVED R 0h 7-0 SW_RST WSC 0h Software Reset Write ADh to initiate software reset. 15-8 RESERVED R 0h 15-8RESERVEDR0h 7-0 SW_RST WSC 0h Software Reset Write ADh to initiate software reset. 7-0SW_RSTWSC0h Software Reset Write ADh to initiate software reset. Software ResetWrite ADh to initiate software reset. ADC_CFG Register (Offset = 8h) [Reset = 8810h] Return to the Register Map . ADC_CFG Register Field Descriptions Bit Field Type Reset Description 15 BUF_PD R/W 1h ADC Buffer Power-Down 0h = ADC buffer enabled; 1h = ADC buffer powered down (default) 14-8 HYST R/W 8h HysteresisThe number of codes of hysteresis used when a threshold is exceeded for an ADC measurement of AIN0/AIN1/TEMP. 7-5 FLT_CNT R/W 0h Fault Count Number of successive faults to trip an alarm.Number of successive faults is programmed value + 1 (1-8 faults). 4 AIN_RANGE R/W 1h ADC Analog Input Range Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs. 0h = 2 × VREF; 1h = 1 × VREF (default) 3 EOC_PER_CH R/W 0h ADC End-of-Conversion for Every ChannelSends an EOC pulse at the end of each channel instead of at the end of all the channels.0h = EOC after last channel (default); 1h = EOC for every channel 2-1 CONV_RATE R/W 0h ADC Conversion RateThis setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based on a 76.8-kHz ADC clock. All other channels use 2560 Hz. 0h = 3840 Hz (default) 1h = 2560 Hz 2h = 1280 Hz 3h = 640 Hz 0 DIRECT_MODE R/W 0h Direct Mode Enable 0h = Auto mode (default); 1h = Direct mode ADC_CFG Register (Offset = 8h) [Reset = 8810h] ADC_CFGReturn to the Register Map . Register Map Register Map ADC_CFG Register Field Descriptions Bit Field Type Reset Description 15 BUF_PD R/W 1h ADC Buffer Power-Down 0h = ADC buffer enabled; 1h = ADC buffer powered down (default) 14-8 HYST R/W 8h HysteresisThe number of codes of hysteresis used when a threshold is exceeded for an ADC measurement of AIN0/AIN1/TEMP. 7-5 FLT_CNT R/W 0h Fault Count Number of successive faults to trip an alarm.Number of successive faults is programmed value + 1 (1-8 faults). 4 AIN_RANGE R/W 1h ADC Analog Input Range Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs. 0h = 2 × VREF; 1h = 1 × VREF (default) 3 EOC_PER_CH R/W 0h ADC End-of-Conversion for Every ChannelSends an EOC pulse at the end of each channel instead of at the end of all the channels.0h = EOC after last channel (default); 1h = EOC for every channel 2-1 CONV_RATE R/W 0h ADC Conversion RateThis setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based on a 76.8-kHz ADC clock. All other channels use 2560 Hz. 0h = 3840 Hz (default) 1h = 2560 Hz 2h = 1280 Hz 3h = 640 Hz 0 DIRECT_MODE R/W 0h Direct Mode Enable 0h = Auto mode (default); 1h = Direct mode ADC_CFG Register Field Descriptions Bit Field Type Reset Description 15 BUF_PD R/W 1h ADC Buffer Power-Down 0h = ADC buffer enabled; 1h = ADC buffer powered down (default) 14-8 HYST R/W 8h HysteresisThe number of codes of hysteresis used when a threshold is exceeded for an ADC measurement of AIN0/AIN1/TEMP. 7-5 FLT_CNT R/W 0h Fault Count Number of successive faults to trip an alarm.Number of successive faults is programmed value + 1 (1-8 faults). 4 AIN_RANGE R/W 1h ADC Analog Input Range Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs. 0h = 2 × VREF; 1h = 1 × VREF (default) 3 EOC_PER_CH R/W 0h ADC End-of-Conversion for Every ChannelSends an EOC pulse at the end of each channel instead of at the end of all the channels.0h = EOC after last channel (default); 1h = EOC for every channel 2-1 CONV_RATE R/W 0h ADC Conversion RateThis setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based on a 76.8-kHz ADC clock. All other channels use 2560 Hz. 0h = 3840 Hz (default) 1h = 2560 Hz 2h = 1280 Hz 3h = 640 Hz 0 DIRECT_MODE R/W 0h Direct Mode Enable 0h = Auto mode (default); 1h = Direct mode Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15 BUF_PD R/W 1h ADC Buffer Power-Down 0h = ADC buffer enabled; 1h = ADC buffer powered down (default) 14-8 HYST R/W 8h HysteresisThe number of codes of hysteresis used when a threshold is exceeded for an ADC measurement of AIN0/AIN1/TEMP. 7-5 FLT_CNT R/W 0h Fault Count Number of successive faults to trip an alarm.Number of successive faults is programmed value + 1 (1-8 faults). 4 AIN_RANGE R/W 1h ADC Analog Input Range Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs. 0h = 2 × VREF; 1h = 1 × VREF (default) 3 EOC_PER_CH R/W 0h ADC End-of-Conversion for Every ChannelSends an EOC pulse at the end of each channel instead of at the end of all the channels.0h = EOC after last channel (default); 1h = EOC for every channel 2-1 CONV_RATE R/W 0h ADC Conversion RateThis setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based on a 76.8-kHz ADC clock. All other channels use 2560 Hz. 0h = 3840 Hz (default) 1h = 2560 Hz 2h = 1280 Hz 3h = 640 Hz 0 DIRECT_MODE R/W 0h Direct Mode Enable 0h = Auto mode (default); 1h = Direct mode 15 BUF_PD R/W 1h ADC Buffer Power-Down 0h = ADC buffer enabled; 1h = ADC buffer powered down (default) 15BUF_PDR/W1hADC Buffer Power-Down 0h = ADC buffer enabled; 1h = ADC buffer powered down (default) 0h = ADC buffer enabled; 1h = ADC buffer powered down (default) 14-8 HYST R/W 8h HysteresisThe number of codes of hysteresis used when a threshold is exceeded for an ADC measurement of AIN0/AIN1/TEMP. 14-8HYSTR/W8hHysteresisThe number of codes of hysteresis used when a threshold is exceeded for an ADC measurement of AIN0/AIN1/TEMP. 7-5 FLT_CNT R/W 0h Fault Count Number of successive faults to trip an alarm.Number of successive faults is programmed value + 1 (1-8 faults). 7-5FLT_CNTR/W0hFault Count Number of successive faults to trip an alarm.Number of successive faults is programmed value + 1 (1-8 faults). 4 AIN_RANGE R/W 1h ADC Analog Input Range Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs. 0h = 2 × VREF; 1h = 1 × VREF (default) 4AIN_RANGER/W1hADC Analog Input Range Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs. 0h = 2 × VREF; 1h = 1 × VREF (default) Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs.0h = 2 × VREF; 1h = 1 × VREF (default) 3 EOC_PER_CH R/W 0h ADC End-of-Conversion for Every ChannelSends an EOC pulse at the end of each channel instead of at the end of all the channels.0h = EOC after last channel (default); 1h = EOC for every channel 3EOC_PER_CHR/W0hADC End-of-Conversion for Every ChannelSends an EOC pulse at the end of each channel instead of at the end of all the channels.0h = EOC after last channel (default); 1h = EOC for every channel 0h = EOC after last channel (default); 1h = EOC for every channel 2-1 CONV_RATE R/W 0h ADC Conversion RateThis setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based on a 76.8-kHz ADC clock. All other channels use 2560 Hz. 0h = 3840 Hz (default) 1h = 2560 Hz 2h = 1280 Hz 3h = 640 Hz 2-1CONV_RATER/W0hADC Conversion RateThis setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based on a 76.8-kHz ADC clock. All other channels use 2560 Hz. 0h = 3840 Hz (default) 1h = 2560 Hz 2h = 1280 Hz 3h = 640 Hz 0h = 3840 Hz (default)1h = 2560 Hz2h = 1280 Hz3h = 640 Hz 0 DIRECT_MODE R/W 0h Direct Mode Enable 0h = Auto mode (default); 1h = Direct mode 0DIRECT_MODER/W0hDirect Mode Enable 0h = Auto mode (default); 1h = Direct mode 0h = Auto mode (default); 1h = Direct mode ADC_INDEX_CFG Register (Offset = 9h) [Reset = 0080h] Return to the Register Map . The ADC custom channel sequencing configuration is shown in #GUID-121F6531-236F-4BFA-AA11-8CC4C580B655/GUID-84429441-E2D5-4137-992B-F0A3EE3367A1. ADC_INDEX_CFG Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-4 STOP R/W 8h Custom Channel Sequencer Stop IndexCCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START. 0h = OFFSET 1h = AIN0 2h = AIN1 3h = TEMP 4h = SD0 (VREF) 5h = SD1 (PVDD) 6h = SD2 (VDD) 7h = SD3 (ZTAT) 8h = SD4 (VOUT) (default) 9h through Fh = GND 3-0 START R/W 0h Custom Channel Sequencer Start IndexCCS index to start ADC sequence.0h through Fh = Same as STOP field (0h is default) ADC_INDEX_CFG Register (Offset = 9h) [Reset = 0080h] ADC_INDEX_CFGReturn to the Register Map . Register Map Register MapThe ADC custom channel sequencing configuration is shown in #GUID-121F6531-236F-4BFA-AA11-8CC4C580B655/GUID-84429441-E2D5-4137-992B-F0A3EE3367A1.#GUID-121F6531-236F-4BFA-AA11-8CC4C580B655/GUID-84429441-E2D5-4137-992B-F0A3EE3367A1 ADC_INDEX_CFG Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-4 STOP R/W 8h Custom Channel Sequencer Stop IndexCCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START. 0h = OFFSET 1h = AIN0 2h = AIN1 3h = TEMP 4h = SD0 (VREF) 5h = SD1 (PVDD) 6h = SD2 (VDD) 7h = SD3 (ZTAT) 8h = SD4 (VOUT) (default) 9h through Fh = GND 3-0 START R/W 0h Custom Channel Sequencer Start IndexCCS index to start ADC sequence.0h through Fh = Same as STOP field (0h is default) ADC_INDEX_CFG Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-4 STOP R/W 8h Custom Channel Sequencer Stop IndexCCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START. 0h = OFFSET 1h = AIN0 2h = AIN1 3h = TEMP 4h = SD0 (VREF) 5h = SD1 (PVDD) 6h = SD2 (VDD) 7h = SD3 (ZTAT) 8h = SD4 (VOUT) (default) 9h through Fh = GND 3-0 START R/W 0h Custom Channel Sequencer Start IndexCCS index to start ADC sequence.0h through Fh = Same as STOP field (0h is default) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-8 RESERVED R 0h 7-4 STOP R/W 8h Custom Channel Sequencer Stop IndexCCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START. 0h = OFFSET 1h = AIN0 2h = AIN1 3h = TEMP 4h = SD0 (VREF) 5h = SD1 (PVDD) 6h = SD2 (VDD) 7h = SD3 (ZTAT) 8h = SD4 (VOUT) (default) 9h through Fh = GND 3-0 START R/W 0h Custom Channel Sequencer Start IndexCCS index to start ADC sequence.0h through Fh = Same as STOP field (0h is default) 15-8 RESERVED R 0h 15-8RESERVEDR0h 7-4 STOP R/W 8h Custom Channel Sequencer Stop IndexCCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START. 0h = OFFSET 1h = AIN0 2h = AIN1 3h = TEMP 4h = SD0 (VREF) 5h = SD1 (PVDD) 6h = SD2 (VDD) 7h = SD3 (ZTAT) 8h = SD4 (VOUT) (default) 9h through Fh = GND 7-4STOPR/W8hCustom Channel Sequencer Stop IndexCCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START. 0h = OFFSET 1h = AIN0 2h = AIN1 3h = TEMP 4h = SD0 (VREF) 5h = SD1 (PVDD) 6h = SD2 (VDD) 7h = SD3 (ZTAT) 8h = SD4 (VOUT) (default) 9h through Fh = GND 0h = OFFSET1h = AIN02h = AIN13h = TEMP4h = SD0 (VREF)5h = SD1 (PVDD)6h = SD2 (VDD)7h = SD3 (ZTAT)8h = SD4 (VOUT) (default)9h through Fh = GND 3-0 START R/W 0h Custom Channel Sequencer Start IndexCCS index to start ADC sequence.0h through Fh = Same as STOP field (0h is default) 3-0STARTR/W0hCustom Channel Sequencer Start IndexCCS index to start ADC sequence.0h through Fh = Same as STOP field (0h is default) 0h through Fh = Same as STOP field (0h is default) TRIGGER Register (Offset = Ah) [Reset = 0000h] Return to the Register Map . TRIGGER Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED R 0h 3 RBIST WSC 0h RBIST Trigger This trigger initiates a Register BIST. This BIST runs a CRC calculation through the configuration registers () and compares the result to a stored CRC value in the RBIST_CRC register. 2 MBIST WSC 0h Memory Built-In Self-Test Trigger This trigger initiates an MBIST on the SRAM that is used for the FIFO. During this time communication to/from HART does not work as MBIST takes over the control of the SRAM. 1 SHADOWLOAD WSC 0h Shadow Load TriggerThis trigger initiates the loading of the OTP array into the parallel latches. If an OTP CRC error is detected, assert this trigger to try and reload the OTP into the memory locations. 0 ADC WSC 0h ADC TriggerIn auto mode, this bit enables or disables the conversions. Manually set to 1 (enable) or 0 (disable). In direct mode, set this bit to start a conversion sequence. The bit is cleared at the end of the sequence. To stop a sequence prematurely, manually clear this bit. TRIGGER Register (Offset = Ah) [Reset = 0000h] TRIGGERReturn to the Register Map . Register Map Register Map TRIGGER Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED R 0h 3 RBIST WSC 0h RBIST Trigger This trigger initiates a Register BIST. This BIST runs a CRC calculation through the configuration registers () and compares the result to a stored CRC value in the RBIST_CRC register. 2 MBIST WSC 0h Memory Built-In Self-Test Trigger This trigger initiates an MBIST on the SRAM that is used for the FIFO. During this time communication to/from HART does not work as MBIST takes over the control of the SRAM. 1 SHADOWLOAD WSC 0h Shadow Load TriggerThis trigger initiates the loading of the OTP array into the parallel latches. If an OTP CRC error is detected, assert this trigger to try and reload the OTP into the memory locations. 0 ADC WSC 0h ADC TriggerIn auto mode, this bit enables or disables the conversions. Manually set to 1 (enable) or 0 (disable). In direct mode, set this bit to start a conversion sequence. The bit is cleared at the end of the sequence. To stop a sequence prematurely, manually clear this bit. TRIGGER Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED R 0h 3 RBIST WSC 0h RBIST Trigger This trigger initiates a Register BIST. This BIST runs a CRC calculation through the configuration registers () and compares the result to a stored CRC value in the RBIST_CRC register. 2 MBIST WSC 0h Memory Built-In Self-Test Trigger This trigger initiates an MBIST on the SRAM that is used for the FIFO. During this time communication to/from HART does not work as MBIST takes over the control of the SRAM. 1 SHADOWLOAD WSC 0h Shadow Load TriggerThis trigger initiates the loading of the OTP array into the parallel latches. If an OTP CRC error is detected, assert this trigger to try and reload the OTP into the memory locations. 0 ADC WSC 0h ADC TriggerIn auto mode, this bit enables or disables the conversions. Manually set to 1 (enable) or 0 (disable). In direct mode, set this bit to start a conversion sequence. The bit is cleared at the end of the sequence. To stop a sequence prematurely, manually clear this bit. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-4 RESERVED R 0h 3 RBIST WSC 0h RBIST Trigger This trigger initiates a Register BIST. This BIST runs a CRC calculation through the configuration registers () and compares the result to a stored CRC value in the RBIST_CRC register. 2 MBIST WSC 0h Memory Built-In Self-Test Trigger This trigger initiates an MBIST on the SRAM that is used for the FIFO. During this time communication to/from HART does not work as MBIST takes over the control of the SRAM. 1 SHADOWLOAD WSC 0h Shadow Load TriggerThis trigger initiates the loading of the OTP array into the parallel latches. If an OTP CRC error is detected, assert this trigger to try and reload the OTP into the memory locations. 0 ADC WSC 0h ADC TriggerIn auto mode, this bit enables or disables the conversions. Manually set to 1 (enable) or 0 (disable). In direct mode, set this bit to start a conversion sequence. The bit is cleared at the end of the sequence. To stop a sequence prematurely, manually clear this bit. 15-4 RESERVED R 0h 15-4RESERVEDR0h 3 RBIST WSC 0h RBIST Trigger This trigger initiates a Register BIST. This BIST runs a CRC calculation through the configuration registers () and compares the result to a stored CRC value in the RBIST_CRC register. 3RBISTWSC0hRBIST Trigger This trigger initiates a Register BIST. This BIST runs a CRC calculation through the configuration registers () and compares the result to a stored CRC value in the RBIST_CRC register. This trigger initiates a Register BIST. This BIST runs a CRC calculation through the configuration registers () and compares the result to a stored CRC value in the RBIST_CRC register. 2 MBIST WSC 0h Memory Built-In Self-Test Trigger This trigger initiates an MBIST on the SRAM that is used for the FIFO. During this time communication to/from HART does not work as MBIST takes over the control of the SRAM. 2MBISTWSC0hMemory Built-In Self-Test Trigger This trigger initiates an MBIST on the SRAM that is used for the FIFO. During this time communication to/from HART does not work as MBIST takes over the control of the SRAM. This trigger initiates an MBIST on the SRAM that is used for the FIFO. During this time communication to/from HART does not work as MBIST takes over the control of the SRAM. 1 SHADOWLOAD WSC 0h Shadow Load TriggerThis trigger initiates the loading of the OTP array into the parallel latches. If an OTP CRC error is detected, assert this trigger to try and reload the OTP into the memory locations. 1SHADOWLOADWSC0hShadow Load TriggerThis trigger initiates the loading of the OTP array into the parallel latches. If an OTP CRC error is detected, assert this trigger to try and reload the OTP into the memory locations. 0 ADC WSC 0h ADC TriggerIn auto mode, this bit enables or disables the conversions. Manually set to 1 (enable) or 0 (disable). In direct mode, set this bit to start a conversion sequence. The bit is cleared at the end of the sequence. To stop a sequence prematurely, manually clear this bit. 0ADCWSC0hADC TriggerIn auto mode, this bit enables or disables the conversions. Manually set to 1 (enable) or 0 (disable). In direct mode, set this bit to start a conversion sequence. The bit is cleared at the end of the sequence. To stop a sequence prematurely, manually clear this bit. SPECIAL_CFG Register (Offset = Bh) [Reset = 0000h] Return to the Register Map . SPECIAL_CFG Register Field Descriptions Bit Field Type Reset Description 15-3 RESERVED R 0h 2 OTP_LOAD_SW_RST R/W 0h OTP (One Time Programmable Factory Trimmed Registers) LOAD with SW RESETOTP reloads with the assertion of a software reset (SW_RST). 0h = No reload with SW_RST 1h = Reload with SW_RST 1 ALMV_POL R/W 0h Alarm Voltage PolarityThis register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB bit is low) to control the VOUT during a hardware reset condition or if alarm is active and alarm action is set appropriately. The following Boolean function is implemented for the internal signal ALMV_POL_o that sets the VOUT voltage:ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT AIN1_ENB) 0h = Low (0 V) 1h = High (2.5 V) 0 AIN1_ENB R/W 0h AIN1 Pin EnableThis bit determines whether the POL_SEL/AIN1 pin acts as alarm voltage polarity control bit or an input channel to the ADC. 0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts GND 1h = AIN1 pin is an active channel to the ADC SPECIAL_CFG Register (Offset = Bh) [Reset = 0000h] SPECIAL_CFGReturn to the Register Map . Register Map Register Map SPECIAL_CFG Register Field Descriptions Bit Field Type Reset Description 15-3 RESERVED R 0h 2 OTP_LOAD_SW_RST R/W 0h OTP (One Time Programmable Factory Trimmed Registers) LOAD with SW RESETOTP reloads with the assertion of a software reset (SW_RST). 0h = No reload with SW_RST 1h = Reload with SW_RST 1 ALMV_POL R/W 0h Alarm Voltage PolarityThis register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB bit is low) to control the VOUT during a hardware reset condition or if alarm is active and alarm action is set appropriately. The following Boolean function is implemented for the internal signal ALMV_POL_o that sets the VOUT voltage:ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT AIN1_ENB) 0h = Low (0 V) 1h = High (2.5 V) 0 AIN1_ENB R/W 0h AIN1 Pin EnableThis bit determines whether the POL_SEL/AIN1 pin acts as alarm voltage polarity control bit or an input channel to the ADC. 0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts GND 1h = AIN1 pin is an active channel to the ADC SPECIAL_CFG Register Field Descriptions Bit Field Type Reset Description 15-3 RESERVED R 0h 2 OTP_LOAD_SW_RST R/W 0h OTP (One Time Programmable Factory Trimmed Registers) LOAD with SW RESETOTP reloads with the assertion of a software reset (SW_RST). 0h = No reload with SW_RST 1h = Reload with SW_RST 1 ALMV_POL R/W 0h Alarm Voltage PolarityThis register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB bit is low) to control the VOUT during a hardware reset condition or if alarm is active and alarm action is set appropriately. The following Boolean function is implemented for the internal signal ALMV_POL_o that sets the VOUT voltage:ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT AIN1_ENB) 0h = Low (0 V) 1h = High (2.5 V) 0 AIN1_ENB R/W 0h AIN1 Pin EnableThis bit determines whether the POL_SEL/AIN1 pin acts as alarm voltage polarity control bit or an input channel to the ADC. 0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts GND 1h = AIN1 pin is an active channel to the ADC Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-3 RESERVED R 0h 2 OTP_LOAD_SW_RST R/W 0h OTP (One Time Programmable Factory Trimmed Registers) LOAD with SW RESETOTP reloads with the assertion of a software reset (SW_RST). 0h = No reload with SW_RST 1h = Reload with SW_RST 1 ALMV_POL R/W 0h Alarm Voltage PolarityThis register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB bit is low) to control the VOUT during a hardware reset condition or if alarm is active and alarm action is set appropriately. The following Boolean function is implemented for the internal signal ALMV_POL_o that sets the VOUT voltage:ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT AIN1_ENB) 0h = Low (0 V) 1h = High (2.5 V) 0 AIN1_ENB R/W 0h AIN1 Pin EnableThis bit determines whether the POL_SEL/AIN1 pin acts as alarm voltage polarity control bit or an input channel to the ADC. 0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts GND 1h = AIN1 pin is an active channel to the ADC 15-3 RESERVED R 0h 15-3RESERVEDR0h 2 OTP_LOAD_SW_RST R/W 0h OTP (One Time Programmable Factory Trimmed Registers) LOAD with SW RESETOTP reloads with the assertion of a software reset (SW_RST). 0h = No reload with SW_RST 1h = Reload with SW_RST 2OTP_LOAD_SW_RSTR/W0hOTP (One Time Programmable Factory Trimmed Registers) LOAD with SW RESETOTP reloads with the assertion of a software reset (SW_RST). 0h = No reload with SW_RST 1h = Reload with SW_RST 0h = No reload with SW_RST1h = Reload with SW_RST 1 ALMV_POL R/W 0h Alarm Voltage PolarityThis register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB bit is low) to control the VOUT during a hardware reset condition or if alarm is active and alarm action is set appropriately. The following Boolean function is implemented for the internal signal ALMV_POL_o that sets the VOUT voltage:ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT AIN1_ENB) 0h = Low (0 V) 1h = High (2.5 V) 1ALMV_POLR/W0hAlarm Voltage PolarityThis register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB bit is low) to control the VOUT during a hardware reset condition or if alarm is active and alarm action is set appropriately. The following Boolean function is implemented for the internal signal ALMV_POL_o that sets the VOUT voltage:ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT AIN1_ENB) 0h = Low (0 V) 1h = High (2.5 V) ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT AIN1_ENB)0h = Low (0 V)1h = High (2.5 V) 0 AIN1_ENB R/W 0h AIN1 Pin EnableThis bit determines whether the POL_SEL/AIN1 pin acts as alarm voltage polarity control bit or an input channel to the ADC. 0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts GND 1h = AIN1 pin is an active channel to the ADC 0AIN1_ENBR/W0hAIN1 Pin EnableThis bit determines whether the POL_SEL/AIN1 pin acts as alarm voltage polarity control bit or an input channel to the ADC. 0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts GND 1h = AIN1 pin is an active channel to the ADC 0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts GND 1h = AIN1 pin is an active channel to the ADC MODEM_CFG Register (Offset = Eh) [Reset = 0040h] Return to the Register Map . MODEM_CFG Register Field Descriptions Bit Field Type Reset Description 15 Tx2200Hz R/W 0h Transmit 2200 Hz OnlyBy not sending data to the FIFO buffer and asserting RTS, the user can transmit multiples of 1200 Hz as long as RTS is asserted. By setting this bit the user can transmit multiples of 2200 Hz. Setting this bit prevents data in the FIFO buffer from being correctly transmitted. If using this bit there is no need to use the FIFO buffer. 0h = Transmit 1200 Hz and 2200 Hz (default) 1h = Transmit only 2200 Hz 14-13 RESERVED R 0h 12 DUPLEX_EXT R/W 0h Duplex External ModeAllows full duplex mode but expects the connection of MOD_OUT to RX_IN to be made externally. 0h = Internal duplex connection (default) 1h = External duplex connection 11 RX_HORD_EN R/W 0h High Order Filter EnableEnables a higher order filter on HART_RX. 0h = Disable (default); 1h = Enable 10 RX_EXTFILT_EN R/W 0h External Filter EnableEnables the use of an external filter for HART_RX. If enabled, then connect the HART signal to RX_INF. 0h = Use internal filter (default); 1h = Use external filter 9 TxRES R/W 0h HART Transmit Resolution0h = 32 steps per period (default) at 38.4 kHz update rate for 1200 baud 1h = 128 steps per period at 153.6 kHz update rate for 1200 baud 128-step per period waveform consumes more power. 8-4 TxAMP R/W 4h Transmit AmplitudeHART Tx amplitude. 00h = 400 mVPP; 01h = 425 mVPP 02h = 450 mVPP; 03h = 475 mVPP 04h = 500 mVPP (default); 05h = 525 mVPP 06h = 550 mVPP; 07h = 575 mVPP 08h = 600 mVPP; 09h = 625 mVPP 0Ah = 650 mVPP; 0Bh = 675 mVPP 0Ch = 700 mVPP; 0Dh = 725 mVPP 0Eh = 750 mVPP; 0Fh = 775 mVPP 10h through 1Fh = 800 mVPP 3 HART_EN R/W 0h HART EnableEnable the HART Tx and Rx.0h = Disable (default); 1h = Enable 2 DUPLEX R/W 0h Duplex ModeEnable internal connection of Tx to Rx for debug and testing.0h = Normal operation (default); 1h = Duplex enabled 1 TxHPD R/W 0h HART Tx DAC Output Buffer Hi-Z in Rx Mode or When Disabled0h = HART Tx DAC output is set to midcode with 50 kΩ output impedance (default) 1h = HART Tx DAC is Hi-Z in Rx mode or when disabled. Users can set the default voltage level with an external circuit. 0 RTS R/W 0h Request To Send Starts transmitting a carrier on MOD_OUT pin.0h = No action (default) 1h = Request to send. Device starts modulating the MOD_OUT pin if CD = 0. MODEM_CFG Register (Offset = Eh) [Reset = 0040h] MODEM_CFGReturn to the Register Map . Register Map Register Map MODEM_CFG Register Field Descriptions Bit Field Type Reset Description 15 Tx2200Hz R/W 0h Transmit 2200 Hz OnlyBy not sending data to the FIFO buffer and asserting RTS, the user can transmit multiples of 1200 Hz as long as RTS is asserted. By setting this bit the user can transmit multiples of 2200 Hz. Setting this bit prevents data in the FIFO buffer from being correctly transmitted. If using this bit there is no need to use the FIFO buffer. 0h = Transmit 1200 Hz and 2200 Hz (default) 1h = Transmit only 2200 Hz 14-13 RESERVED R 0h 12 DUPLEX_EXT R/W 0h Duplex External ModeAllows full duplex mode but expects the connection of MOD_OUT to RX_IN to be made externally. 0h = Internal duplex connection (default) 1h = External duplex connection 11 RX_HORD_EN R/W 0h High Order Filter EnableEnables a higher order filter on HART_RX. 0h = Disable (default); 1h = Enable 10 RX_EXTFILT_EN R/W 0h External Filter EnableEnables the use of an external filter for HART_RX. If enabled, then connect the HART signal to RX_INF. 0h = Use internal filter (default); 1h = Use external filter 9 TxRES R/W 0h HART Transmit Resolution0h = 32 steps per period (default) at 38.4 kHz update rate for 1200 baud 1h = 128 steps per period at 153.6 kHz update rate for 1200 baud 128-step per period waveform consumes more power. 8-4 TxAMP R/W 4h Transmit AmplitudeHART Tx amplitude. 00h = 400 mVPP; 01h = 425 mVPP 02h = 450 mVPP; 03h = 475 mVPP 04h = 500 mVPP (default); 05h = 525 mVPP 06h = 550 mVPP; 07h = 575 mVPP 08h = 600 mVPP; 09h = 625 mVPP 0Ah = 650 mVPP; 0Bh = 675 mVPP 0Ch = 700 mVPP; 0Dh = 725 mVPP 0Eh = 750 mVPP; 0Fh = 775 mVPP 10h through 1Fh = 800 mVPP 3 HART_EN R/W 0h HART EnableEnable the HART Tx and Rx.0h = Disable (default); 1h = Enable 2 DUPLEX R/W 0h Duplex ModeEnable internal connection of Tx to Rx for debug and testing.0h = Normal operation (default); 1h = Duplex enabled 1 TxHPD R/W 0h HART Tx DAC Output Buffer Hi-Z in Rx Mode or When Disabled0h = HART Tx DAC output is set to midcode with 50 kΩ output impedance (default) 1h = HART Tx DAC is Hi-Z in Rx mode or when disabled. Users can set the default voltage level with an external circuit. 0 RTS R/W 0h Request To Send Starts transmitting a carrier on MOD_OUT pin.0h = No action (default) 1h = Request to send. Device starts modulating the MOD_OUT pin if CD = 0. MODEM_CFG Register Field Descriptions Bit Field Type Reset Description 15 Tx2200Hz R/W 0h Transmit 2200 Hz OnlyBy not sending data to the FIFO buffer and asserting RTS, the user can transmit multiples of 1200 Hz as long as RTS is asserted. By setting this bit the user can transmit multiples of 2200 Hz. Setting this bit prevents data in the FIFO buffer from being correctly transmitted. If using this bit there is no need to use the FIFO buffer. 0h = Transmit 1200 Hz and 2200 Hz (default) 1h = Transmit only 2200 Hz 14-13 RESERVED R 0h 12 DUPLEX_EXT R/W 0h Duplex External ModeAllows full duplex mode but expects the connection of MOD_OUT to RX_IN to be made externally. 0h = Internal duplex connection (default) 1h = External duplex connection 11 RX_HORD_EN R/W 0h High Order Filter EnableEnables a higher order filter on HART_RX. 0h = Disable (default); 1h = Enable 10 RX_EXTFILT_EN R/W 0h External Filter EnableEnables the use of an external filter for HART_RX. If enabled, then connect the HART signal to RX_INF. 0h = Use internal filter (default); 1h = Use external filter 9 TxRES R/W 0h HART Transmit Resolution0h = 32 steps per period (default) at 38.4 kHz update rate for 1200 baud 1h = 128 steps per period at 153.6 kHz update rate for 1200 baud 128-step per period waveform consumes more power. 8-4 TxAMP R/W 4h Transmit AmplitudeHART Tx amplitude. 00h = 400 mVPP; 01h = 425 mVPP 02h = 450 mVPP; 03h = 475 mVPP 04h = 500 mVPP (default); 05h = 525 mVPP 06h = 550 mVPP; 07h = 575 mVPP 08h = 600 mVPP; 09h = 625 mVPP 0Ah = 650 mVPP; 0Bh = 675 mVPP 0Ch = 700 mVPP; 0Dh = 725 mVPP 0Eh = 750 mVPP; 0Fh = 775 mVPP 10h through 1Fh = 800 mVPP 3 HART_EN R/W 0h HART EnableEnable the HART Tx and Rx.0h = Disable (default); 1h = Enable 2 DUPLEX R/W 0h Duplex ModeEnable internal connection of Tx to Rx for debug and testing.0h = Normal operation (default); 1h = Duplex enabled 1 TxHPD R/W 0h HART Tx DAC Output Buffer Hi-Z in Rx Mode or When Disabled0h = HART Tx DAC output is set to midcode with 50 kΩ output impedance (default) 1h = HART Tx DAC is Hi-Z in Rx mode or when disabled. Users can set the default voltage level with an external circuit. 0 RTS R/W 0h Request To Send Starts transmitting a carrier on MOD_OUT pin.0h = No action (default) 1h = Request to send. Device starts modulating the MOD_OUT pin if CD = 0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15 Tx2200Hz R/W 0h Transmit 2200 Hz OnlyBy not sending data to the FIFO buffer and asserting RTS, the user can transmit multiples of 1200 Hz as long as RTS is asserted. By setting this bit the user can transmit multiples of 2200 Hz. Setting this bit prevents data in the FIFO buffer from being correctly transmitted. If using this bit there is no need to use the FIFO buffer. 0h = Transmit 1200 Hz and 2200 Hz (default) 1h = Transmit only 2200 Hz 14-13 RESERVED R 0h 12 DUPLEX_EXT R/W 0h Duplex External ModeAllows full duplex mode but expects the connection of MOD_OUT to RX_IN to be made externally. 0h = Internal duplex connection (default) 1h = External duplex connection 11 RX_HORD_EN R/W 0h High Order Filter EnableEnables a higher order filter on HART_RX. 0h = Disable (default); 1h = Enable 10 RX_EXTFILT_EN R/W 0h External Filter EnableEnables the use of an external filter for HART_RX. If enabled, then connect the HART signal to RX_INF. 0h = Use internal filter (default); 1h = Use external filter 9 TxRES R/W 0h HART Transmit Resolution0h = 32 steps per period (default) at 38.4 kHz update rate for 1200 baud 1h = 128 steps per period at 153.6 kHz update rate for 1200 baud 128-step per period waveform consumes more power. 8-4 TxAMP R/W 4h Transmit AmplitudeHART Tx amplitude. 00h = 400 mVPP; 01h = 425 mVPP 02h = 450 mVPP; 03h = 475 mVPP 04h = 500 mVPP (default); 05h = 525 mVPP 06h = 550 mVPP; 07h = 575 mVPP 08h = 600 mVPP; 09h = 625 mVPP 0Ah = 650 mVPP; 0Bh = 675 mVPP 0Ch = 700 mVPP; 0Dh = 725 mVPP 0Eh = 750 mVPP; 0Fh = 775 mVPP 10h through 1Fh = 800 mVPP 3 HART_EN R/W 0h HART EnableEnable the HART Tx and Rx.0h = Disable (default); 1h = Enable 2 DUPLEX R/W 0h Duplex ModeEnable internal connection of Tx to Rx for debug and testing.0h = Normal operation (default); 1h = Duplex enabled 1 TxHPD R/W 0h HART Tx DAC Output Buffer Hi-Z in Rx Mode or When Disabled0h = HART Tx DAC output is set to midcode with 50 kΩ output impedance (default) 1h = HART Tx DAC is Hi-Z in Rx mode or when disabled. Users can set the default voltage level with an external circuit. 0 RTS R/W 0h Request To Send Starts transmitting a carrier on MOD_OUT pin.0h = No action (default) 1h = Request to send. Device starts modulating the MOD_OUT pin if CD = 0. 15 Tx2200Hz R/W 0h Transmit 2200 Hz OnlyBy not sending data to the FIFO buffer and asserting RTS, the user can transmit multiples of 1200 Hz as long as RTS is asserted. By setting this bit the user can transmit multiples of 2200 Hz. Setting this bit prevents data in the FIFO buffer from being correctly transmitted. If using this bit there is no need to use the FIFO buffer. 0h = Transmit 1200 Hz and 2200 Hz (default) 1h = Transmit only 2200 Hz 15Tx2200HzR/W0hTransmit 2200 Hz OnlyBy not sending data to the FIFO buffer and asserting RTS, the user can transmit multiples of 1200 Hz as long as RTS is asserted. By setting this bit the user can transmit multiples of 2200 Hz. Setting this bit prevents data in the FIFO buffer from being correctly transmitted. If using this bit there is no need to use the FIFO buffer. 0h = Transmit 1200 Hz and 2200 Hz (default) 1h = Transmit only 2200 Hz 0h = Transmit 1200 Hz and 2200 Hz (default)1h = Transmit only 2200 Hz 14-13 RESERVED R 0h 14-13RESERVEDR0h 12 DUPLEX_EXT R/W 0h Duplex External ModeAllows full duplex mode but expects the connection of MOD_OUT to RX_IN to be made externally. 0h = Internal duplex connection (default) 1h = External duplex connection 12DUPLEX_EXTR/W0hDuplex External ModeAllows full duplex mode but expects the connection of MOD_OUT to RX_IN to be made externally. 0h = Internal duplex connection (default) 1h = External duplex connection 0h = Internal duplex connection (default)1h = External duplex connection 11 RX_HORD_EN R/W 0h High Order Filter EnableEnables a higher order filter on HART_RX. 0h = Disable (default); 1h = Enable 11RX_HORD_ENR/W0hHigh Order Filter EnableEnables a higher order filter on HART_RX. 0h = Disable (default); 1h = Enable 0h = Disable (default); 1h = Enable 10 RX_EXTFILT_EN R/W 0h External Filter EnableEnables the use of an external filter for HART_RX. If enabled, then connect the HART signal to RX_INF. 0h = Use internal filter (default); 1h = Use external filter 10RX_EXTFILT_ENR/W0hExternal Filter EnableEnables the use of an external filter for HART_RX. If enabled, then connect the HART signal to RX_INF. 0h = Use internal filter (default); 1h = Use external filter 0h = Use internal filter (default); 1h = Use external filter 9 TxRES R/W 0h HART Transmit Resolution0h = 32 steps per period (default) at 38.4 kHz update rate for 1200 baud 1h = 128 steps per period at 153.6 kHz update rate for 1200 baud 128-step per period waveform consumes more power. 9TxRESR/W0hHART Transmit Resolution0h = 32 steps per period (default) at 38.4 kHz update rate for 1200 baud 1h = 128 steps per period at 153.6 kHz update rate for 1200 baud 128-step per period waveform consumes more power. 0h = 32 steps per period (default) at 38.4 kHz update rate for 1200 baud1h = 128 steps per period at 153.6 kHz update rate for 1200 baud128-step per period waveform consumes more power. 8-4 TxAMP R/W 4h Transmit AmplitudeHART Tx amplitude. 00h = 400 mVPP; 01h = 425 mVPP 02h = 450 mVPP; 03h = 475 mVPP 04h = 500 mVPP (default); 05h = 525 mVPP 06h = 550 mVPP; 07h = 575 mVPP 08h = 600 mVPP; 09h = 625 mVPP 0Ah = 650 mVPP; 0Bh = 675 mVPP 0Ch = 700 mVPP; 0Dh = 725 mVPP 0Eh = 750 mVPP; 0Fh = 775 mVPP 10h through 1Fh = 800 mVPP 8-4TxAMPR/W4hTransmit AmplitudeHART Tx amplitude. 00h = 400 mVPP; 01h = 425 mVPP 02h = 450 mVPP; 03h = 475 mVPP 04h = 500 mVPP (default); 05h = 525 mVPP 06h = 550 mVPP; 07h = 575 mVPP 08h = 600 mVPP; 09h = 625 mVPP 0Ah = 650 mVPP; 0Bh = 675 mVPP 0Ch = 700 mVPP; 0Dh = 725 mVPP 0Eh = 750 mVPP; 0Fh = 775 mVPP 10h through 1Fh = 800 mVPP 00h = 400 mVPP; 01h = 425 mVPP PPPP02h = 450 mVPP; 03h = 475 mVPP PPPP04h = 500 mVPP (default); 05h = 525 mVPP PPPP06h = 550 mVPP; 07h = 575 mVPP PPPP08h = 600 mVPP; 09h = 625 mVPP PPPP0Ah = 650 mVPP; 0Bh = 675 mVPP PPPP0Ch = 700 mVPP; 0Dh = 725 mVPP PPPP0Eh = 750 mVPP; 0Fh = 775 mVPP PPPP10h through 1Fh = 800 mVPP PP 3 HART_EN R/W 0h HART EnableEnable the HART Tx and Rx.0h = Disable (default); 1h = Enable 3HART_ENR/W0hHART EnableEnable the HART Tx and Rx.0h = Disable (default); 1h = Enable 0h = Disable (default); 1h = Enable 2 DUPLEX R/W 0h Duplex ModeEnable internal connection of Tx to Rx for debug and testing.0h = Normal operation (default); 1h = Duplex enabled 2DUPLEXR/W0hDuplex ModeEnable internal connection of Tx to Rx for debug and testing.0h = Normal operation (default); 1h = Duplex enabled 0h = Normal operation (default); 1h = Duplex enabled 1 TxHPD R/W 0h HART Tx DAC Output Buffer Hi-Z in Rx Mode or When Disabled0h = HART Tx DAC output is set to midcode with 50 kΩ output impedance (default) 1h = HART Tx DAC is Hi-Z in Rx mode or when disabled. Users can set the default voltage level with an external circuit. 1TxHPDR/W0hHART Tx DAC Output Buffer Hi-Z in Rx Mode or When Disabled0h = HART Tx DAC output is set to midcode with 50 kΩ output impedance (default) 1h = HART Tx DAC is Hi-Z in Rx mode or when disabled. Users can set the default voltage level with an external circuit. 0h = HART Tx DAC output is set to midcode with 50 kΩ output impedance (default)1h = HART Tx DAC is Hi-Z in Rx mode or when disabled. Users can set the default voltage level with an external circuit. 0 RTS R/W 0h Request To Send Starts transmitting a carrier on MOD_OUT pin.0h = No action (default) 1h = Request to send. Device starts modulating the MOD_OUT pin if CD = 0. 0RTSR/W0hRequest To Send Starts transmitting a carrier on MOD_OUT pin.0h = No action (default) 1h = Request to send. Device starts modulating the MOD_OUT pin if CD = 0. 0h = No action (default)1h = Request to send. Device starts modulating the MOD_OUT pin if CD = 0. FIFO_CFG Register (Offset = Fh) [Reset = 00F0h] Return to the Register Map . FIFO_CFG Register Field Descriptions Bit Field Type Reset Description 15-10 RESERVED R 0h 9 FIFO_H2U_FLUSH WSC 0h Flush HART-to-µC FIFO (FIFO_H2U) Clear the pointers for the FIFO_H2U. 8 FIFO_U2H_FLUSH WSC 0h Flush µC-to-HART FIFO (FIFO_U2H) Clear the pointers for the FIFO_U2H. 7-4 H2U_LEVEL_SET R/W Fh FIFO_H2U FIFO Level Flag Trip SetSets the level for FIFO_H2U at which the Level Flag trips. This is a (>) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. 3-0 U2H_LEVEL_SET R/W 0h FIFO_U2H FIFO Level Flag Trip SetSets the level for FIFO_U2H at which the Level Flag trips. This is a (<) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. FIFO_CFG Register (Offset = Fh) [Reset = 00F0h] FIFO_CFGReturn to the Register Map . Register Map Register Map FIFO_CFG Register Field Descriptions Bit Field Type Reset Description 15-10 RESERVED R 0h 9 FIFO_H2U_FLUSH WSC 0h Flush HART-to-µC FIFO (FIFO_H2U) Clear the pointers for the FIFO_H2U. 8 FIFO_U2H_FLUSH WSC 0h Flush µC-to-HART FIFO (FIFO_U2H) Clear the pointers for the FIFO_U2H. 7-4 H2U_LEVEL_SET R/W Fh FIFO_H2U FIFO Level Flag Trip SetSets the level for FIFO_H2U at which the Level Flag trips. This is a (>) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. 3-0 U2H_LEVEL_SET R/W 0h FIFO_U2H FIFO Level Flag Trip SetSets the level for FIFO_U2H at which the Level Flag trips. This is a (<) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. FIFO_CFG Register Field Descriptions Bit Field Type Reset Description 15-10 RESERVED R 0h 9 FIFO_H2U_FLUSH WSC 0h Flush HART-to-µC FIFO (FIFO_H2U) Clear the pointers for the FIFO_H2U. 8 FIFO_U2H_FLUSH WSC 0h Flush µC-to-HART FIFO (FIFO_U2H) Clear the pointers for the FIFO_U2H. 7-4 H2U_LEVEL_SET R/W Fh FIFO_H2U FIFO Level Flag Trip SetSets the level for FIFO_H2U at which the Level Flag trips. This is a (>) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. 3-0 U2H_LEVEL_SET R/W 0h FIFO_U2H FIFO Level Flag Trip SetSets the level for FIFO_U2H at which the Level Flag trips. This is a (<) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-10 RESERVED R 0h 9 FIFO_H2U_FLUSH WSC 0h Flush HART-to-µC FIFO (FIFO_H2U) Clear the pointers for the FIFO_H2U. 8 FIFO_U2H_FLUSH WSC 0h Flush µC-to-HART FIFO (FIFO_U2H) Clear the pointers for the FIFO_U2H. 7-4 H2U_LEVEL_SET R/W Fh FIFO_H2U FIFO Level Flag Trip SetSets the level for FIFO_H2U at which the Level Flag trips. This is a (>) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. 3-0 U2H_LEVEL_SET R/W 0h FIFO_U2H FIFO Level Flag Trip SetSets the level for FIFO_U2H at which the Level Flag trips. This is a (<) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. 15-10 RESERVED R 0h 15-10RESERVEDR0h 9 FIFO_H2U_FLUSH WSC 0h Flush HART-to-µC FIFO (FIFO_H2U) Clear the pointers for the FIFO_H2U. 9FIFO_H2U_FLUSHWSC0hFlush HART-to-µC FIFO (FIFO_H2U) Clear the pointers for the FIFO_H2U. Clear the pointers for the FIFO_H2U. 8 FIFO_U2H_FLUSH WSC 0h Flush µC-to-HART FIFO (FIFO_U2H) Clear the pointers for the FIFO_U2H. 8FIFO_U2H_FLUSHWSC0hFlush µC-to-HART FIFO (FIFO_U2H) Clear the pointers for the FIFO_U2H. Clear the pointers for the FIFO_U2H. 7-4 H2U_LEVEL_SET R/W Fh FIFO_H2U FIFO Level Flag Trip SetSets the level for FIFO_H2U at which the Level Flag trips. This is a (>) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. 7-4H2U_LEVEL_SETR/WFhFIFO_H2U FIFO Level Flag Trip SetSets the level for FIFO_H2U at which the Level Flag trips. This is a (>) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. 3-0 U2H_LEVEL_SET R/W 0h FIFO_U2H FIFO Level Flag Trip SetSets the level for FIFO_U2H at which the Level Flag trips. This is a (<) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. 3-0U2H_LEVEL_SETR/W0hFIFO_U2H FIFO Level Flag Trip SetSets the level for FIFO_U2H at which the Level Flag trips. This is a (<) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0. ALARM_ACT Register (Offset = 10h) [Reset = 8020h] Return to the Register Map . ALARM_ACT Register Field Descriptions Bit Field Type Reset Description 15-14 SD_FLT R/W 2h Self-Diagnostic Fault Action These bits set the device action after a self-diagnostic fault. 0h = No Action 1h = Set DAC to CLEAR state 2h = Switch to alarm voltage determined by ALMV_POL (default) 3h = Place DAC into Hi-Z (power-down) 13-12 TEMP_FLT R/W 0h TEMP Fault ActionThese bits set the device action if the ADC temperature is outside the TEMP_THRESHOLD Hi or Lo thresholds.0h through 3h = Same as SD_FLT field (default 0h) 11-10 AIN1_FLT R/W 0h AIN1 Fault ActionThese bits set the device action if the ADC AIN1 channel is outside the AIN1_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 9-8 AIN0_FLT R/W 0h AIN0 Fault Action These bits set the device action if the ADC AIN0 channel is outside the AIN0_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 7-6 CRC_WDT_FLT R/W 0h CRC and WDT Fault ActionThese bits set the device action when a SPI CRC or SPI Watchdog Timeout error occurs. 0h through 3h = Same as SD_FLT field (default 0h) 5-4 VREF_FLT R/W 2h VREF Fault ActionThese bits set the device action when a fault is detected on VREF. 0h through 3h = Same as SD_FLT field a 3-2 THERM_ERR_FLT R/W 0h Thermal Error Fault ActionThese bits set the device action when a high temperature error occurs (> 130°C). 0h through 3h = Same as SD_FLT field (default 0h) 1-0 THERM_WARN_FLT R/W 0h Thermal Warning Fault ActionThese bits set the device action when a high temperature warning occurs (> 85°C). 0h through 3h = Same as SD_FLT field (default 0h) ALARM_ACT Register (Offset = 10h) [Reset = 8020h] ALARM_ACTReturn to the Register Map . Register Map Register Map ALARM_ACT Register Field Descriptions Bit Field Type Reset Description 15-14 SD_FLT R/W 2h Self-Diagnostic Fault Action These bits set the device action after a self-diagnostic fault. 0h = No Action 1h = Set DAC to CLEAR state 2h = Switch to alarm voltage determined by ALMV_POL (default) 3h = Place DAC into Hi-Z (power-down) 13-12 TEMP_FLT R/W 0h TEMP Fault ActionThese bits set the device action if the ADC temperature is outside the TEMP_THRESHOLD Hi or Lo thresholds.0h through 3h = Same as SD_FLT field (default 0h) 11-10 AIN1_FLT R/W 0h AIN1 Fault ActionThese bits set the device action if the ADC AIN1 channel is outside the AIN1_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 9-8 AIN0_FLT R/W 0h AIN0 Fault Action These bits set the device action if the ADC AIN0 channel is outside the AIN0_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 7-6 CRC_WDT_FLT R/W 0h CRC and WDT Fault ActionThese bits set the device action when a SPI CRC or SPI Watchdog Timeout error occurs. 0h through 3h = Same as SD_FLT field (default 0h) 5-4 VREF_FLT R/W 2h VREF Fault ActionThese bits set the device action when a fault is detected on VREF. 0h through 3h = Same as SD_FLT field a 3-2 THERM_ERR_FLT R/W 0h Thermal Error Fault ActionThese bits set the device action when a high temperature error occurs (> 130°C). 0h through 3h = Same as SD_FLT field (default 0h) 1-0 THERM_WARN_FLT R/W 0h Thermal Warning Fault ActionThese bits set the device action when a high temperature warning occurs (> 85°C). 0h through 3h = Same as SD_FLT field (default 0h) ALARM_ACT Register Field Descriptions Bit Field Type Reset Description 15-14 SD_FLT R/W 2h Self-Diagnostic Fault Action These bits set the device action after a self-diagnostic fault. 0h = No Action 1h = Set DAC to CLEAR state 2h = Switch to alarm voltage determined by ALMV_POL (default) 3h = Place DAC into Hi-Z (power-down) 13-12 TEMP_FLT R/W 0h TEMP Fault ActionThese bits set the device action if the ADC temperature is outside the TEMP_THRESHOLD Hi or Lo thresholds.0h through 3h = Same as SD_FLT field (default 0h) 11-10 AIN1_FLT R/W 0h AIN1 Fault ActionThese bits set the device action if the ADC AIN1 channel is outside the AIN1_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 9-8 AIN0_FLT R/W 0h AIN0 Fault Action These bits set the device action if the ADC AIN0 channel is outside the AIN0_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 7-6 CRC_WDT_FLT R/W 0h CRC and WDT Fault ActionThese bits set the device action when a SPI CRC or SPI Watchdog Timeout error occurs. 0h through 3h = Same as SD_FLT field (default 0h) 5-4 VREF_FLT R/W 2h VREF Fault ActionThese bits set the device action when a fault is detected on VREF. 0h through 3h = Same as SD_FLT field a 3-2 THERM_ERR_FLT R/W 0h Thermal Error Fault ActionThese bits set the device action when a high temperature error occurs (> 130°C). 0h through 3h = Same as SD_FLT field (default 0h) 1-0 THERM_WARN_FLT R/W 0h Thermal Warning Fault ActionThese bits set the device action when a high temperature warning occurs (> 85°C). 0h through 3h = Same as SD_FLT field (default 0h) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-14 SD_FLT R/W 2h Self-Diagnostic Fault Action These bits set the device action after a self-diagnostic fault. 0h = No Action 1h = Set DAC to CLEAR state 2h = Switch to alarm voltage determined by ALMV_POL (default) 3h = Place DAC into Hi-Z (power-down) 13-12 TEMP_FLT R/W 0h TEMP Fault ActionThese bits set the device action if the ADC temperature is outside the TEMP_THRESHOLD Hi or Lo thresholds.0h through 3h = Same as SD_FLT field (default 0h) 11-10 AIN1_FLT R/W 0h AIN1 Fault ActionThese bits set the device action if the ADC AIN1 channel is outside the AIN1_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 9-8 AIN0_FLT R/W 0h AIN0 Fault Action These bits set the device action if the ADC AIN0 channel is outside the AIN0_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 7-6 CRC_WDT_FLT R/W 0h CRC and WDT Fault ActionThese bits set the device action when a SPI CRC or SPI Watchdog Timeout error occurs. 0h through 3h = Same as SD_FLT field (default 0h) 5-4 VREF_FLT R/W 2h VREF Fault ActionThese bits set the device action when a fault is detected on VREF. 0h through 3h = Same as SD_FLT field a 3-2 THERM_ERR_FLT R/W 0h Thermal Error Fault ActionThese bits set the device action when a high temperature error occurs (> 130°C). 0h through 3h = Same as SD_FLT field (default 0h) 1-0 THERM_WARN_FLT R/W 0h Thermal Warning Fault ActionThese bits set the device action when a high temperature warning occurs (> 85°C). 0h through 3h = Same as SD_FLT field (default 0h) 15-14 SD_FLT R/W 2h Self-Diagnostic Fault Action These bits set the device action after a self-diagnostic fault. 0h = No Action 1h = Set DAC to CLEAR state 2h = Switch to alarm voltage determined by ALMV_POL (default) 3h = Place DAC into Hi-Z (power-down) 15-14SD_FLTR/W2hSelf-Diagnostic Fault Action These bits set the device action after a self-diagnostic fault. 0h = No Action 1h = Set DAC to CLEAR state 2h = Switch to alarm voltage determined by ALMV_POL (default) 3h = Place DAC into Hi-Z (power-down) These bits set the device action after a self-diagnostic fault.0h = No Action1h = Set DAC to CLEAR state2h = Switch to alarm voltage determined by ALMV_POL (default)3h = Place DAC into Hi-Z (power-down) 13-12 TEMP_FLT R/W 0h TEMP Fault ActionThese bits set the device action if the ADC temperature is outside the TEMP_THRESHOLD Hi or Lo thresholds.0h through 3h = Same as SD_FLT field (default 0h) 13-12TEMP_FLTR/W0hTEMP Fault ActionThese bits set the device action if the ADC temperature is outside the TEMP_THRESHOLD Hi or Lo thresholds.0h through 3h = Same as SD_FLT field (default 0h) 0h through 3h = Same as SD_FLT field (default 0h) 11-10 AIN1_FLT R/W 0h AIN1 Fault ActionThese bits set the device action if the ADC AIN1 channel is outside the AIN1_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 11-10AIN1_FLTR/W0hAIN1 Fault ActionThese bits set the device action if the ADC AIN1 channel is outside the AIN1_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 0h through 3h = Same as SD_FLT field (default 0h) 9-8 AIN0_FLT R/W 0h AIN0 Fault Action These bits set the device action if the ADC AIN0 channel is outside the AIN0_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 9-8AIN0_FLTR/W0hAIN0 Fault Action These bits set the device action if the ADC AIN0 channel is outside the AIN0_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 0h through 3h = Same as SD_FLT field (default 0h) 7-6 CRC_WDT_FLT R/W 0h CRC and WDT Fault ActionThese bits set the device action when a SPI CRC or SPI Watchdog Timeout error occurs. 0h through 3h = Same as SD_FLT field (default 0h) 7-6CRC_WDT_FLTR/W0hCRC and WDT Fault ActionThese bits set the device action when a SPI CRC or SPI Watchdog Timeout error occurs. 0h through 3h = Same as SD_FLT field (default 0h) 0h through 3h = Same as SD_FLT field (default 0h) 5-4 VREF_FLT R/W 2h VREF Fault ActionThese bits set the device action when a fault is detected on VREF. 0h through 3h = Same as SD_FLT field a 5-4VREF_FLTR/W2hVREF Fault ActionThese bits set the device action when a fault is detected on VREF. 0h through 3h = Same as SD_FLT field a 0h through 3h = Same as SD_FLT field a 3-2 THERM_ERR_FLT R/W 0h Thermal Error Fault ActionThese bits set the device action when a high temperature error occurs (> 130°C). 0h through 3h = Same as SD_FLT field (default 0h) 3-2THERM_ERR_FLTR/W0hThermal Error Fault ActionThese bits set the device action when a high temperature error occurs (> 130°C). 0h through 3h = Same as SD_FLT field (default 0h) 0h through 3h = Same as SD_FLT field (default 0h) 1-0 THERM_WARN_FLT R/W 0h Thermal Warning Fault ActionThese bits set the device action when a high temperature warning occurs (> 85°C). 0h through 3h = Same as SD_FLT field (default 0h) 1-0THERM_WARN_FLTR/W0hThermal Warning Fault ActionThese bits set the device action when a high temperature warning occurs (> 85°C). 0h through 3h = Same as SD_FLT field (default 0h) 0h through 3h = Same as SD_FLT field (default 0h) WDT Register (Offset = 11h) [Reset = 0018h] Return to the Register Map . WDT Register Field Descriptions Bit Field Type Reset Description 15-6 RESERVED R 0h 5-3 WDT_UP R/W 3h Watchdog Timer (WDT) Upper LimitIf the WDT is enabled and the timer exceeds the programmed value, a WDT error is asserted. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = 53 ms (64 clocks) 1h = 106 ms (128 clocks) 2h = 427 ms (512 clocks) 3h = 853 ms (1024 clocks, default) 4h = 1.7 s (2048 clocks) 5h = 2.56 s (3072 clocks) 6h = 3.41 s (4096 clocks) 7h = 5.12 s (6144 clocks) 2-1 WDT_LO R/W 0h WDT Lower LimitIf the WDT is enabled and the WDT Lower Limit is enabled, then only a write to this register resets the WDT timer. If the write occurs before the WDT Lower Limit time, or after the WDT Upper Limit time, then a WDT error is asserted. If WDT Lower Limit is disabled, then a write to any register resets the timer. This is true for both SPI and UART Break modes. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = Disabled (default) 1h = 53 ms (64 clocks) 2h = 106 ms (128 clocks) 3h = 427 ms (512 clocks) 0 WDT_EN R/W 0h WDT Enable 0h = Disabled (default); 1h = Enabled WDT Register (Offset = 11h) [Reset = 0018h] WDTReturn to the Register Map . Register Map Register Map WDT Register Field Descriptions Bit Field Type Reset Description 15-6 RESERVED R 0h 5-3 WDT_UP R/W 3h Watchdog Timer (WDT) Upper LimitIf the WDT is enabled and the timer exceeds the programmed value, a WDT error is asserted. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = 53 ms (64 clocks) 1h = 106 ms (128 clocks) 2h = 427 ms (512 clocks) 3h = 853 ms (1024 clocks, default) 4h = 1.7 s (2048 clocks) 5h = 2.56 s (3072 clocks) 6h = 3.41 s (4096 clocks) 7h = 5.12 s (6144 clocks) 2-1 WDT_LO R/W 0h WDT Lower LimitIf the WDT is enabled and the WDT Lower Limit is enabled, then only a write to this register resets the WDT timer. If the write occurs before the WDT Lower Limit time, or after the WDT Upper Limit time, then a WDT error is asserted. If WDT Lower Limit is disabled, then a write to any register resets the timer. This is true for both SPI and UART Break modes. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = Disabled (default) 1h = 53 ms (64 clocks) 2h = 106 ms (128 clocks) 3h = 427 ms (512 clocks) 0 WDT_EN R/W 0h WDT Enable 0h = Disabled (default); 1h = Enabled WDT Register Field Descriptions Bit Field Type Reset Description 15-6 RESERVED R 0h 5-3 WDT_UP R/W 3h Watchdog Timer (WDT) Upper LimitIf the WDT is enabled and the timer exceeds the programmed value, a WDT error is asserted. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = 53 ms (64 clocks) 1h = 106 ms (128 clocks) 2h = 427 ms (512 clocks) 3h = 853 ms (1024 clocks, default) 4h = 1.7 s (2048 clocks) 5h = 2.56 s (3072 clocks) 6h = 3.41 s (4096 clocks) 7h = 5.12 s (6144 clocks) 2-1 WDT_LO R/W 0h WDT Lower LimitIf the WDT is enabled and the WDT Lower Limit is enabled, then only a write to this register resets the WDT timer. If the write occurs before the WDT Lower Limit time, or after the WDT Upper Limit time, then a WDT error is asserted. If WDT Lower Limit is disabled, then a write to any register resets the timer. This is true for both SPI and UART Break modes. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = Disabled (default) 1h = 53 ms (64 clocks) 2h = 106 ms (128 clocks) 3h = 427 ms (512 clocks) 0 WDT_EN R/W 0h WDT Enable 0h = Disabled (default); 1h = Enabled Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-6 RESERVED R 0h 5-3 WDT_UP R/W 3h Watchdog Timer (WDT) Upper LimitIf the WDT is enabled and the timer exceeds the programmed value, a WDT error is asserted. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = 53 ms (64 clocks) 1h = 106 ms (128 clocks) 2h = 427 ms (512 clocks) 3h = 853 ms (1024 clocks, default) 4h = 1.7 s (2048 clocks) 5h = 2.56 s (3072 clocks) 6h = 3.41 s (4096 clocks) 7h = 5.12 s (6144 clocks) 2-1 WDT_LO R/W 0h WDT Lower LimitIf the WDT is enabled and the WDT Lower Limit is enabled, then only a write to this register resets the WDT timer. If the write occurs before the WDT Lower Limit time, or after the WDT Upper Limit time, then a WDT error is asserted. If WDT Lower Limit is disabled, then a write to any register resets the timer. This is true for both SPI and UART Break modes. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = Disabled (default) 1h = 53 ms (64 clocks) 2h = 106 ms (128 clocks) 3h = 427 ms (512 clocks) 0 WDT_EN R/W 0h WDT Enable 0h = Disabled (default); 1h = Enabled 15-6 RESERVED R 0h 15-6RESERVEDR0h 5-3 WDT_UP R/W 3h Watchdog Timer (WDT) Upper LimitIf the WDT is enabled and the timer exceeds the programmed value, a WDT error is asserted. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = 53 ms (64 clocks) 1h = 106 ms (128 clocks) 2h = 427 ms (512 clocks) 3h = 853 ms (1024 clocks, default) 4h = 1.7 s (2048 clocks) 5h = 2.56 s (3072 clocks) 6h = 3.41 s (4096 clocks) 7h = 5.12 s (6144 clocks) 5-3WDT_UPR/W3hWatchdog Timer (WDT) Upper LimitIf the WDT is enabled and the timer exceeds the programmed value, a WDT error is asserted. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = 53 ms (64 clocks) 1h = 106 ms (128 clocks) 2h = 427 ms (512 clocks) 3h = 853 ms (1024 clocks, default) 4h = 1.7 s (2048 clocks) 5h = 2.56 s (3072 clocks) 6h = 3.41 s (4096 clocks) 7h = 5.12 s (6144 clocks) 0h = 53 ms (64 clocks) 1h = 106 ms (128 clocks) 2h = 427 ms (512 clocks) 3h = 853 ms (1024 clocks, default) 4h = 1.7 s (2048 clocks) 5h = 2.56 s (3072 clocks) 6h = 3.41 s (4096 clocks) 7h = 5.12 s (6144 clocks) 2-1 WDT_LO R/W 0h WDT Lower LimitIf the WDT is enabled and the WDT Lower Limit is enabled, then only a write to this register resets the WDT timer. If the write occurs before the WDT Lower Limit time, or after the WDT Upper Limit time, then a WDT error is asserted. If WDT Lower Limit is disabled, then a write to any register resets the timer. This is true for both SPI and UART Break modes. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = Disabled (default) 1h = 53 ms (64 clocks) 2h = 106 ms (128 clocks) 3h = 427 ms (512 clocks) 2-1WDT_LOR/W0hWDT Lower LimitIf the WDT is enabled and the WDT Lower Limit is enabled, then only a write to this register resets the WDT timer. If the write occurs before the WDT Lower Limit time, or after the WDT Upper Limit time, then a WDT error is asserted. If WDT Lower Limit is disabled, then a write to any register resets the timer. This is true for both SPI and UART Break modes. All times are based on 1200-Hz clock (1.2288 MHz / 1024).0h = Disabled (default) 1h = 53 ms (64 clocks) 2h = 106 ms (128 clocks) 3h = 427 ms (512 clocks) 0h = Disabled (default) 1h = 53 ms (64 clocks) 2h = 106 ms (128 clocks) 3h = 427 ms (512 clocks) 0 WDT_EN R/W 0h WDT Enable 0h = Disabled (default); 1h = Enabled 0WDT_ENR/W0hWDT Enable 0h = Disabled (default); 1h = Enabled 0h = Disabled (default); 1h = Enabled AIN0_THRESHOLD Register (Offset = 12h) [Reset = FF00h] Return to the Register Map . AIN0_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN0 {[11:4],4b1111} This value is compared (>) against AIN0 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN0 {[11:4],4b0000} This value is compared (<) against AIN0 data bits[11:0]. AIN0_THRESHOLD Register (Offset = 12h) [Reset = FF00h] AIN0_THRESHOLDReturn to the Register Map . Register Map Register Map AIN0_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN0 {[11:4],4b1111} This value is compared (>) against AIN0 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN0 {[11:4],4b0000} This value is compared (<) against AIN0 data bits[11:0]. AIN0_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN0 {[11:4],4b1111} This value is compared (>) against AIN0 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN0 {[11:4],4b0000} This value is compared (<) against AIN0 data bits[11:0]. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-8 Hi R/W FFh High Threshold for Channel AIN0 {[11:4],4b1111} This value is compared (>) against AIN0 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN0 {[11:4],4b0000} This value is compared (<) against AIN0 data bits[11:0]. 15-8 Hi R/W FFh High Threshold for Channel AIN0 {[11:4],4b1111} This value is compared (>) against AIN0 data bits[11:0]. 15-8HiR/WFFh High Threshold for Channel AIN0 {[11:4],4b1111} This value is compared (>) against AIN0 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN0 {[11:4],4b0000} This value is compared (<) against AIN0 data bits[11:0]. 7-0LoR/W0h Low Threshold for Channel AIN0 {[11:4],4b0000} This value is compared (<) against AIN0 data bits[11:0]. AIN1_THRESHOLD Register (Offset = 13h) [Reset = FF00h] Return to the Register Map . AIN1_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN1 {[11:4],4b1111} This value is compared (>) against AIN1 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN1 {[11:4],4b0000} This value is compared (<) against AIN1 data bits[11:0]. AIN1_THRESHOLD Register (Offset = 13h) [Reset = FF00h] AIN1_THRESHOLDReturn to the Register Map . Register Map Register Map AIN1_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN1 {[11:4],4b1111} This value is compared (>) against AIN1 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN1 {[11:4],4b0000} This value is compared (<) against AIN1 data bits[11:0]. AIN1_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN1 {[11:4],4b1111} This value is compared (>) against AIN1 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN1 {[11:4],4b0000} This value is compared (<) against AIN1 data bits[11:0]. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-8 Hi R/W FFh High Threshold for Channel AIN1 {[11:4],4b1111} This value is compared (>) against AIN1 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN1 {[11:4],4b0000} This value is compared (<) against AIN1 data bits[11:0]. 15-8 Hi R/W FFh High Threshold for Channel AIN1 {[11:4],4b1111} This value is compared (>) against AIN1 data bits[11:0]. 15-8HiR/WFFh High Threshold for Channel AIN1 {[11:4],4b1111} This value is compared (>) against AIN1 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN1 {[11:4],4b0000} This value is compared (<) against AIN1 data bits[11:0]. 7-0LoR/W0h Low Threshold for Channel AIN1 {[11:4],4b0000} This value is compared (<) against AIN1 data bits[11:0]. TEMP_THRESHOLD Register (Offset = 14h) [Reset = FF00h] Return to the Register Map . TEMP_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel TEMP {[11:4],4b1111} This value is compared (>) against TEMP data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel TEMP {[11:4],4b0000} This value is compared (<) against TEMP data bits[11:0]. TEMP_THRESHOLD Register (Offset = 14h) [Reset = FF00h] TEMP_THRESHOLDReturn to the Register Map . Register Map Register Map TEMP_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel TEMP {[11:4],4b1111} This value is compared (>) against TEMP data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel TEMP {[11:4],4b0000} This value is compared (<) against TEMP data bits[11:0]. TEMP_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel TEMP {[11:4],4b1111} This value is compared (>) against TEMP data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel TEMP {[11:4],4b0000} This value is compared (<) against TEMP data bits[11:0]. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-8 Hi R/W FFh High Threshold for Channel TEMP {[11:4],4b1111} This value is compared (>) against TEMP data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel TEMP {[11:4],4b0000} This value is compared (<) against TEMP data bits[11:0]. 15-8 Hi R/W FFh High Threshold for Channel TEMP {[11:4],4b1111} This value is compared (>) against TEMP data bits[11:0]. 15-8HiR/WFFh High Threshold for Channel TEMP {[11:4],4b1111} This value is compared (>) against TEMP data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel TEMP {[11:4],4b0000} This value is compared (<) against TEMP data bits[11:0]. 7-0LoR/W0h Low Threshold for Channel TEMP {[11:4],4b0000} This value is compared (<) against TEMP data bits[11:0]. FIFO_U2H_WR Register (Offset = 15h) [Reset = 0000h] Return to the Register Map . This register controls the HART to microcontroller FIFO buffer. FIFO_U2H_WR Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h 8 PARITY WO 0h ParityOdd parity bit to be transmitted with data. This field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. 7-0 DATA WO 0h Data ByteThis field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. FIFO_U2H_WR Register (Offset = 15h) [Reset = 0000h] FIFO_U2H_WRReturn to the Register Map . Register Map Register MapThis register controls the HART to microcontroller FIFO buffer. FIFO_U2H_WR Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h 8 PARITY WO 0h ParityOdd parity bit to be transmitted with data. This field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. 7-0 DATA WO 0h Data ByteThis field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. FIFO_U2H_WR Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h 8 PARITY WO 0h ParityOdd parity bit to be transmitted with data. This field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. 7-0 DATA WO 0h Data ByteThis field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-9 RESERVED R 0h 8 PARITY WO 0h ParityOdd parity bit to be transmitted with data. This field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. 7-0 DATA WO 0h Data ByteThis field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. 15-9 RESERVED R 0h 15-9RESERVEDR0h 8 PARITY WO 0h ParityOdd parity bit to be transmitted with data. This field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. 8PARITYWO0hParityOdd parity bit to be transmitted with data. This field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. 7-0 DATA WO 0h Data ByteThis field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. 7-0DATAWO0hData ByteThis field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored. UBM Register (Offset = 16h) [Reset = 0000h] Return to the Register Map . UBM Register Field Descriptions Bit Field Type Reset Description 15-1 RESERVED R 0h 0 REG_MODE R/W 0h Register ModeConfigure the rest of the Register Map to be accessed by UART break mode (UBM) or SPI. This register can only be written by the UART Break communication.0h = SPI Mode (default) 1h = UART Break Mode UBM Register (Offset = 16h) [Reset = 0000h] UBMReturn to the Register Map . Register Map Register Map UBM Register Field Descriptions Bit Field Type Reset Description 15-1 RESERVED R 0h 0 REG_MODE R/W 0h Register ModeConfigure the rest of the Register Map to be accessed by UART break mode (UBM) or SPI. This register can only be written by the UART Break communication.0h = SPI Mode (default) 1h = UART Break Mode UBM Register Field Descriptions Bit Field Type Reset Description 15-1 RESERVED R 0h 0 REG_MODE R/W 0h Register ModeConfigure the rest of the Register Map to be accessed by UART break mode (UBM) or SPI. This register can only be written by the UART Break communication.0h = SPI Mode (default) 1h = UART Break Mode Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-1 RESERVED R 0h 0 REG_MODE R/W 0h Register ModeConfigure the rest of the Register Map to be accessed by UART break mode (UBM) or SPI. This register can only be written by the UART Break communication.0h = SPI Mode (default) 1h = UART Break Mode 15-1 RESERVED R 0h 15-1RESERVEDR0h 0 REG_MODE R/W 0h Register ModeConfigure the rest of the Register Map to be accessed by UART break mode (UBM) or SPI. This register can only be written by the UART Break communication.0h = SPI Mode (default) 1h = UART Break Mode 0REG_MODER/W0hRegister ModeConfigure the rest of the Register Map to be accessed by UART break mode (UBM) or SPI. This register can only be written by the UART Break communication.0h = SPI Mode (default) 1h = UART Break Mode 0h = SPI Mode (default)1h = UART Break Mode SCRATCH Register (Offset = 18h) [Reset = FFFFh] Return to the Register Map . SCRATCH Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W FFFFh Scratch Data Data written is read back as the inverted value. For example, writing 0xAAAA is read back as 0x5555. SCRATCH Register (Offset = 18h) [Reset = FFFFh] SCRATCHReturn to the Register Map . Register Map Register Map SCRATCH Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W FFFFh Scratch Data Data written is read back as the inverted value. For example, writing 0xAAAA is read back as 0x5555. SCRATCH Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W FFFFh Scratch Data Data written is read back as the inverted value. For example, writing 0xAAAA is read back as 0x5555. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 DATA R/W FFFFh Scratch Data Data written is read back as the inverted value. For example, writing 0xAAAA is read back as 0x5555. 15-0 DATA R/W FFFFh Scratch Data Data written is read back as the inverted value. For example, writing 0xAAAA is read back as 0x5555. 15-0DATAR/WFFFFh Scratch Data Data written is read back as the inverted value. For example, writing 0xAAAA is read back as 0x5555. Data written is read back as the inverted value.For example, writing 0xAAAA is read back as 0x5555. CHIP_ID_LSB Register (Offset = 19h) Return to the Register Map . CHIP ID LSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Unique part number within each lot CHIP_ID_LSB Register (Offset = 19h)CHIP_ID_LSBReturn to the Register Map . Register Map Register Map CHIP ID LSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Unique part number within each lot CHIP ID LSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Unique part number within each lot Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 ID R Unique part number within each lot 15-0 ID R Unique part number within each lot 15-0IDR Unique part number within each lot Unique part number within each lot CHIP_ID_MSB Register (Offset = 1Ah) Return to the Register Map . CHIP ID MSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Encoded lot identification number CHIP_ID_MSB Register (Offset = 1Ah) CHIP_ID_MSBReturn to the Register Map . Register Map Register Map CHIP ID MSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Encoded lot identification number CHIP ID MSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Encoded lot identification number Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 ID R Encoded lot identification number 15-0 ID R Encoded lot identification number 15-0IDR Encoded lot identification number Encoded lot identification number GPIO_CFG Register (Offset = 1Bh) [Reset = 00FFh] Return to the Register Map . GPIO CONFIG Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R 0h 14-8 EN R/W 00h GPIO per Pin Enable. (See for additional configuration required specific to each pin and communication mode) [14] = GPIO6 [13] = GPIO5 [12] = GPIO4 [11] = GPIO3 [10] = GPIO2 [9] = GPIO1 [8] = GPIO00h = GPIO function disable1h = GPIO function enabledFor any pin used either for the communication function or not used as an active GPIO, set this bit to 0h. 7 RESERVED R 0h 6-0 ODE R/W FFh Pseudo Open Drain EnableGPIO output enable and pseudo open drain functionality on the GPIO pins. (See for additional configuration required specific to each pin and communication mode.) [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO00h = Push-pull output enabled1h = Pseudo open-drain output enabled GPIO_CFG Register (Offset = 1Bh) [Reset = 00FFh] GPIO_CFGReturn to the Register Map . Register Map Register Map GPIO CONFIG Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R 0h 14-8 EN R/W 00h GPIO per Pin Enable. (See for additional configuration required specific to each pin and communication mode) [14] = GPIO6 [13] = GPIO5 [12] = GPIO4 [11] = GPIO3 [10] = GPIO2 [9] = GPIO1 [8] = GPIO00h = GPIO function disable1h = GPIO function enabledFor any pin used either for the communication function or not used as an active GPIO, set this bit to 0h. 7 RESERVED R 0h 6-0 ODE R/W FFh Pseudo Open Drain EnableGPIO output enable and pseudo open drain functionality on the GPIO pins. (See for additional configuration required specific to each pin and communication mode.) [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO00h = Push-pull output enabled1h = Pseudo open-drain output enabled GPIO CONFIG Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R 0h 14-8 EN R/W 00h GPIO per Pin Enable. (See for additional configuration required specific to each pin and communication mode) [14] = GPIO6 [13] = GPIO5 [12] = GPIO4 [11] = GPIO3 [10] = GPIO2 [9] = GPIO1 [8] = GPIO00h = GPIO function disable1h = GPIO function enabledFor any pin used either for the communication function or not used as an active GPIO, set this bit to 0h. 7 RESERVED R 0h 6-0 ODE R/W FFh Pseudo Open Drain EnableGPIO output enable and pseudo open drain functionality on the GPIO pins. (See for additional configuration required specific to each pin and communication mode.) [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO00h = Push-pull output enabled1h = Pseudo open-drain output enabled Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15 RESERVED R 0h 14-8 EN R/W 00h GPIO per Pin Enable. (See for additional configuration required specific to each pin and communication mode) [14] = GPIO6 [13] = GPIO5 [12] = GPIO4 [11] = GPIO3 [10] = GPIO2 [9] = GPIO1 [8] = GPIO00h = GPIO function disable1h = GPIO function enabledFor any pin used either for the communication function or not used as an active GPIO, set this bit to 0h. 7 RESERVED R 0h 6-0 ODE R/W FFh Pseudo Open Drain EnableGPIO output enable and pseudo open drain functionality on the GPIO pins. (See for additional configuration required specific to each pin and communication mode.) [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO00h = Push-pull output enabled1h = Pseudo open-drain output enabled 15 RESERVED R 0h 15RESERVEDR0h 14-8 EN R/W 00h GPIO per Pin Enable. (See for additional configuration required specific to each pin and communication mode) [14] = GPIO6 [13] = GPIO5 [12] = GPIO4 [11] = GPIO3 [10] = GPIO2 [9] = GPIO1 [8] = GPIO00h = GPIO function disable1h = GPIO function enabledFor any pin used either for the communication function or not used as an active GPIO, set this bit to 0h. 14-8ENR/W00hGPIO per Pin Enable. (See for additional configuration required specific to each pin and communication mode) [14] = GPIO6 [13] = GPIO5 [12] = GPIO4 [11] = GPIO3 [10] = GPIO2 [9] = GPIO1 [8] = GPIO00h = GPIO function disable1h = GPIO function enabledFor any pin used either for the communication function or not used as an active GPIO, set this bit to 0h. [14] = GPIO6[13] = GPIO5[12] = GPIO4[11] = GPIO3[10] = GPIO2[9] = GPIO1[8] = GPIO0For any pin used either for the communication function or not used as an active GPIO, set this bit to 0h. 7 RESERVED R 0h 7RESERVEDR0h 6-0 ODE R/W FFh Pseudo Open Drain EnableGPIO output enable and pseudo open drain functionality on the GPIO pins. (See for additional configuration required specific to each pin and communication mode.) [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO00h = Push-pull output enabled1h = Pseudo open-drain output enabled 6-0ODER/WFFhPseudo Open Drain EnableGPIO output enable and pseudo open drain functionality on the GPIO pins. (See for additional configuration required specific to each pin and communication mode.) [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO00h = Push-pull output enabled1h = Pseudo open-drain output enabledGPIO output enable and pseudo open drain functionality on the GPIO pins. (See for additional configuration required specific to each pin and communication mode.)[6] = GPIO6[5] = GPIO5[4] = GPIO4[3] = GPIO3[2] = GPIO2[1] = GPIO1[0] = GPIO0 GPIO Register (Offset = 1Ch) [Reset = 007Fh] Return to the Register Map . GPIO Register Field Descriptions Bit Field Type Reset Description 15-7 RESERVED R 0h 6-0 DATA R/W 7Fh GPIO pin data. For GPIO input this bit must be written as 1 and GPIO_CFG.ODE = 1 and GPIO_CFG.EN = 1. Reading this register reads the pin value when the pin is correctly enabled. (See for additional configuration required specific to each pin and communication mode) For GPIO output this bit sets the pin value. [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO0 GPIO Register (Offset = 1Ch) [Reset = 007Fh] GPIOReturn to the Register Map . Register Map Register Map GPIO Register Field Descriptions Bit Field Type Reset Description 15-7 RESERVED R 0h 6-0 DATA R/W 7Fh GPIO pin data. For GPIO input this bit must be written as 1 and GPIO_CFG.ODE = 1 and GPIO_CFG.EN = 1. Reading this register reads the pin value when the pin is correctly enabled. (See for additional configuration required specific to each pin and communication mode) For GPIO output this bit sets the pin value. [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO0 GPIO Register Field Descriptions Bit Field Type Reset Description 15-7 RESERVED R 0h 6-0 DATA R/W 7Fh GPIO pin data. For GPIO input this bit must be written as 1 and GPIO_CFG.ODE = 1 and GPIO_CFG.EN = 1. Reading this register reads the pin value when the pin is correctly enabled. (See for additional configuration required specific to each pin and communication mode) For GPIO output this bit sets the pin value. [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO0 Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-7 RESERVED R 0h 6-0 DATA R/W 7Fh GPIO pin data. For GPIO input this bit must be written as 1 and GPIO_CFG.ODE = 1 and GPIO_CFG.EN = 1. Reading this register reads the pin value when the pin is correctly enabled. (See for additional configuration required specific to each pin and communication mode) For GPIO output this bit sets the pin value. [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO0 15-7 RESERVED R 0h 15-7RESERVEDR0h 6-0 DATA R/W 7Fh GPIO pin data. For GPIO input this bit must be written as 1 and GPIO_CFG.ODE = 1 and GPIO_CFG.EN = 1. Reading this register reads the pin value when the pin is correctly enabled. (See for additional configuration required specific to each pin and communication mode) For GPIO output this bit sets the pin value. [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO0 6-0DATAR/W7Fh GPIO pin data. For GPIO input this bit must be written as 1 and GPIO_CFG.ODE = 1 and GPIO_CFG.EN = 1. Reading this register reads the pin value when the pin is correctly enabled. (See for additional configuration required specific to each pin and communication mode) For GPIO output this bit sets the pin value. [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO0 GPIO pin data. For GPIO input this bit must be written as 1 and GPIO_CFG.ODE = 1 and GPIO_CFG.EN = 1. Reading this register reads the pin value when the pin is correctly enabled. (See for additional configuration required specific to each pin and communication mode)For GPIO output this bit sets the pin value.[6] = GPIO6[5] = GPIO5[4] = GPIO4[3] = GPIO3[2] = GPIO2[1] = GPIO1[0] = GPIO0 ALARM_STATUS_MASK Register (Offset = 1Dh) [Reset = EFDFh] Return to the Register Map . ALARM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-14 RESERVED R 3h 13 SD_FLT R/W 1h SD Fault Mask0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 12 OSC_FAIL R/W 0h OSC_FAIL Fault Mask Same as SD Fault Mask (default 0h). 11-9 RESERVED R 7h 8 OTP_CRC_ERR R/W 1h OTP CRC Error Mask Same as SD Fault Mask (default 1h). 7 CRC_FLT R/W 1h SPI CRC Fault Mask Same as SD Fault Mask (default 1h). 6 WD_FLT R/W 1h Watchdog Fault Mask Same as SD Fault Mask (default 1h). 5 VREF_FLT R/W 0h VREF Fault Mask Same as SD Fault Mask (default 0h). 4 ADC_AIN1_FLT R/W 1h ADC AIN1 Fault Mask Same as SD Fault Mask (default 1h). 3 ADC_AIN0_FLT R/W 1h ADC AIN0 Fault Mask Same as SD Fault Mask (default 1h). 2 ADC_TEMP_FLT R/W 1h ADC TEMP Fault Mask Same as SD Fault Mask (default 1h). 1 THERM_ERR_FLT R/W 1h Temperature > 130°C Error Mask Same as SD Fault Mask (default 1h). 0 THERM_WARN_FLT R/W 1h Temperature > 85°C Warning Mask Same as SD Fault Mask (default 1h). ALARM_STATUS_MASK Register (Offset = 1Dh) [Reset = EFDFh] ALARM_STATUS_MASKReturn to the Register Map . Register Map Register Map ALARM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-14 RESERVED R 3h 13 SD_FLT R/W 1h SD Fault Mask0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 12 OSC_FAIL R/W 0h OSC_FAIL Fault Mask Same as SD Fault Mask (default 0h). 11-9 RESERVED R 7h 8 OTP_CRC_ERR R/W 1h OTP CRC Error Mask Same as SD Fault Mask (default 1h). 7 CRC_FLT R/W 1h SPI CRC Fault Mask Same as SD Fault Mask (default 1h). 6 WD_FLT R/W 1h Watchdog Fault Mask Same as SD Fault Mask (default 1h). 5 VREF_FLT R/W 0h VREF Fault Mask Same as SD Fault Mask (default 0h). 4 ADC_AIN1_FLT R/W 1h ADC AIN1 Fault Mask Same as SD Fault Mask (default 1h). 3 ADC_AIN0_FLT R/W 1h ADC AIN0 Fault Mask Same as SD Fault Mask (default 1h). 2 ADC_TEMP_FLT R/W 1h ADC TEMP Fault Mask Same as SD Fault Mask (default 1h). 1 THERM_ERR_FLT R/W 1h Temperature > 130°C Error Mask Same as SD Fault Mask (default 1h). 0 THERM_WARN_FLT R/W 1h Temperature > 85°C Warning Mask Same as SD Fault Mask (default 1h). ALARM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-14 RESERVED R 3h 13 SD_FLT R/W 1h SD Fault Mask0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 12 OSC_FAIL R/W 0h OSC_FAIL Fault Mask Same as SD Fault Mask (default 0h). 11-9 RESERVED R 7h 8 OTP_CRC_ERR R/W 1h OTP CRC Error Mask Same as SD Fault Mask (default 1h). 7 CRC_FLT R/W 1h SPI CRC Fault Mask Same as SD Fault Mask (default 1h). 6 WD_FLT R/W 1h Watchdog Fault Mask Same as SD Fault Mask (default 1h). 5 VREF_FLT R/W 0h VREF Fault Mask Same as SD Fault Mask (default 0h). 4 ADC_AIN1_FLT R/W 1h ADC AIN1 Fault Mask Same as SD Fault Mask (default 1h). 3 ADC_AIN0_FLT R/W 1h ADC AIN0 Fault Mask Same as SD Fault Mask (default 1h). 2 ADC_TEMP_FLT R/W 1h ADC TEMP Fault Mask Same as SD Fault Mask (default 1h). 1 THERM_ERR_FLT R/W 1h Temperature > 130°C Error Mask Same as SD Fault Mask (default 1h). 0 THERM_WARN_FLT R/W 1h Temperature > 85°C Warning Mask Same as SD Fault Mask (default 1h). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-14 RESERVED R 3h 13 SD_FLT R/W 1h SD Fault Mask0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 12 OSC_FAIL R/W 0h OSC_FAIL Fault Mask Same as SD Fault Mask (default 0h). 11-9 RESERVED R 7h 8 OTP_CRC_ERR R/W 1h OTP CRC Error Mask Same as SD Fault Mask (default 1h). 7 CRC_FLT R/W 1h SPI CRC Fault Mask Same as SD Fault Mask (default 1h). 6 WD_FLT R/W 1h Watchdog Fault Mask Same as SD Fault Mask (default 1h). 5 VREF_FLT R/W 0h VREF Fault Mask Same as SD Fault Mask (default 0h). 4 ADC_AIN1_FLT R/W 1h ADC AIN1 Fault Mask Same as SD Fault Mask (default 1h). 3 ADC_AIN0_FLT R/W 1h ADC AIN0 Fault Mask Same as SD Fault Mask (default 1h). 2 ADC_TEMP_FLT R/W 1h ADC TEMP Fault Mask Same as SD Fault Mask (default 1h). 1 THERM_ERR_FLT R/W 1h Temperature > 130°C Error Mask Same as SD Fault Mask (default 1h). 0 THERM_WARN_FLT R/W 1h Temperature > 85°C Warning Mask Same as SD Fault Mask (default 1h). 15-14 RESERVED R 3h 15-14RESERVEDR3h 13 SD_FLT R/W 1h SD Fault Mask0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 13SD_FLTR/W1hSD Fault Mask0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 0h = Fault asserts IRQ1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 12 OSC_FAIL R/W 0h OSC_FAIL Fault Mask Same as SD Fault Mask (default 0h). 12OSC_FAILR/W0hOSC_FAIL Fault Mask Same as SD Fault Mask (default 0h). Same as SD Fault Mask (default 0h). 11-9 RESERVED R 7h 11-9RESERVEDR7h 8 OTP_CRC_ERR R/W 1h OTP CRC Error Mask Same as SD Fault Mask (default 1h). 8OTP_CRC_ERRR/W1hOTP CRC Error Mask Same as SD Fault Mask (default 1h). Same as SD Fault Mask (default 1h). 7 CRC_FLT R/W 1h SPI CRC Fault Mask Same as SD Fault Mask (default 1h). 7CRC_FLTR/W1hSPI CRC Fault Mask Same as SD Fault Mask (default 1h). Same as SD Fault Mask (default 1h). 6 WD_FLT R/W 1h Watchdog Fault Mask Same as SD Fault Mask (default 1h). 6WD_FLTR/W1hWatchdog Fault Mask Same as SD Fault Mask (default 1h). Same as SD Fault Mask (default 1h). 5 VREF_FLT R/W 0h VREF Fault Mask Same as SD Fault Mask (default 0h). 5VREF_FLTR/W0hVREF Fault Mask Same as SD Fault Mask (default 0h). Same as SD Fault Mask (default 0h). 4 ADC_AIN1_FLT R/W 1h ADC AIN1 Fault Mask Same as SD Fault Mask (default 1h). 4ADC_AIN1_FLTR/W1hADC AIN1 Fault Mask Same as SD Fault Mask (default 1h). Same as SD Fault Mask (default 1h). 3 ADC_AIN0_FLT R/W 1h ADC AIN0 Fault Mask Same as SD Fault Mask (default 1h). 3ADC_AIN0_FLTR/W1hADC AIN0 Fault Mask Same as SD Fault Mask (default 1h). Same as SD Fault Mask (default 1h). 2 ADC_TEMP_FLT R/W 1h ADC TEMP Fault Mask Same as SD Fault Mask (default 1h). 2ADC_TEMP_FLTR/W1hADC TEMP Fault Mask Same as SD Fault Mask (default 1h). Same as SD Fault Mask (default 1h). 1 THERM_ERR_FLT R/W 1h Temperature > 130°C Error Mask Same as SD Fault Mask (default 1h). 1THERM_ERR_FLTR/W1hTemperature > 130°C Error Mask Same as SD Fault Mask (default 1h). Same as SD Fault Mask (default 1h). 0 THERM_WARN_FLT R/W 1h Temperature > 85°C Warning Mask Same as SD Fault Mask (default 1h). 0THERM_WARN_FLTR/W1hTemperature > 85°C Warning Mask Same as SD Fault Mask (default 1h). Same as SD Fault Mask (default 1h). GEN_STATUS_MASK Register (Offset = 1Eh) [Reset = FFFFh] Return to the Register Map . GEN_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-11 RESERVED R 1Fh 10 BIST_DONE R/W 1h BIST Done Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 9 BIST_FAIL R/W 1h BIST Failed Fault Mask Same as BIST Done Mask (default 1h). 8 RESERVED R 1h 7 SR_BUSYn R/W 1h Slew Rate Not Busy Mask Same as BIST Done Mask (default 1h). 6 ADC_EOC R/W 1h ADC End Of Conversion Mask Same as BIST Done Mask (default 1h). 5-4 RESERVED R 3h 3 BREAK_FRAME_ERR R/W 1h Break Frame Error Fault Mask Same as BIST Done Mask (default 1h). 2 BREAK_PARITY_ERR R/W 1h Break Parity Error Fault Mask Same as BIST Done Mask (default 1h). 1 UART_FRAME_ERR R/W 1h UART Frame Error Fault Mask Same as BIST Done Mask (default 1h). 0 UART_PARITY_ERR R/W 1h UART Parity Error Fault Mask Same as BIST Done Mask (default 1h). GEN_STATUS_MASK Register (Offset = 1Eh) [Reset = FFFFh] GEN_STATUS_MASKReturn to the Register Map . Register Map Register Map GEN_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-11 RESERVED R 1Fh 10 BIST_DONE R/W 1h BIST Done Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 9 BIST_FAIL R/W 1h BIST Failed Fault Mask Same as BIST Done Mask (default 1h). 8 RESERVED R 1h 7 SR_BUSYn R/W 1h Slew Rate Not Busy Mask Same as BIST Done Mask (default 1h). 6 ADC_EOC R/W 1h ADC End Of Conversion Mask Same as BIST Done Mask (default 1h). 5-4 RESERVED R 3h 3 BREAK_FRAME_ERR R/W 1h Break Frame Error Fault Mask Same as BIST Done Mask (default 1h). 2 BREAK_PARITY_ERR R/W 1h Break Parity Error Fault Mask Same as BIST Done Mask (default 1h). 1 UART_FRAME_ERR R/W 1h UART Frame Error Fault Mask Same as BIST Done Mask (default 1h). 0 UART_PARITY_ERR R/W 1h UART Parity Error Fault Mask Same as BIST Done Mask (default 1h). GEN_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-11 RESERVED R 1Fh 10 BIST_DONE R/W 1h BIST Done Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 9 BIST_FAIL R/W 1h BIST Failed Fault Mask Same as BIST Done Mask (default 1h). 8 RESERVED R 1h 7 SR_BUSYn R/W 1h Slew Rate Not Busy Mask Same as BIST Done Mask (default 1h). 6 ADC_EOC R/W 1h ADC End Of Conversion Mask Same as BIST Done Mask (default 1h). 5-4 RESERVED R 3h 3 BREAK_FRAME_ERR R/W 1h Break Frame Error Fault Mask Same as BIST Done Mask (default 1h). 2 BREAK_PARITY_ERR R/W 1h Break Parity Error Fault Mask Same as BIST Done Mask (default 1h). 1 UART_FRAME_ERR R/W 1h UART Frame Error Fault Mask Same as BIST Done Mask (default 1h). 0 UART_PARITY_ERR R/W 1h UART Parity Error Fault Mask Same as BIST Done Mask (default 1h). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-11 RESERVED R 1Fh 10 BIST_DONE R/W 1h BIST Done Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 9 BIST_FAIL R/W 1h BIST Failed Fault Mask Same as BIST Done Mask (default 1h). 8 RESERVED R 1h 7 SR_BUSYn R/W 1h Slew Rate Not Busy Mask Same as BIST Done Mask (default 1h). 6 ADC_EOC R/W 1h ADC End Of Conversion Mask Same as BIST Done Mask (default 1h). 5-4 RESERVED R 3h 3 BREAK_FRAME_ERR R/W 1h Break Frame Error Fault Mask Same as BIST Done Mask (default 1h). 2 BREAK_PARITY_ERR R/W 1h Break Parity Error Fault Mask Same as BIST Done Mask (default 1h). 1 UART_FRAME_ERR R/W 1h UART Frame Error Fault Mask Same as BIST Done Mask (default 1h). 0 UART_PARITY_ERR R/W 1h UART Parity Error Fault Mask Same as BIST Done Mask (default 1h). 15-11 RESERVED R 1Fh 15-11RESERVEDR1Fh 10 BIST_DONE R/W 1h BIST Done Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 10BIST_DONER/W1hBIST Done Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 0h = Fault asserts IRQ1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 9 BIST_FAIL R/W 1h BIST Failed Fault Mask Same as BIST Done Mask (default 1h). 9BIST_FAILR/W1hBIST Failed Fault Mask Same as BIST Done Mask (default 1h). Same as BIST Done Mask (default 1h). 8 RESERVED R 1h 8RESERVEDR1h 7 SR_BUSYn R/W 1h Slew Rate Not Busy Mask Same as BIST Done Mask (default 1h). 7SR_BUSYnR/W1hSlew Rate Not Busy Mask Same as BIST Done Mask (default 1h). Same as BIST Done Mask (default 1h). 6 ADC_EOC R/W 1h ADC End Of Conversion Mask Same as BIST Done Mask (default 1h). 6ADC_EOCR/W1hADC End Of Conversion Mask Same as BIST Done Mask (default 1h). Same as BIST Done Mask (default 1h). 5-4 RESERVED R 3h 5-4RESERVEDR3h 3 BREAK_FRAME_ERR R/W 1h Break Frame Error Fault Mask Same as BIST Done Mask (default 1h). 3BREAK_FRAME_ERRR/W1hBreak Frame Error Fault Mask Same as BIST Done Mask (default 1h). Same as BIST Done Mask (default 1h). 2 BREAK_PARITY_ERR R/W 1h Break Parity Error Fault Mask Same as BIST Done Mask (default 1h). 2BREAK_PARITY_ERRR/W1hBreak Parity Error Fault Mask Same as BIST Done Mask (default 1h). Same as BIST Done Mask (default 1h). 1 UART_FRAME_ERR R/W 1h UART Frame Error Fault Mask Same as BIST Done Mask (default 1h). 1UART_FRAME_ERRR/W1hUART Frame Error Fault Mask Same as BIST Done Mask (default 1h). Same as BIST Done Mask (default 1h). 0 UART_PARITY_ERR R/W 1h UART Parity Error Fault Mask Same as BIST Done Mask (default 1h). 0UART_PARITY_ERRR/W1hUART Parity Error Fault Mask Same as BIST Done Mask (default 1h). Same as BIST Done Mask (default 1h). MODEM_STATUS_MASK Register (Offset = 1Fh) [Reset = FFFFh] Return to the Register Map . MODEM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R 7h 12 GAP_ERR R/W 1h HART Gap Error Fault Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 11 FRAME_ERR R/W 1h HART Frame Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 10 PARITY_ERR R/W 1h HART Parity (ODD) Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 9 FIFO_H2U_LEVEL_FLAG R/W 1h FIFO_H2U Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 8 FIFO_H2U_FULL_FLAG R/W 1h FIFO_H2U Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 7 FIFO_H2U_EMPTY_FLAG R/W 1h FIFO_H2U Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 6 FIFO_U2H_LEVEL_FLAG R/W 1h FIFO_U2H Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 5 FIFO_U2H_FULL_FLAG R/W 1h FIFO_U2H Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 4 FIFO_U2H_EMPTY_FLAG R/W 1h FIFO_U2H Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 3 CD_DEASSERT R/W 1h CD Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 2 CD_ASSERT R/W 1h CD Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 1 CTS_DEASSERT R/W 1h CTS Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 0 CTS_ASSERT R/W 1h CTS Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). MODEM_STATUS_MASK Register (Offset = 1Fh) [Reset = FFFFh] MODEM_STATUS_MASKReturn to the Register Map . Register Map Register Map MODEM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R 7h 12 GAP_ERR R/W 1h HART Gap Error Fault Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 11 FRAME_ERR R/W 1h HART Frame Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 10 PARITY_ERR R/W 1h HART Parity (ODD) Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 9 FIFO_H2U_LEVEL_FLAG R/W 1h FIFO_H2U Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 8 FIFO_H2U_FULL_FLAG R/W 1h FIFO_H2U Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 7 FIFO_H2U_EMPTY_FLAG R/W 1h FIFO_H2U Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 6 FIFO_U2H_LEVEL_FLAG R/W 1h FIFO_U2H Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 5 FIFO_U2H_FULL_FLAG R/W 1h FIFO_U2H Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 4 FIFO_U2H_EMPTY_FLAG R/W 1h FIFO_U2H Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 3 CD_DEASSERT R/W 1h CD Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 2 CD_ASSERT R/W 1h CD Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 1 CTS_DEASSERT R/W 1h CTS Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 0 CTS_ASSERT R/W 1h CTS Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). MODEM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R 7h 12 GAP_ERR R/W 1h HART Gap Error Fault Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 11 FRAME_ERR R/W 1h HART Frame Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 10 PARITY_ERR R/W 1h HART Parity (ODD) Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 9 FIFO_H2U_LEVEL_FLAG R/W 1h FIFO_H2U Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 8 FIFO_H2U_FULL_FLAG R/W 1h FIFO_H2U Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 7 FIFO_H2U_EMPTY_FLAG R/W 1h FIFO_H2U Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 6 FIFO_U2H_LEVEL_FLAG R/W 1h FIFO_U2H Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 5 FIFO_U2H_FULL_FLAG R/W 1h FIFO_U2H Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 4 FIFO_U2H_EMPTY_FLAG R/W 1h FIFO_U2H Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 3 CD_DEASSERT R/W 1h CD Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 2 CD_ASSERT R/W 1h CD Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 1 CTS_DEASSERT R/W 1h CTS Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 0 CTS_ASSERT R/W 1h CTS Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-13 RESERVED R 7h 12 GAP_ERR R/W 1h HART Gap Error Fault Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 11 FRAME_ERR R/W 1h HART Frame Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 10 PARITY_ERR R/W 1h HART Parity (ODD) Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 9 FIFO_H2U_LEVEL_FLAG R/W 1h FIFO_H2U Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 8 FIFO_H2U_FULL_FLAG R/W 1h FIFO_H2U Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 7 FIFO_H2U_EMPTY_FLAG R/W 1h FIFO_H2U Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 6 FIFO_U2H_LEVEL_FLAG R/W 1h FIFO_U2H Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 5 FIFO_U2H_FULL_FLAG R/W 1h FIFO_U2H Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 4 FIFO_U2H_EMPTY_FLAG R/W 1h FIFO_U2H Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 3 CD_DEASSERT R/W 1h CD Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 2 CD_ASSERT R/W 1h CD Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 1 CTS_DEASSERT R/W 1h CTS Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 0 CTS_ASSERT R/W 1h CTS Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 15-13 RESERVED R 7h 15-13RESERVEDR7h 12 GAP_ERR R/W 1h HART Gap Error Fault Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 12GAP_ERRR/W1hHART Gap Error Fault Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 0h = Fault asserts IRQ1h = The mask prevents IRQ or Alarm being triggered (default).The status is always set if the condition exists. 11 FRAME_ERR R/W 1h HART Frame Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 11FRAME_ERRR/W1hHART Frame Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). Same as HART Gap Error Fault Mask (default 1h). 10 PARITY_ERR R/W 1h HART Parity (ODD) Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). 10PARITY_ERRR/W1hHART Parity (ODD) Error Fault Mask Same as HART Gap Error Fault Mask (default 1h). Same as HART Gap Error Fault Mask (default 1h). 9 FIFO_H2U_LEVEL_FLAG R/W 1h FIFO_H2U Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 9FIFO_H2U_LEVEL_FLAGR/W1hFIFO_H2U Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). Same as HART Gap Error Fault Mask (default 1h). 8 FIFO_H2U_FULL_FLAG R/W 1h FIFO_H2U Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 8FIFO_H2U_FULL_FLAGR/W1hFIFO_H2U Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). Same as HART Gap Error Fault Mask (default 1h). 7 FIFO_H2U_EMPTY_FLAG R/W 1h FIFO_H2U Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 7FIFO_H2U_EMPTY_FLAGR/W1hFIFO_H2U Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). Same as HART Gap Error Fault Mask (default 1h). 6 FIFO_U2H_LEVEL_FLAG R/W 1h FIFO_U2H Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). 6FIFO_U2H_LEVEL_FLAGR/W1hFIFO_U2H Level Flag Mask Same as HART Gap Error Fault Mask (default 1h). Same as HART Gap Error Fault Mask (default 1h). 5 FIFO_U2H_FULL_FLAG R/W 1h FIFO_U2H Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). 5FIFO_U2H_FULL_FLAGR/W1hFIFO_U2H Full Flag Mask Same as HART Gap Error Fault Mask (default 1h). Same as HART Gap Error Fault Mask (default 1h). 4 FIFO_U2H_EMPTY_FLAG R/W 1h FIFO_U2H Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). 4FIFO_U2H_EMPTY_FLAGR/W1hFIFO_U2H Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h). Same as HART Gap Error Fault Mask (default 1h). 3 CD_DEASSERT R/W 1h CD Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 3CD_DEASSERTR/W1hCD Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). Same as HART Gap Error Fault Mask (default 1h). 2 CD_ASSERT R/W 1h CD Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 2CD_ASSERTR/W1hCD Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). Same as HART Gap Error Fault Mask (default 1h). 1 CTS_DEASSERT R/W 1h CTS Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 1CTS_DEASSERTR/W1hCTS Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). Same as HART Gap Error Fault Mask (default 1h). 0 CTS_ASSERT R/W 1h CTS Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). 0CTS_ASSERTR/W1hCTS Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h). Same as HART Gap Error Fault Mask (default 1h). ALARM_STATUS Register (Offset = 20h) [Reset = 0200h] Return to the Register Map . ALARM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 SD_FLT R 0h Self Diagnostic (SD) Fault0h = All self diagnostic channels are within threshold limits 1h = At least one of the self diagnostic channels has failed 12 OSC_FAIL R 0h Oscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed IRQ.0h = Oscillator started; 1h = Oscillator has failed to start 11-10 CRC_CNT R 0h CRC Fault CounterIf counter limit ≤ 4 then bits[1:0] of the counter are shown here. If the counter limit = 8 then bits[2:1] of the counter are shown. 9 OTP_LOADEDn R 1h OTP NOT Loaded Clears when OTP has loaded at least once. Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ.0h = OTP has loaded at least once; 1h = OTP has not finished loading 8 OTP_CRC_ERR R 0h OTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation. Sticky, cleared by reading register, unless condition still persist.0h = No OTP CRC fault; 1h = OTP CRC fault 7 CRC_FLT R 0h CRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame. Sticky, cleared by reading register, unless condition still persist.0h = No CRC fault; 1h = CRC fault 6 WD_FLT R 0h Watchdog Timer Fault Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No watchdog fault; 1h = Watchdog fault 5 VREF_FLT R 0h Invalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Valid VREF voltage; 1h = Invalid VREF voltage 4 ADC_AIN1_FLT R 0h ADC AIN1 Fault. Maskable fault. 0h = AIN1 ADC measurement within threshold limits 1h = AIN1 ADC measurement outside threshold limits 3 ADC_AIN0_FLT R 0h ADC AIN0 Fault. Maskable fault. 0h = AIN0 ADC measurement within threshold limits 1h = AIN0 ADC measurement outside threshold limits 2 ADC_TEMP_FLT R 0h ADC Temp Fault. Maskable fault. 0h = TEMP ADC measurement within threshold limits 1h = TEMP ADC measurement outside threshold limits 1 THERM_ERR_FLT R 0h Temperature > 130°C error. Maskable fault. OR with FORCE_FAIL.THERM_ERR_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C 0 THERM_WARN_FLT R 0h Temperature > 85°C warning. Maskable fault. OR with FORCE_FAIL.THERM_WARN_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C ALARM_STATUS Register (Offset = 20h) [Reset = 0200h] ALARM_STATUSReturn to the Register Map . Register Map Register Map ALARM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 SD_FLT R 0h Self Diagnostic (SD) Fault0h = All self diagnostic channels are within threshold limits 1h = At least one of the self diagnostic channels has failed 12 OSC_FAIL R 0h Oscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed IRQ.0h = Oscillator started; 1h = Oscillator has failed to start 11-10 CRC_CNT R 0h CRC Fault CounterIf counter limit ≤ 4 then bits[1:0] of the counter are shown here. If the counter limit = 8 then bits[2:1] of the counter are shown. 9 OTP_LOADEDn R 1h OTP NOT Loaded Clears when OTP has loaded at least once. Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ.0h = OTP has loaded at least once; 1h = OTP has not finished loading 8 OTP_CRC_ERR R 0h OTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation. Sticky, cleared by reading register, unless condition still persist.0h = No OTP CRC fault; 1h = OTP CRC fault 7 CRC_FLT R 0h CRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame. Sticky, cleared by reading register, unless condition still persist.0h = No CRC fault; 1h = CRC fault 6 WD_FLT R 0h Watchdog Timer Fault Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No watchdog fault; 1h = Watchdog fault 5 VREF_FLT R 0h Invalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Valid VREF voltage; 1h = Invalid VREF voltage 4 ADC_AIN1_FLT R 0h ADC AIN1 Fault. Maskable fault. 0h = AIN1 ADC measurement within threshold limits 1h = AIN1 ADC measurement outside threshold limits 3 ADC_AIN0_FLT R 0h ADC AIN0 Fault. Maskable fault. 0h = AIN0 ADC measurement within threshold limits 1h = AIN0 ADC measurement outside threshold limits 2 ADC_TEMP_FLT R 0h ADC Temp Fault. Maskable fault. 0h = TEMP ADC measurement within threshold limits 1h = TEMP ADC measurement outside threshold limits 1 THERM_ERR_FLT R 0h Temperature > 130°C error. Maskable fault. OR with FORCE_FAIL.THERM_ERR_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C 0 THERM_WARN_FLT R 0h Temperature > 85°C warning. Maskable fault. OR with FORCE_FAIL.THERM_WARN_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C ALARM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 SD_FLT R 0h Self Diagnostic (SD) Fault0h = All self diagnostic channels are within threshold limits 1h = At least one of the self diagnostic channels has failed 12 OSC_FAIL R 0h Oscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed IRQ.0h = Oscillator started; 1h = Oscillator has failed to start 11-10 CRC_CNT R 0h CRC Fault CounterIf counter limit ≤ 4 then bits[1:0] of the counter are shown here. If the counter limit = 8 then bits[2:1] of the counter are shown. 9 OTP_LOADEDn R 1h OTP NOT Loaded Clears when OTP has loaded at least once. Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ.0h = OTP has loaded at least once; 1h = OTP has not finished loading 8 OTP_CRC_ERR R 0h OTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation. Sticky, cleared by reading register, unless condition still persist.0h = No OTP CRC fault; 1h = OTP CRC fault 7 CRC_FLT R 0h CRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame. Sticky, cleared by reading register, unless condition still persist.0h = No CRC fault; 1h = CRC fault 6 WD_FLT R 0h Watchdog Timer Fault Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No watchdog fault; 1h = Watchdog fault 5 VREF_FLT R 0h Invalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Valid VREF voltage; 1h = Invalid VREF voltage 4 ADC_AIN1_FLT R 0h ADC AIN1 Fault. Maskable fault. 0h = AIN1 ADC measurement within threshold limits 1h = AIN1 ADC measurement outside threshold limits 3 ADC_AIN0_FLT R 0h ADC AIN0 Fault. Maskable fault. 0h = AIN0 ADC measurement within threshold limits 1h = AIN0 ADC measurement outside threshold limits 2 ADC_TEMP_FLT R 0h ADC Temp Fault. Maskable fault. 0h = TEMP ADC measurement within threshold limits 1h = TEMP ADC measurement outside threshold limits 1 THERM_ERR_FLT R 0h Temperature > 130°C error. Maskable fault. OR with FORCE_FAIL.THERM_ERR_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C 0 THERM_WARN_FLT R 0h Temperature > 85°C warning. Maskable fault. OR with FORCE_FAIL.THERM_WARN_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 SD_FLT R 0h Self Diagnostic (SD) Fault0h = All self diagnostic channels are within threshold limits 1h = At least one of the self diagnostic channels has failed 12 OSC_FAIL R 0h Oscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed IRQ.0h = Oscillator started; 1h = Oscillator has failed to start 11-10 CRC_CNT R 0h CRC Fault CounterIf counter limit ≤ 4 then bits[1:0] of the counter are shown here. If the counter limit = 8 then bits[2:1] of the counter are shown. 9 OTP_LOADEDn R 1h OTP NOT Loaded Clears when OTP has loaded at least once. Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ.0h = OTP has loaded at least once; 1h = OTP has not finished loading 8 OTP_CRC_ERR R 0h OTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation. Sticky, cleared by reading register, unless condition still persist.0h = No OTP CRC fault; 1h = OTP CRC fault 7 CRC_FLT R 0h CRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame. Sticky, cleared by reading register, unless condition still persist.0h = No CRC fault; 1h = CRC fault 6 WD_FLT R 0h Watchdog Timer Fault Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No watchdog fault; 1h = Watchdog fault 5 VREF_FLT R 0h Invalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Valid VREF voltage; 1h = Invalid VREF voltage 4 ADC_AIN1_FLT R 0h ADC AIN1 Fault. Maskable fault. 0h = AIN1 ADC measurement within threshold limits 1h = AIN1 ADC measurement outside threshold limits 3 ADC_AIN0_FLT R 0h ADC AIN0 Fault. Maskable fault. 0h = AIN0 ADC measurement within threshold limits 1h = AIN0 ADC measurement outside threshold limits 2 ADC_TEMP_FLT R 0h ADC Temp Fault. Maskable fault. 0h = TEMP ADC measurement within threshold limits 1h = TEMP ADC measurement outside threshold limits 1 THERM_ERR_FLT R 0h Temperature > 130°C error. Maskable fault. OR with FORCE_FAIL.THERM_ERR_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C 0 THERM_WARN_FLT R 0h Temperature > 85°C warning. Maskable fault. OR with FORCE_FAIL.THERM_WARN_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C 15 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 15GEN_IRQR0hGeneral IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 0h = All of the unmasked bits of the GEN_STATUS register are low1h = At least one of the unmasked bits in the GEN_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 14MODEM_IRQR0hModem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 0h = All of the unmasked bits of the MODEM_STATUS register are low1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 SD_FLT R 0h Self Diagnostic (SD) Fault0h = All self diagnostic channels are within threshold limits 1h = At least one of the self diagnostic channels has failed 13SD_FLTR0hSelf Diagnostic (SD) Fault0h = All self diagnostic channels are within threshold limits 1h = At least one of the self diagnostic channels has failed 0h = All self diagnostic channels are within threshold limits1h = At least one of the self diagnostic channels has failed 12 OSC_FAIL R 0h Oscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed IRQ.0h = Oscillator started; 1h = Oscillator has failed to start 12OSC_FAILR0hOscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed IRQ.0h = Oscillator started; 1h = Oscillator has failed to start ALARM0h = Oscillator started; 1h = Oscillator has failed to start 11-10 CRC_CNT R 0h CRC Fault CounterIf counter limit ≤ 4 then bits[1:0] of the counter are shown here. If the counter limit = 8 then bits[2:1] of the counter are shown. 11-10CRC_CNTR0hCRC Fault CounterIf counter limit ≤ 4 then bits[1:0] of the counter are shown here. If the counter limit = 8 then bits[2:1] of the counter are shown. 9 OTP_LOADEDn R 1h OTP NOT Loaded Clears when OTP has loaded at least once. Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ.0h = OTP has loaded at least once; 1h = OTP has not finished loading 9OTP_LOADEDnR1hOTP NOT Loaded Clears when OTP has loaded at least once. Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ.0h = OTP has loaded at least once; 1h = OTP has not finished loading ALARM0h = OTP has loaded at least once; 1h = OTP has not finished loading 8 OTP_CRC_ERR R 0h OTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation. Sticky, cleared by reading register, unless condition still persist.0h = No OTP CRC fault; 1h = OTP CRC fault 8OTP_CRC_ERRR0hOTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation. Sticky, cleared by reading register, unless condition still persist.0h = No OTP CRC fault; 1h = OTP CRC fault 0h = No OTP CRC fault; 1h = OTP CRC fault 7 CRC_FLT R 0h CRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame. Sticky, cleared by reading register, unless condition still persist.0h = No CRC fault; 1h = CRC fault 7CRC_FLTR0hCRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame. Sticky, cleared by reading register, unless condition still persist.0h = No CRC fault; 1h = CRC fault 0h = No CRC fault; 1h = CRC fault 6 WD_FLT R 0h Watchdog Timer Fault Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No watchdog fault; 1h = Watchdog fault 6WD_FLTR0hWatchdog Timer Fault Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No watchdog fault; 1h = Watchdog fault 0h = No watchdog fault; 1h = Watchdog fault 5 VREF_FLT R 0h Invalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Valid VREF voltage; 1h = Invalid VREF voltage 5VREF_FLTR0hInvalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Valid VREF voltage; 1h = Invalid VREF voltage 0h = Valid VREF voltage; 1h = Invalid VREF voltage 4 ADC_AIN1_FLT R 0h ADC AIN1 Fault. Maskable fault. 0h = AIN1 ADC measurement within threshold limits 1h = AIN1 ADC measurement outside threshold limits 4ADC_AIN1_FLTR0hADC AIN1 Fault. Maskable fault. 0h = AIN1 ADC measurement within threshold limits 1h = AIN1 ADC measurement outside threshold limits 0h = AIN1 ADC measurement within threshold limits1h = AIN1 ADC measurement outside threshold limits 3 ADC_AIN0_FLT R 0h ADC AIN0 Fault. Maskable fault. 0h = AIN0 ADC measurement within threshold limits 1h = AIN0 ADC measurement outside threshold limits 3ADC_AIN0_FLTR0hADC AIN0 Fault. Maskable fault. 0h = AIN0 ADC measurement within threshold limits 1h = AIN0 ADC measurement outside threshold limits 0h = AIN0 ADC measurement within threshold limits1h = AIN0 ADC measurement outside threshold limits 2 ADC_TEMP_FLT R 0h ADC Temp Fault. Maskable fault. 0h = TEMP ADC measurement within threshold limits 1h = TEMP ADC measurement outside threshold limits 2ADC_TEMP_FLTR0hADC Temp Fault. Maskable fault. 0h = TEMP ADC measurement within threshold limits 1h = TEMP ADC measurement outside threshold limits 0h = TEMP ADC measurement within threshold limits1h = TEMP ADC measurement outside threshold limits 1 THERM_ERR_FLT R 0h Temperature > 130°C error. Maskable fault. OR with FORCE_FAIL.THERM_ERR_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C 1THERM_ERR_FLTR0hTemperature > 130°C error. Maskable fault. OR with FORCE_FAIL.THERM_ERR_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C 0 THERM_WARN_FLT R 0h Temperature > 85°C warning. Maskable fault. OR with FORCE_FAIL.THERM_WARN_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C 0THERM_WARN_FLTR0hTemperature > 85°C warning. Maskable fault. OR with FORCE_FAIL.THERM_WARN_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C GEN_STATUS Register (Offset = 21h) [Reset = 1180h] Return to the Register Map . GEN_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 RESERVED R 0h 12 OTP_BUSY R 1h OTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches.0h = OTP has completed loading into the device 1h = OTP is being loaded into the device 11 BIST_MODE R 0h Denotes which BIST is being run.0h = MBIST; 1h = RBIST 10 BIST_DONE R 0h BIST Completed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has not completed; 1h = BIST has completed 9 BIST_FAIL R 0h BIST Failed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has passed; 1h = BIST has failed 8 RESET R 1h Device Reset Occurred. Status only. Does not feed IRQ.Sticky, cleared by reading register, unless condition still persist. 0h = Device has not reset since last read of register 1h = Device has reset since last read of register 7 SR_BUSYn R 1h Slew Rate Not Busy. Maskable fault. 0h = DAC is slewing to the target code1h = DAC_OUT has reached the DAC_DATA. If slew rate is disabled, then this signal produces a rising edge within 3 internal clock cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can cause an unwanted fast transition on VOUT. 6 ADC_EOC R 0h ADC End of Conversion (EOC). Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No EOC since last read of register; 1h = ADC end of conversion 5 ADC_BUSY R 0h ADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true. 0h = No ADC activity; 1h = ADC is actively converting 4 PVDD_HI R 0h PVDD High. Status only. Does not feed IRQ. Set as long as condition is true. 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7 V 3 BREAK_FRAME_ERR R 0h Incorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break frame error; 1h = Break frame error 2 BREAK_PARITY_ERR R 0h Incorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break parity error; 1h = Break parity error 1 UART_FRAME_ERR R 0h Incorrect Stop Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART frame error; 1h = UART frame error 0 UART_PARITY_ERR R 0h Incorrect Parity (ODD) Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART parity error; 1h = UART parity error GEN_STATUS Register (Offset = 21h) [Reset = 1180h] GEN_STATUSReturn to the Register Map . Register Map Register Map GEN_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 RESERVED R 0h 12 OTP_BUSY R 1h OTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches.0h = OTP has completed loading into the device 1h = OTP is being loaded into the device 11 BIST_MODE R 0h Denotes which BIST is being run.0h = MBIST; 1h = RBIST 10 BIST_DONE R 0h BIST Completed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has not completed; 1h = BIST has completed 9 BIST_FAIL R 0h BIST Failed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has passed; 1h = BIST has failed 8 RESET R 1h Device Reset Occurred. Status only. Does not feed IRQ.Sticky, cleared by reading register, unless condition still persist. 0h = Device has not reset since last read of register 1h = Device has reset since last read of register 7 SR_BUSYn R 1h Slew Rate Not Busy. Maskable fault. 0h = DAC is slewing to the target code1h = DAC_OUT has reached the DAC_DATA. If slew rate is disabled, then this signal produces a rising edge within 3 internal clock cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can cause an unwanted fast transition on VOUT. 6 ADC_EOC R 0h ADC End of Conversion (EOC). Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No EOC since last read of register; 1h = ADC end of conversion 5 ADC_BUSY R 0h ADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true. 0h = No ADC activity; 1h = ADC is actively converting 4 PVDD_HI R 0h PVDD High. Status only. Does not feed IRQ. Set as long as condition is true. 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7 V 3 BREAK_FRAME_ERR R 0h Incorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break frame error; 1h = Break frame error 2 BREAK_PARITY_ERR R 0h Incorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break parity error; 1h = Break parity error 1 UART_FRAME_ERR R 0h Incorrect Stop Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART frame error; 1h = UART frame error 0 UART_PARITY_ERR R 0h Incorrect Parity (ODD) Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART parity error; 1h = UART parity error GEN_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 RESERVED R 0h 12 OTP_BUSY R 1h OTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches.0h = OTP has completed loading into the device 1h = OTP is being loaded into the device 11 BIST_MODE R 0h Denotes which BIST is being run.0h = MBIST; 1h = RBIST 10 BIST_DONE R 0h BIST Completed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has not completed; 1h = BIST has completed 9 BIST_FAIL R 0h BIST Failed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has passed; 1h = BIST has failed 8 RESET R 1h Device Reset Occurred. Status only. Does not feed IRQ.Sticky, cleared by reading register, unless condition still persist. 0h = Device has not reset since last read of register 1h = Device has reset since last read of register 7 SR_BUSYn R 1h Slew Rate Not Busy. Maskable fault. 0h = DAC is slewing to the target code1h = DAC_OUT has reached the DAC_DATA. If slew rate is disabled, then this signal produces a rising edge within 3 internal clock cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can cause an unwanted fast transition on VOUT. 6 ADC_EOC R 0h ADC End of Conversion (EOC). Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No EOC since last read of register; 1h = ADC end of conversion 5 ADC_BUSY R 0h ADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true. 0h = No ADC activity; 1h = ADC is actively converting 4 PVDD_HI R 0h PVDD High. Status only. Does not feed IRQ. Set as long as condition is true. 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7 V 3 BREAK_FRAME_ERR R 0h Incorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break frame error; 1h = Break frame error 2 BREAK_PARITY_ERR R 0h Incorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break parity error; 1h = Break parity error 1 UART_FRAME_ERR R 0h Incorrect Stop Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART frame error; 1h = UART frame error 0 UART_PARITY_ERR R 0h Incorrect Parity (ODD) Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART parity error; 1h = UART parity error Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 RESERVED R 0h 12 OTP_BUSY R 1h OTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches.0h = OTP has completed loading into the device 1h = OTP is being loaded into the device 11 BIST_MODE R 0h Denotes which BIST is being run.0h = MBIST; 1h = RBIST 10 BIST_DONE R 0h BIST Completed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has not completed; 1h = BIST has completed 9 BIST_FAIL R 0h BIST Failed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has passed; 1h = BIST has failed 8 RESET R 1h Device Reset Occurred. Status only. Does not feed IRQ.Sticky, cleared by reading register, unless condition still persist. 0h = Device has not reset since last read of register 1h = Device has reset since last read of register 7 SR_BUSYn R 1h Slew Rate Not Busy. Maskable fault. 0h = DAC is slewing to the target code1h = DAC_OUT has reached the DAC_DATA. If slew rate is disabled, then this signal produces a rising edge within 3 internal clock cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can cause an unwanted fast transition on VOUT. 6 ADC_EOC R 0h ADC End of Conversion (EOC). Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No EOC since last read of register; 1h = ADC end of conversion 5 ADC_BUSY R 0h ADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true. 0h = No ADC activity; 1h = ADC is actively converting 4 PVDD_HI R 0h PVDD High. Status only. Does not feed IRQ. Set as long as condition is true. 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7 V 3 BREAK_FRAME_ERR R 0h Incorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break frame error; 1h = Break frame error 2 BREAK_PARITY_ERR R 0h Incorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break parity error; 1h = Break parity error 1 UART_FRAME_ERR R 0h Incorrect Stop Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART frame error; 1h = UART frame error 0 UART_PARITY_ERR R 0h Incorrect Parity (ODD) Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART parity error; 1h = UART parity error 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 15ALARM_IRQR0hAlarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 0h = All of the unmasked bits of the ALARM_STATUS register are low1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 MODEM_IRQ R 0h Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 14 MODEM_IRQ MODEM_IRQR0hModem IRQ OR of all the unmasked bits in the MODEM_STATUS register.0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high 0h = All of the unmasked bits of the MODEM_STATUS register are low1h = At least one of the unmasked bits in the MODEM_STATUS register is high 13 RESERVED R 0h 13RESERVEDR0h 12 OTP_BUSY R 1h OTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches.0h = OTP has completed loading into the device 1h = OTP is being loaded into the device 12OTP_BUSYR1hOTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches.0h = OTP has completed loading into the device 1h = OTP is being loaded into the device 0h = OTP has completed loading into the device1h = OTP is being loaded into the device 11 BIST_MODE R 0h Denotes which BIST is being run.0h = MBIST; 1h = RBIST 11BIST_MODER0h Denotes which BIST is being run.0h = MBIST; 1h = RBISTDenotes which BIST is being run. 10 BIST_DONE R 0h BIST Completed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has not completed; 1h = BIST has completed 10BIST_DONER0hBIST Completed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has not completed; 1h = BIST has completed 0h = BIST has not completed; 1h = BIST has completed 9 BIST_FAIL R 0h BIST Failed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has passed; 1h = BIST has failed 9BIST_FAILR0hBIST Failed. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = BIST has passed; 1h = BIST has failed 0h = BIST has passed; 1h = BIST has failed 8 RESET R 1h Device Reset Occurred. Status only. Does not feed IRQ.Sticky, cleared by reading register, unless condition still persist. 0h = Device has not reset since last read of register 1h = Device has reset since last read of register 8RESETR1hDevice Reset Occurred. Status only. Does not feed IRQ.Sticky, cleared by reading register, unless condition still persist. 0h = Device has not reset since last read of register 1h = Device has reset since last read of register 0h = Device has not reset since last read of register1h = Device has reset since last read of register 7 SR_BUSYn R 1h Slew Rate Not Busy. Maskable fault. 0h = DAC is slewing to the target code1h = DAC_OUT has reached the DAC_DATA. If slew rate is disabled, then this signal produces a rising edge within 3 internal clock cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can cause an unwanted fast transition on VOUT. 7SR_BUSYnR1hSlew Rate Not Busy. Maskable fault. 0h = DAC is slewing to the target code1h = DAC_OUT has reached the DAC_DATA. If slew rate is disabled, then this signal produces a rising edge within 3 internal clock cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can cause an unwanted fast transition on VOUT. 6 ADC_EOC R 0h ADC End of Conversion (EOC). Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No EOC since last read of register; 1h = ADC end of conversion 6ADC_EOCR0hADC End of Conversion (EOC). Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = No EOC since last read of register; 1h = ADC end of conversion 0h = No EOC since last read of register; 1h = ADC end of conversion 5 ADC_BUSY R 0h ADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true. 0h = No ADC activity; 1h = ADC is actively converting 5ADC_BUSYR0hADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true. 0h = No ADC activity; 1h = ADC is actively converting 0h = No ADC activity; 1h = ADC is actively converting 4 PVDD_HI R 0h PVDD High. Status only. Does not feed IRQ. Set as long as condition is true. 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7 V 4PVDD_HIR0hPVDD High. Status only. Does not feed IRQ. Set as long as condition is true. 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7 V 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7 V 3 BREAK_FRAME_ERR R 0h Incorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break frame error; 1h = Break frame error 3BREAK_FRAME_ERRR0hIncorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break frame error; 1h = Break frame error 0h = No break frame error; 1h = Break frame error 2 BREAK_PARITY_ERR R 0h Incorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break parity error; 1h = Break parity error 2BREAK_PARITY_ERRR0hIncorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break parity error; 1h = Break parity error 0h = No break parity error; 1h = Break parity error 1 UART_FRAME_ERR R 0h Incorrect Stop Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART frame error; 1h = UART frame error 1UART_FRAME_ERRR0hIncorrect Stop Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART frame error; 1h = UART frame error 0h = No UART frame error; 1h = UART frame error 0 UART_PARITY_ERR R 0h Incorrect Parity (ODD) Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART parity error; 1h = UART parity error 0UART_PARITY_ERRR0hIncorrect Parity (ODD) Bit During UART Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART parity error; 1h = UART parity error 0h = No UART parity error; 1h = UART parity error MODEM_STATUS Register (Offset = 22h) [Reset = 009Ah] Return to the Register Map . MODEM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 13 RESERVED R 0h 12 GAP_ERR R 0h HART Gap Error. Maskable fault. Applies to RX_IN/RX_INF. Too much time (11 bit times) between HART characters. Sticky, cleared by reading register, unless condition still persist. Fatal Fault.0h = No HART gap error; 1h = HART gap error 11 FRAME_ERR R 0h Incorrect Stop Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. Fatal Fault. 0h = No HART frame error; 1h = HART frame error 10 PARITY_ERR R 0h Incorrect Parity (ODD) Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. 0h = No HART parity error; 1h = HART parity error 9 FIFO_H2U_LEVEL_FLAG R 0h FIFO HART-to-µC Level Flag. Maskable fault. If the level of the FIFO_H2U is full, then the level flag is not asserted, but the full flag is, so no information is lost.0h = FIFO_H2U level ≤ {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 1h = FIFO_H2U level > {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 8 FIFO_H2U_FULL_FLAG R 0h FIFO HART-to-µC Full Flag. Maskable fault. 0h = FIFO_H2U is not full; 1h = FIFO_H2U is full 7 FIFO_H2U_EMPTY_FLAG R 1h FIFO HART-to-µC Empty Flag. Maskable fault. 0h = FIFO_H2U is not empty; 1h = FIFO_H2U is empty 6 FIFO_U2H_LEVEL_FLAG R 0h FIFO µC-to-HART Level Flag. Maskable fault. FIFO_U2H < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0}. When the FIFO_U2H is empty, this flag is set unless FIFO_CFG.U2H_LEVEL_SET = 0. This flag and the empty flag can be set at the same time.0h = FIFO_U2H level ≥ {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 1h = FIFO_U2H level < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 5 FIFO_U2H_FULL_FLAG R 0h FIFO µC-to-HART Full Flag. Maskable fault. 0h = FIFO_U2H is not full; 1h = FIFO_U2H is full 4 FIFO_U2H_EMPTY_FLAG R 1h FIFO µC-to-HART Empty Flag. Maskable fault. 0h = FIFO_U2H is not empty; 1h = FIFO_U2H is empty 3 CD_DEASSERT R 1h Carrier Detect Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is asserted; 1h = Carrier detect is deasserted 2 CD_ASSERT R 0h Carrier Detect Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is deasserted; 1h = Carrier detect is asserted 1 CTS_DEASSERT R 1h Clear To Send Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is asserted; 1h = Clear to send is deasserted 0 CTS_ASSERT R 0h Clear To Send Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is deasserted; 1h = Clear to send is asserted MODEM_STATUS Register (Offset = 22h) [Reset = 009Ah] MODEM_STATUSReturn to the Register Map . Register Map Register Map MODEM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 13 RESERVED R 0h 12 GAP_ERR R 0h HART Gap Error. Maskable fault. Applies to RX_IN/RX_INF. Too much time (11 bit times) between HART characters. Sticky, cleared by reading register, unless condition still persist. Fatal Fault.0h = No HART gap error; 1h = HART gap error 11 FRAME_ERR R 0h Incorrect Stop Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. Fatal Fault. 0h = No HART frame error; 1h = HART frame error 10 PARITY_ERR R 0h Incorrect Parity (ODD) Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. 0h = No HART parity error; 1h = HART parity error 9 FIFO_H2U_LEVEL_FLAG R 0h FIFO HART-to-µC Level Flag. Maskable fault. If the level of the FIFO_H2U is full, then the level flag is not asserted, but the full flag is, so no information is lost.0h = FIFO_H2U level ≤ {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 1h = FIFO_H2U level > {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 8 FIFO_H2U_FULL_FLAG R 0h FIFO HART-to-µC Full Flag. Maskable fault. 0h = FIFO_H2U is not full; 1h = FIFO_H2U is full 7 FIFO_H2U_EMPTY_FLAG R 1h FIFO HART-to-µC Empty Flag. Maskable fault. 0h = FIFO_H2U is not empty; 1h = FIFO_H2U is empty 6 FIFO_U2H_LEVEL_FLAG R 0h FIFO µC-to-HART Level Flag. Maskable fault. FIFO_U2H < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0}. When the FIFO_U2H is empty, this flag is set unless FIFO_CFG.U2H_LEVEL_SET = 0. This flag and the empty flag can be set at the same time.0h = FIFO_U2H level ≥ {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 1h = FIFO_U2H level < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 5 FIFO_U2H_FULL_FLAG R 0h FIFO µC-to-HART Full Flag. Maskable fault. 0h = FIFO_U2H is not full; 1h = FIFO_U2H is full 4 FIFO_U2H_EMPTY_FLAG R 1h FIFO µC-to-HART Empty Flag. Maskable fault. 0h = FIFO_U2H is not empty; 1h = FIFO_U2H is empty 3 CD_DEASSERT R 1h Carrier Detect Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is asserted; 1h = Carrier detect is deasserted 2 CD_ASSERT R 0h Carrier Detect Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is deasserted; 1h = Carrier detect is asserted 1 CTS_DEASSERT R 1h Clear To Send Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is asserted; 1h = Clear to send is deasserted 0 CTS_ASSERT R 0h Clear To Send Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is deasserted; 1h = Clear to send is asserted MODEM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 13 RESERVED R 0h 12 GAP_ERR R 0h HART Gap Error. Maskable fault. Applies to RX_IN/RX_INF. Too much time (11 bit times) between HART characters. Sticky, cleared by reading register, unless condition still persist. Fatal Fault.0h = No HART gap error; 1h = HART gap error 11 FRAME_ERR R 0h Incorrect Stop Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. Fatal Fault. 0h = No HART frame error; 1h = HART frame error 10 PARITY_ERR R 0h Incorrect Parity (ODD) Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. 0h = No HART parity error; 1h = HART parity error 9 FIFO_H2U_LEVEL_FLAG R 0h FIFO HART-to-µC Level Flag. Maskable fault. If the level of the FIFO_H2U is full, then the level flag is not asserted, but the full flag is, so no information is lost.0h = FIFO_H2U level ≤ {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 1h = FIFO_H2U level > {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 8 FIFO_H2U_FULL_FLAG R 0h FIFO HART-to-µC Full Flag. Maskable fault. 0h = FIFO_H2U is not full; 1h = FIFO_H2U is full 7 FIFO_H2U_EMPTY_FLAG R 1h FIFO HART-to-µC Empty Flag. Maskable fault. 0h = FIFO_H2U is not empty; 1h = FIFO_H2U is empty 6 FIFO_U2H_LEVEL_FLAG R 0h FIFO µC-to-HART Level Flag. Maskable fault. FIFO_U2H < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0}. When the FIFO_U2H is empty, this flag is set unless FIFO_CFG.U2H_LEVEL_SET = 0. This flag and the empty flag can be set at the same time.0h = FIFO_U2H level ≥ {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 1h = FIFO_U2H level < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 5 FIFO_U2H_FULL_FLAG R 0h FIFO µC-to-HART Full Flag. Maskable fault. 0h = FIFO_U2H is not full; 1h = FIFO_U2H is full 4 FIFO_U2H_EMPTY_FLAG R 1h FIFO µC-to-HART Empty Flag. Maskable fault. 0h = FIFO_U2H is not empty; 1h = FIFO_U2H is empty 3 CD_DEASSERT R 1h Carrier Detect Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is asserted; 1h = Carrier detect is deasserted 2 CD_ASSERT R 0h Carrier Detect Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is deasserted; 1h = Carrier detect is asserted 1 CTS_DEASSERT R 1h Clear To Send Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is asserted; 1h = Clear to send is deasserted 0 CTS_ASSERT R 0h Clear To Send Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is deasserted; 1h = Clear to send is asserted Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 13 RESERVED R 0h 12 GAP_ERR R 0h HART Gap Error. Maskable fault. Applies to RX_IN/RX_INF. Too much time (11 bit times) between HART characters. Sticky, cleared by reading register, unless condition still persist. Fatal Fault.0h = No HART gap error; 1h = HART gap error 11 FRAME_ERR R 0h Incorrect Stop Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. Fatal Fault. 0h = No HART frame error; 1h = HART frame error 10 PARITY_ERR R 0h Incorrect Parity (ODD) Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. 0h = No HART parity error; 1h = HART parity error 9 FIFO_H2U_LEVEL_FLAG R 0h FIFO HART-to-µC Level Flag. Maskable fault. If the level of the FIFO_H2U is full, then the level flag is not asserted, but the full flag is, so no information is lost.0h = FIFO_H2U level ≤ {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 1h = FIFO_H2U level > {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 8 FIFO_H2U_FULL_FLAG R 0h FIFO HART-to-µC Full Flag. Maskable fault. 0h = FIFO_H2U is not full; 1h = FIFO_H2U is full 7 FIFO_H2U_EMPTY_FLAG R 1h FIFO HART-to-µC Empty Flag. Maskable fault. 0h = FIFO_H2U is not empty; 1h = FIFO_H2U is empty 6 FIFO_U2H_LEVEL_FLAG R 0h FIFO µC-to-HART Level Flag. Maskable fault. FIFO_U2H < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0}. When the FIFO_U2H is empty, this flag is set unless FIFO_CFG.U2H_LEVEL_SET = 0. This flag and the empty flag can be set at the same time.0h = FIFO_U2H level ≥ {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 1h = FIFO_U2H level < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 5 FIFO_U2H_FULL_FLAG R 0h FIFO µC-to-HART Full Flag. Maskable fault. 0h = FIFO_U2H is not full; 1h = FIFO_U2H is full 4 FIFO_U2H_EMPTY_FLAG R 1h FIFO µC-to-HART Empty Flag. Maskable fault. 0h = FIFO_U2H is not empty; 1h = FIFO_U2H is empty 3 CD_DEASSERT R 1h Carrier Detect Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is asserted; 1h = Carrier detect is deasserted 2 CD_ASSERT R 0h Carrier Detect Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is deasserted; 1h = Carrier detect is asserted 1 CTS_DEASSERT R 1h Clear To Send Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is asserted; 1h = Clear to send is deasserted 0 CTS_ASSERT R 0h Clear To Send Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is deasserted; 1h = Clear to send is asserted 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 15ALARM_IRQR0hAlarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 0h = All of the unmasked bits of the ALARM_STATUS register are low1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 14GEN_IRQR0hGeneral IRQ OR of all the unmasked bits in the GEN_STATUS register.0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high 0h = All of the unmasked bits of the GEN_STATUS register are low1h = At least one of the unmasked bits in the GEN_STATUS register is high 13 RESERVED R 0h 13RESERVEDR0h 12 GAP_ERR R 0h HART Gap Error. Maskable fault. Applies to RX_IN/RX_INF. Too much time (11 bit times) between HART characters. Sticky, cleared by reading register, unless condition still persist. Fatal Fault.0h = No HART gap error; 1h = HART gap error 12GAP_ERRR0hHART Gap Error. Maskable fault. Applies to RX_IN/RX_INF. Too much time (11 bit times) between HART characters. Sticky, cleared by reading register, unless condition still persist. Fatal Fault.0h = No HART gap error; 1h = HART gap error 0h = No HART gap error; 1h = HART gap error 11 FRAME_ERR R 0h Incorrect Stop Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. Fatal Fault. 0h = No HART frame error; 1h = HART frame error 11FRAME_ERRR0hIncorrect Stop Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. Fatal Fault. 0h = No HART frame error; 1h = HART frame error 0h = No HART frame error; 1h = HART frame error 10 PARITY_ERR R 0h Incorrect Parity (ODD) Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. 0h = No HART parity error; 1h = HART parity error 10PARITY_ERRR0hIncorrect Parity (ODD) Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. 0h = No HART parity error; 1h = HART parity error 0h = No HART parity error; 1h = HART parity error 9 FIFO_H2U_LEVEL_FLAG R 0h FIFO HART-to-µC Level Flag. Maskable fault. If the level of the FIFO_H2U is full, then the level flag is not asserted, but the full flag is, so no information is lost.0h = FIFO_H2U level ≤ {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 1h = FIFO_H2U level > {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 9FIFO_H2U_LEVEL_FLAGR0hFIFO HART-to-µC Level Flag. Maskable fault. If the level of the FIFO_H2U is full, then the level flag is not asserted, but the full flag is, so no information is lost.0h = FIFO_H2U level ≤ {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 1h = FIFO_H2U level > {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 0h = FIFO_H2U level ≤ {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1}1h = FIFO_H2U level > {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 8 FIFO_H2U_FULL_FLAG R 0h FIFO HART-to-µC Full Flag. Maskable fault. 0h = FIFO_H2U is not full; 1h = FIFO_H2U is full 8FIFO_H2U_FULL_FLAGR0hFIFO HART-to-µC Full Flag. Maskable fault. 0h = FIFO_H2U is not full; 1h = FIFO_H2U is full 0h = FIFO_H2U is not full; 1h = FIFO_H2U is full 7 FIFO_H2U_EMPTY_FLAG R 1h FIFO HART-to-µC Empty Flag. Maskable fault. 0h = FIFO_H2U is not empty; 1h = FIFO_H2U is empty 7FIFO_H2U_EMPTY_FLAGR1hFIFO HART-to-µC Empty Flag. Maskable fault. 0h = FIFO_H2U is not empty; 1h = FIFO_H2U is empty 0h = FIFO_H2U is not empty; 1h = FIFO_H2U is empty 6 FIFO_U2H_LEVEL_FLAG R 0h FIFO µC-to-HART Level Flag. Maskable fault. FIFO_U2H < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0}. When the FIFO_U2H is empty, this flag is set unless FIFO_CFG.U2H_LEVEL_SET = 0. This flag and the empty flag can be set at the same time.0h = FIFO_U2H level ≥ {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 1h = FIFO_U2H level < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 6FIFO_U2H_LEVEL_FLAGR0hFIFO µC-to-HART Level Flag. Maskable fault. FIFO_U2H < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0}. When the FIFO_U2H is empty, this flag is set unless FIFO_CFG.U2H_LEVEL_SET = 0. This flag and the empty flag can be set at the same time.0h = FIFO_U2H level ≥ {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 1h = FIFO_U2H level < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 0h = FIFO_U2H level ≥ {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0}1h = FIFO_U2H level < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 5 FIFO_U2H_FULL_FLAG R 0h FIFO µC-to-HART Full Flag. Maskable fault. 0h = FIFO_U2H is not full; 1h = FIFO_U2H is full 5FIFO_U2H_FULL_FLAGR0hFIFO µC-to-HART Full Flag. Maskable fault. 0h = FIFO_U2H is not full; 1h = FIFO_U2H is full 0h = FIFO_U2H is not full; 1h = FIFO_U2H is full 4 FIFO_U2H_EMPTY_FLAG R 1h FIFO µC-to-HART Empty Flag. Maskable fault. 0h = FIFO_U2H is not empty; 1h = FIFO_U2H is empty 4FIFO_U2H_EMPTY_FLAGR1hFIFO µC-to-HART Empty Flag. Maskable fault. 0h = FIFO_U2H is not empty; 1h = FIFO_U2H is empty 0h = FIFO_U2H is not empty; 1h = FIFO_U2H is empty 3 CD_DEASSERT R 1h Carrier Detect Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is asserted; 1h = Carrier detect is deasserted 3CD_DEASSERTR1hCarrier Detect Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is asserted; 1h = Carrier detect is deasserted 0h = Carrier detect is asserted; 1h = Carrier detect is deasserted 2 CD_ASSERT R 0h Carrier Detect Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is deasserted; 1h = Carrier detect is asserted 2CD_ASSERTR0hCarrier Detect Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Carrier detect is deasserted; 1h = Carrier detect is asserted 0h = Carrier detect is deasserted; 1h = Carrier detect is asserted 1 CTS_DEASSERT R 1h Clear To Send Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is asserted; 1h = Clear to send is deasserted 1CTS_DEASSERTR1hClear To Send Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is asserted; 1h = Clear to send is deasserted 0h = Clear to send is asserted; 1h = Clear to send is deasserted 0 CTS_ASSERT R 0h Clear To Send Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is deasserted; 1h = Clear to send is asserted 0CTS_ASSERTR0hClear To Send Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist.0h = Clear to send is deasserted; 1h = Clear to send is asserted 0h = Clear to send is deasserted; 1h = Clear to send is asserted ADC_FLAGS Register (Offset = 23h) [Reset = 0000h] Return to the Register Map .The limits for Self Diagnostic (SD) Alarm ADC Thresholds are shown in . ADC_FLAGS Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h 8 SD4_FAIL R 0h SD4 (VOUT) Limit Fail 7 SD3_FAIL R 0h SD3 (ZTAT) Limit Fail 6 SD2_FAIL R 0h SD2 (VDD) Limit Fail 5 SD1_FAIL R 0h SD1 (PVDD) Limit Fail 4 SD0_FAIL R 0h SD0 (VREF) Limit Fail 3 TEMP_FAIL R 0h TEMP Limit Fail 2 AIN1_FAIL R 0h AIN1 Limit Fail 1 AIN0_FAIL R 0h AIN0 Limit Fail 0 RESERVED R 0h ADC_FLAGS Register (Offset = 23h) [Reset = 0000h] ADC_FLAGSReturn to the Register Map . Register Map Register Map ADC_FLAGS Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h 8 SD4_FAIL R 0h SD4 (VOUT) Limit Fail 7 SD3_FAIL R 0h SD3 (ZTAT) Limit Fail 6 SD2_FAIL R 0h SD2 (VDD) Limit Fail 5 SD1_FAIL R 0h SD1 (PVDD) Limit Fail 4 SD0_FAIL R 0h SD0 (VREF) Limit Fail 3 TEMP_FAIL R 0h TEMP Limit Fail 2 AIN1_FAIL R 0h AIN1 Limit Fail 1 AIN0_FAIL R 0h AIN0 Limit Fail 0 RESERVED R 0h ADC_FLAGS Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h 8 SD4_FAIL R 0h SD4 (VOUT) Limit Fail 7 SD3_FAIL R 0h SD3 (ZTAT) Limit Fail 6 SD2_FAIL R 0h SD2 (VDD) Limit Fail 5 SD1_FAIL R 0h SD1 (PVDD) Limit Fail 4 SD0_FAIL R 0h SD0 (VREF) Limit Fail 3 TEMP_FAIL R 0h TEMP Limit Fail 2 AIN1_FAIL R 0h AIN1 Limit Fail 1 AIN0_FAIL R 0h AIN0 Limit Fail 0 RESERVED R 0h Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-9 RESERVED R 0h 8 SD4_FAIL R 0h SD4 (VOUT) Limit Fail 7 SD3_FAIL R 0h SD3 (ZTAT) Limit Fail 6 SD2_FAIL R 0h SD2 (VDD) Limit Fail 5 SD1_FAIL R 0h SD1 (PVDD) Limit Fail 4 SD0_FAIL R 0h SD0 (VREF) Limit Fail 3 TEMP_FAIL R 0h TEMP Limit Fail 2 AIN1_FAIL R 0h AIN1 Limit Fail 1 AIN0_FAIL R 0h AIN0 Limit Fail 0 RESERVED R 0h 15-9 RESERVED R 0h 15-9RESERVEDR0h 8 SD4_FAIL R 0h SD4 (VOUT) Limit Fail 8SD4_FAILR0hSD4 (VOUT) Limit Fail 7 SD3_FAIL R 0h SD3 (ZTAT) Limit Fail 7SD3_FAILR0hSD3 (ZTAT) Limit Fail 6 SD2_FAIL R 0h SD2 (VDD) Limit Fail 6SD2_FAILR0hSD2 (VDD) Limit Fail 5 SD1_FAIL R 0h SD1 (PVDD) Limit Fail 5SD1_FAILR0hSD1 (PVDD) Limit Fail 4 SD0_FAIL R 0h SD0 (VREF) Limit Fail 4SD0_FAILR0hSD0 (VREF) Limit Fail 3 TEMP_FAIL R 0h TEMP Limit Fail 3TEMP_FAILR0hTEMP Limit Fail 2 AIN1_FAIL R 0h AIN1 Limit Fail 2AIN1_FAILR0hAIN1 Limit Fail 1 AIN0_FAIL R 0h AIN0 Limit Fail 1AIN0_FAILR0hAIN0 Limit Fail 0 RESERVED R 0h 0RESERVEDR0h ADC_AIN0 Register (Offset = 24h) [Reset = 0000h] Return to the Register Map . ADC_AIN0 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN0 ADC_AIN0 Register (Offset = 24h) [Reset = 0000h] ADC_AIN0Return to the Register Map . Register Map Register Map ADC_AIN0 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN0 ADC_AIN0 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN0 Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN0 15-12 RESERVED R 0h 15-12RESERVEDR0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN0 11-0DATAR0hConverted Value of Voltage on Pin AIN0 ADC_AIN1 Register (Offset = 25h) [Reset = 0000h] Return to the Register Map . ADC_AIN1 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN1 ADC_AIN1 Register (Offset = 25h) [Reset = 0000h] ADC_AIN1Return to the Register Map . Register Map Register Map ADC_AIN1 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN1 ADC_AIN1 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN1 Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN1 15-12 RESERVED R 0h 15-12RESERVEDR0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN1 11-0DATAR0hConverted Value of Voltage on Pin AIN1 ADC_TEMP Register (Offset = 26h) [Reset = 0000h] Return to the Register Map . ADC_TEMP Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Temperature ADC_TEMP Register (Offset = 26h) [Reset = 0000h] ADC_TEMPReturn to the Register Map . Register Map Register Map ADC_TEMP Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Temperature ADC_TEMP Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Temperature Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Temperature 15-12 RESERVED R 0h 15-12RESERVEDR0h 11-0 DATA R 0h Converted Value of Temperature 11-0DATAR0hConverted Value of Temperature ADC_SD_MUX Register (Offset = 27h) [Reset = 0000h] Return to the Register Map . ADC_SD_MUX Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Self-Diagnostic (SD) MUX Input ADC_SD_MUX Register (Offset = 27h) [Reset = 0000h] ADC_SD_MUXReturn to the Register Map . Register Map Register Map ADC_SD_MUX Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Self-Diagnostic (SD) MUX Input ADC_SD_MUX Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Self-Diagnostic (SD) MUX Input Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Self-Diagnostic (SD) MUX Input 15-12 RESERVED R 0h 15-12RESERVEDR0h 11-0 DATA R 0h Converted Value of Voltage on Self-Diagnostic (SD) MUX Input 11-0DATAR0hConverted Value of Voltage on Self-Diagnostic (SD) MUX Input ADC_OFFSET Register (Offset = 28h) [Reset = 0000h] Return to the Register Map . ADC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Comparator Offset This value reports the offset measured in the device, and can be used to adjust each conversion value. If ADC_BYP.OFST_BYP_EN is set, then the value in ADC_BYP.DATA is used as the offset. This value is not affected by ADC_BYP. ADC_OFFSET Register (Offset = 28h) [Reset = 0000h] ADC_OFFSETReturn to the Register Map . Register Map Register Map ADC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Comparator Offset This value reports the offset measured in the device, and can be used to adjust each conversion value. If ADC_BYP.OFST_BYP_EN is set, then the value in ADC_BYP.DATA is used as the offset. This value is not affected by ADC_BYP. ADC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Comparator Offset This value reports the offset measured in the device, and can be used to adjust each conversion value. If ADC_BYP.OFST_BYP_EN is set, then the value in ADC_BYP.DATA is used as the offset. This value is not affected by ADC_BYP. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Comparator Offset This value reports the offset measured in the device, and can be used to adjust each conversion value. If ADC_BYP.OFST_BYP_EN is set, then the value in ADC_BYP.DATA is used as the offset. This value is not affected by ADC_BYP. 15-12 RESERVED R 0h 15-12RESERVEDR0h 11-0 DATA R 0h ADC Comparator Offset This value reports the offset measured in the device, and can be used to adjust each conversion value. If ADC_BYP.OFST_BYP_EN is set, then the value in ADC_BYP.DATA is used as the offset. This value is not affected by ADC_BYP. 11-0DATAR0hADC Comparator Offset This value reports the offset measured in the device, and can be used to adjust each conversion value. If ADC_BYP.OFST_BYP_EN is set, then the value in ADC_BYP.DATA is used as the offset. This value is not affected by ADC_BYP. FIFO_H2U_RD Register (Offset = 2Ah) [Reset = 0200h] Return to the Register Map . FIFO_H2U_RD Register Field Descriptions Bit Field Type Reset Description 15-12 LEVEL R 0h LevelCurrent Level of FIFO_H2U, bits [4:1] represented as Level[3:0]. Pre-dequeue. 11 LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO_H2U Level > {Level,1b1}. Pre-dequeue.0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 FULL_FLAG R 0h HART-to-µC FIFO Full Flag. Pre-dequeue. 0h = FIFO_H2U is not full, pre-dequeue 1h = FIFO_H2U is full, pre-dequeue 9 EMPTY_FLAG R 1h HART-to-µC FIFO Empty Flag. Pre-dequeue. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 PARITY R 0h Parity Bit (ODD)Parity bit received with data on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. 7-0 DATA R 0h Data8-bit data received on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. FIFO_H2U_RD Register (Offset = 2Ah) [Reset = 0200h] FIFO_H2U_RDReturn to the Register Map . Register Map Register Map FIFO_H2U_RD Register Field Descriptions Bit Field Type Reset Description 15-12 LEVEL R 0h LevelCurrent Level of FIFO_H2U, bits [4:1] represented as Level[3:0]. Pre-dequeue. 11 LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO_H2U Level > {Level,1b1}. Pre-dequeue.0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 FULL_FLAG R 0h HART-to-µC FIFO Full Flag. Pre-dequeue. 0h = FIFO_H2U is not full, pre-dequeue 1h = FIFO_H2U is full, pre-dequeue 9 EMPTY_FLAG R 1h HART-to-µC FIFO Empty Flag. Pre-dequeue. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 PARITY R 0h Parity Bit (ODD)Parity bit received with data on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. 7-0 DATA R 0h Data8-bit data received on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. FIFO_H2U_RD Register Field Descriptions Bit Field Type Reset Description 15-12 LEVEL R 0h LevelCurrent Level of FIFO_H2U, bits [4:1] represented as Level[3:0]. Pre-dequeue. 11 LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO_H2U Level > {Level,1b1}. Pre-dequeue.0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 FULL_FLAG R 0h HART-to-µC FIFO Full Flag. Pre-dequeue. 0h = FIFO_H2U is not full, pre-dequeue 1h = FIFO_H2U is full, pre-dequeue 9 EMPTY_FLAG R 1h HART-to-µC FIFO Empty Flag. Pre-dequeue. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 PARITY R 0h Parity Bit (ODD)Parity bit received with data on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. 7-0 DATA R 0h Data8-bit data received on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-12 LEVEL R 0h LevelCurrent Level of FIFO_H2U, bits [4:1] represented as Level[3:0]. Pre-dequeue. 11 LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO_H2U Level > {Level,1b1}. Pre-dequeue.0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 FULL_FLAG R 0h HART-to-µC FIFO Full Flag. Pre-dequeue. 0h = FIFO_H2U is not full, pre-dequeue 1h = FIFO_H2U is full, pre-dequeue 9 EMPTY_FLAG R 1h HART-to-µC FIFO Empty Flag. Pre-dequeue. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 PARITY R 0h Parity Bit (ODD)Parity bit received with data on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. 7-0 DATA R 0h Data8-bit data received on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. 15-12 LEVEL R 0h LevelCurrent Level of FIFO_H2U, bits [4:1] represented as Level[3:0]. Pre-dequeue. 15-12LEVELR0hLevelCurrent Level of FIFO_H2U, bits [4:1] represented as Level[3:0]. Pre-dequeue. 11 LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO_H2U Level > {Level,1b1}. Pre-dequeue.0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 11LEVEL_FLAGR0hHART-to-µC FIFO Level FlagSet when FIFO_H2U Level > {Level,1b1}. Pre-dequeue.0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 0h = FIFO_H2U level ≤ {Level, 1b1}1h = FIFO_H2U level > {Level, 1b1} 10 FULL_FLAG R 0h HART-to-µC FIFO Full Flag. Pre-dequeue. 0h = FIFO_H2U is not full, pre-dequeue 1h = FIFO_H2U is full, pre-dequeue 10FULL_FLAGR0hHART-to-µC FIFO Full Flag. Pre-dequeue. 0h = FIFO_H2U is not full, pre-dequeue 1h = FIFO_H2U is full, pre-dequeue 0h = FIFO_H2U is not full, pre-dequeue1h = FIFO_H2U is full, pre-dequeue 9 EMPTY_FLAG R 1h HART-to-µC FIFO Empty Flag. Pre-dequeue. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 9EMPTY_FLAGR1hHART-to-µC FIFO Empty Flag. Pre-dequeue. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 0h = FIFO_H2U is not empty1h = FIFO_H2U is empty 8 PARITY R 0h Parity Bit (ODD)Parity bit received with data on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. 8PARITYR0hParity Bit (ODD)Parity bit received with data on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. 7-0 DATA R 0h Data8-bit data received on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. 7-0DATAR0hData8-bit data received on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO. FIFO_STATUS Register (Offset = 2Bh) [Reset = 0202h] Return to the Register Map . The FIFO_STATUS register is provided to allow the user to view the state of both FIFOs without enqueuing or dequeuing data in the FIFO. This also allows the flags to be viewed without disturbing other status bits in the MODEM_STATUS register. This register is provided to enable users to check the FIFO status register without disturbing other functions within the device. FIFO_STATUS Register Field Descriptions Bit Field Type Reset Description 15-12 H2U_LEVEL R 0h HART-to-µC FIFO LevelCurrent level of FIFO_H2U, right shifted 1 bit (>>1) so only even counts are represented. 11 H2U_LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO Level > {Level,1b1}. 0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 H2U_FULL_FLAG R 0h HART-to-µC FIFO Full FlagSet when FIFO is full. 0h = FIFO_H2U is not full 1h = FIFO_H2U is full 9 H2U_EMPTY_FLAG R 1h HART-to-µC Empty FlagSet when FIFO is empty. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 RESERVED R 0h 7-4 U2H_LEVEL R 0h µC-to-HART FIFO LevelCurrent level of FIFO_U2H, right shifted 1 bit (>>1) so only even counts are represented 3 U2H_LEVEL_FLAG R 0h µC-to-HART FIFO Level FlagSet when FIFO_U2H Level < {Level,1b0}. 0h = FIFO_U2H level ≥ {Level, 1b0} 1h = FIFO_U2H level < {Level, 1b0} 2 U2H_FULL_FLAG R 0h µC-to-HART Full FlagSet when FIFO_U2H is full. 0h = FIFO_U2H is not full 1h = FIFO_U2H is full 1 U2H_EMPTY_FLAG R 1h µC-to-HART Empty FlagSet when FIFO_U2H is empty. 0h = FIFO_U2H is not empty 1h = FIFO_U2H is empty 0 RESERVED R 0h FIFO_STATUS Register (Offset = 2Bh) [Reset = 0202h] FIFO_STATUSReturn to the Register Map . Register Map Register MapThe FIFO_STATUS register is provided to allow the user to view the state of both FIFOs without enqueuing or dequeuing data in the FIFO. This also allows the flags to be viewed without disturbing other status bits in the MODEM_STATUS register. This register is provided to enable users to check the FIFO status register without disturbing other functions within the device. FIFO_STATUS Register Field Descriptions Bit Field Type Reset Description 15-12 H2U_LEVEL R 0h HART-to-µC FIFO LevelCurrent level of FIFO_H2U, right shifted 1 bit (>>1) so only even counts are represented. 11 H2U_LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO Level > {Level,1b1}. 0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 H2U_FULL_FLAG R 0h HART-to-µC FIFO Full FlagSet when FIFO is full. 0h = FIFO_H2U is not full 1h = FIFO_H2U is full 9 H2U_EMPTY_FLAG R 1h HART-to-µC Empty FlagSet when FIFO is empty. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 RESERVED R 0h 7-4 U2H_LEVEL R 0h µC-to-HART FIFO LevelCurrent level of FIFO_U2H, right shifted 1 bit (>>1) so only even counts are represented 3 U2H_LEVEL_FLAG R 0h µC-to-HART FIFO Level FlagSet when FIFO_U2H Level < {Level,1b0}. 0h = FIFO_U2H level ≥ {Level, 1b0} 1h = FIFO_U2H level < {Level, 1b0} 2 U2H_FULL_FLAG R 0h µC-to-HART Full FlagSet when FIFO_U2H is full. 0h = FIFO_U2H is not full 1h = FIFO_U2H is full 1 U2H_EMPTY_FLAG R 1h µC-to-HART Empty FlagSet when FIFO_U2H is empty. 0h = FIFO_U2H is not empty 1h = FIFO_U2H is empty 0 RESERVED R 0h FIFO_STATUS Register Field Descriptions Bit Field Type Reset Description 15-12 H2U_LEVEL R 0h HART-to-µC FIFO LevelCurrent level of FIFO_H2U, right shifted 1 bit (>>1) so only even counts are represented. 11 H2U_LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO Level > {Level,1b1}. 0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 H2U_FULL_FLAG R 0h HART-to-µC FIFO Full FlagSet when FIFO is full. 0h = FIFO_H2U is not full 1h = FIFO_H2U is full 9 H2U_EMPTY_FLAG R 1h HART-to-µC Empty FlagSet when FIFO is empty. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 RESERVED R 0h 7-4 U2H_LEVEL R 0h µC-to-HART FIFO LevelCurrent level of FIFO_U2H, right shifted 1 bit (>>1) so only even counts are represented 3 U2H_LEVEL_FLAG R 0h µC-to-HART FIFO Level FlagSet when FIFO_U2H Level < {Level,1b0}. 0h = FIFO_U2H level ≥ {Level, 1b0} 1h = FIFO_U2H level < {Level, 1b0} 2 U2H_FULL_FLAG R 0h µC-to-HART Full FlagSet when FIFO_U2H is full. 0h = FIFO_U2H is not full 1h = FIFO_U2H is full 1 U2H_EMPTY_FLAG R 1h µC-to-HART Empty FlagSet when FIFO_U2H is empty. 0h = FIFO_U2H is not empty 1h = FIFO_U2H is empty 0 RESERVED R 0h Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-12 H2U_LEVEL R 0h HART-to-µC FIFO LevelCurrent level of FIFO_H2U, right shifted 1 bit (>>1) so only even counts are represented. 11 H2U_LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO Level > {Level,1b1}. 0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 10 H2U_FULL_FLAG R 0h HART-to-µC FIFO Full FlagSet when FIFO is full. 0h = FIFO_H2U is not full 1h = FIFO_H2U is full 9 H2U_EMPTY_FLAG R 1h HART-to-µC Empty FlagSet when FIFO is empty. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 8 RESERVED R 0h 7-4 U2H_LEVEL R 0h µC-to-HART FIFO LevelCurrent level of FIFO_U2H, right shifted 1 bit (>>1) so only even counts are represented 3 U2H_LEVEL_FLAG R 0h µC-to-HART FIFO Level FlagSet when FIFO_U2H Level < {Level,1b0}. 0h = FIFO_U2H level ≥ {Level, 1b0} 1h = FIFO_U2H level < {Level, 1b0} 2 U2H_FULL_FLAG R 0h µC-to-HART Full FlagSet when FIFO_U2H is full. 0h = FIFO_U2H is not full 1h = FIFO_U2H is full 1 U2H_EMPTY_FLAG R 1h µC-to-HART Empty FlagSet when FIFO_U2H is empty. 0h = FIFO_U2H is not empty 1h = FIFO_U2H is empty 0 RESERVED R 0h 15-12 H2U_LEVEL R 0h HART-to-µC FIFO LevelCurrent level of FIFO_H2U, right shifted 1 bit (>>1) so only even counts are represented. 15-12H2U_LEVELR0hHART-to-µC FIFO LevelCurrent level of FIFO_H2U, right shifted 1 bit (>>1) so only even counts are represented. 11 H2U_LEVEL_FLAG R 0h HART-to-µC FIFO Level FlagSet when FIFO Level > {Level,1b1}. 0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 11H2U_LEVEL_FLAGR0hHART-to-µC FIFO Level FlagSet when FIFO Level > {Level,1b1}. 0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1} 0h = FIFO_H2U level ≤ {Level, 1b1}1h = FIFO_H2U level > {Level, 1b1} 10 H2U_FULL_FLAG R 0h HART-to-µC FIFO Full FlagSet when FIFO is full. 0h = FIFO_H2U is not full 1h = FIFO_H2U is full 10H2U_FULL_FLAGR0hHART-to-µC FIFO Full FlagSet when FIFO is full. 0h = FIFO_H2U is not full 1h = FIFO_H2U is full 0h = FIFO_H2U is not full1h = FIFO_H2U is full 9 H2U_EMPTY_FLAG R 1h HART-to-µC Empty FlagSet when FIFO is empty. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 9H2U_EMPTY_FLAGR1hHART-to-µC Empty FlagSet when FIFO is empty. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty 0h = FIFO_H2U is not empty1h = FIFO_H2U is empty 8 RESERVED R 0h 8RESERVEDR0h 7-4 U2H_LEVEL R 0h µC-to-HART FIFO LevelCurrent level of FIFO_U2H, right shifted 1 bit (>>1) so only even counts are represented 7-4U2H_LEVELR0hµC-to-HART FIFO LevelCurrent level of FIFO_U2H, right shifted 1 bit (>>1) so only even counts are represented 3 U2H_LEVEL_FLAG R 0h µC-to-HART FIFO Level FlagSet when FIFO_U2H Level < {Level,1b0}. 0h = FIFO_U2H level ≥ {Level, 1b0} 1h = FIFO_U2H level < {Level, 1b0} 3U2H_LEVEL_FLAGR0hµC-to-HART FIFO Level FlagSet when FIFO_U2H Level < {Level,1b0}. 0h = FIFO_U2H level ≥ {Level, 1b0} 1h = FIFO_U2H level < {Level, 1b0} 0h = FIFO_U2H level ≥ {Level, 1b0}1h = FIFO_U2H level < {Level, 1b0} 2 U2H_FULL_FLAG R 0h µC-to-HART Full FlagSet when FIFO_U2H is full. 0h = FIFO_U2H is not full 1h = FIFO_U2H is full 2U2H_FULL_FLAGR0hµC-to-HART Full FlagSet when FIFO_U2H is full. 0h = FIFO_U2H is not full 1h = FIFO_U2H is full 0h = FIFO_U2H is not full1h = FIFO_U2H is full 1 U2H_EMPTY_FLAG R 1h µC-to-HART Empty FlagSet when FIFO_U2H is empty. 0h = FIFO_U2H is not empty 1h = FIFO_U2H is empty 1U2H_EMPTY_FLAGR1hµC-to-HART Empty FlagSet when FIFO_U2H is empty. 0h = FIFO_U2H is not empty 1h = FIFO_U2H is empty 0h = FIFO_U2H is not empty1h = FIFO_U2H is empty 0 RESERVED R 0h 0RESERVEDR0h DAC_OUT Register (Offset = 2Ch) [Reset = 0000h] Return to the Register Map . DAC_OUT Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R 0h DAC Code Applied to the Analog Circuit DAC_OUT Register (Offset = 2Ch) [Reset = 0000h] DAC_OUTReturn to the Register Map . Register Map Register Map DAC_OUT Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R 0h DAC Code Applied to the Analog Circuit DAC_OUT Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R 0h DAC Code Applied to the Analog Circuit Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 DATA R 0h DAC Code Applied to the Analog Circuit 15-0 DATA R 0h DAC Code Applied to the Analog Circuit 15-0DATAR0h DAC Code Applied to the Analog Circuit ADC_OUT Register (Offset = 2Dh) [Reset = 0000h] Return to the Register Map . ADC_OUT Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Data for Each Conversion Does not include ADC_OFFSET.DATA adjustment. Is not affected by ADC_BYP.DATA. ADC_OUT Register (Offset = 2Dh) [Reset = 0000h] ADC_OUTReturn to the Register Map . Register Map Register Map ADC_OUT Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Data for Each Conversion Does not include ADC_OFFSET.DATA adjustment. Is not affected by ADC_BYP.DATA. ADC_OUT Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Data for Each Conversion Does not include ADC_OFFSET.DATA adjustment. Is not affected by ADC_BYP.DATA. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Data for Each Conversion Does not include ADC_OFFSET.DATA adjustment. Is not affected by ADC_BYP.DATA. 15-12 RESERVED R 0h 15-12RESERVEDR0h 11-0 DATA R 0h ADC Data for Each Conversion Does not include ADC_OFFSET.DATA adjustment. Is not affected by ADC_BYP.DATA. 11-0DATAR0hADC Data for Each Conversion Does not include ADC_OFFSET.DATA adjustment. Is not affected by ADC_BYP.DATA. ADC_BYP Register (Offset = 2Eh) [Reset = 0000h] Return to the Register Map . ADC_BYP is shown in ADC_BYP Register Field Descriptions . ADC_BYP Register Field Descriptions Bit Field Type Reset Description 15 DATA_BYP_EN R/W 0h Data Bypass EnableApplies ADC_BYP.DATA to the ADC channel being converted. ADC_OFFSET is ignored. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. If OFST_BYP_EN is also set, DATA_BYP_EN takes priority over OFST_BYP_EN. After a channel is converted, the ADC_BYP.DATA value appears in the readback register for the converted channel and is used to calculate faults. 0h = Data bypass disabled (default) 1h = Data bypass enabled 14 OFST_BYP_EN R/W 0h Offset Bypass EnableOverrides the offset register with the ADC_BYP.DATA value. When using this bit, the ADC_BYP.DATA field is processed as 2's complement. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time.0h = Offset bypass disabled (default) 1h = Offset bypass enabled 13 DIS_GND_SAMP R/W 0h Disable GND SamplingThis bit disables the sampling of GND during SAR activity. The sampling of GND is used to fully discharge the sampling CAP to reduce channel crosstalk. 0h = GND sampling enabled (default) 1h = GND sampling disabled 12 RESERVED R 0h 11-0 DATA R/W 0h Bypass Data ADC_BYP Register (Offset = 2Eh) [Reset = 0000h] ADC_BYPReturn to the Register Map . Register Map Register MapADC_BYP is shown in ADC_BYP Register Field Descriptions . ADC_BYP Register Field Descriptions ADC_BYP Register Field Descriptions ADC_BYP Register Field Descriptions Bit Field Type Reset Description 15 DATA_BYP_EN R/W 0h Data Bypass EnableApplies ADC_BYP.DATA to the ADC channel being converted. ADC_OFFSET is ignored. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. If OFST_BYP_EN is also set, DATA_BYP_EN takes priority over OFST_BYP_EN. After a channel is converted, the ADC_BYP.DATA value appears in the readback register for the converted channel and is used to calculate faults. 0h = Data bypass disabled (default) 1h = Data bypass enabled 14 OFST_BYP_EN R/W 0h Offset Bypass EnableOverrides the offset register with the ADC_BYP.DATA value. When using this bit, the ADC_BYP.DATA field is processed as 2's complement. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time.0h = Offset bypass disabled (default) 1h = Offset bypass enabled 13 DIS_GND_SAMP R/W 0h Disable GND SamplingThis bit disables the sampling of GND during SAR activity. The sampling of GND is used to fully discharge the sampling CAP to reduce channel crosstalk. 0h = GND sampling enabled (default) 1h = GND sampling disabled 12 RESERVED R 0h 11-0 DATA R/W 0h Bypass Data ADC_BYP Register Field Descriptions Bit Field Type Reset Description 15 DATA_BYP_EN R/W 0h Data Bypass EnableApplies ADC_BYP.DATA to the ADC channel being converted. ADC_OFFSET is ignored. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. If OFST_BYP_EN is also set, DATA_BYP_EN takes priority over OFST_BYP_EN. After a channel is converted, the ADC_BYP.DATA value appears in the readback register for the converted channel and is used to calculate faults. 0h = Data bypass disabled (default) 1h = Data bypass enabled 14 OFST_BYP_EN R/W 0h Offset Bypass EnableOverrides the offset register with the ADC_BYP.DATA value. When using this bit, the ADC_BYP.DATA field is processed as 2's complement. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time.0h = Offset bypass disabled (default) 1h = Offset bypass enabled 13 DIS_GND_SAMP R/W 0h Disable GND SamplingThis bit disables the sampling of GND during SAR activity. The sampling of GND is used to fully discharge the sampling CAP to reduce channel crosstalk. 0h = GND sampling enabled (default) 1h = GND sampling disabled 12 RESERVED R 0h 11-0 DATA R/W 0h Bypass Data Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15 DATA_BYP_EN R/W 0h Data Bypass EnableApplies ADC_BYP.DATA to the ADC channel being converted. ADC_OFFSET is ignored. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. If OFST_BYP_EN is also set, DATA_BYP_EN takes priority over OFST_BYP_EN. After a channel is converted, the ADC_BYP.DATA value appears in the readback register for the converted channel and is used to calculate faults. 0h = Data bypass disabled (default) 1h = Data bypass enabled 14 OFST_BYP_EN R/W 0h Offset Bypass EnableOverrides the offset register with the ADC_BYP.DATA value. When using this bit, the ADC_BYP.DATA field is processed as 2's complement. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time.0h = Offset bypass disabled (default) 1h = Offset bypass enabled 13 DIS_GND_SAMP R/W 0h Disable GND SamplingThis bit disables the sampling of GND during SAR activity. The sampling of GND is used to fully discharge the sampling CAP to reduce channel crosstalk. 0h = GND sampling enabled (default) 1h = GND sampling disabled 12 RESERVED R 0h 11-0 DATA R/W 0h Bypass Data 15 DATA_BYP_EN R/W 0h Data Bypass EnableApplies ADC_BYP.DATA to the ADC channel being converted. ADC_OFFSET is ignored. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. If OFST_BYP_EN is also set, DATA_BYP_EN takes priority over OFST_BYP_EN. After a channel is converted, the ADC_BYP.DATA value appears in the readback register for the converted channel and is used to calculate faults. 0h = Data bypass disabled (default) 1h = Data bypass enabled 15DATA_BYP_ENR/W0hData Bypass EnableApplies ADC_BYP.DATA to the ADC channel being converted. ADC_OFFSET is ignored. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. If OFST_BYP_EN is also set, DATA_BYP_EN takes priority over OFST_BYP_EN. After a channel is converted, the ADC_BYP.DATA value appears in the readback register for the converted channel and is used to calculate faults. 0h = Data bypass disabled (default) 1h = Data bypass enabled 0h = Data bypass disabled (default)1h = Data bypass enabled 14 OFST_BYP_EN R/W 0h Offset Bypass EnableOverrides the offset register with the ADC_BYP.DATA value. When using this bit, the ADC_BYP.DATA field is processed as 2's complement. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time.0h = Offset bypass disabled (default) 1h = Offset bypass enabled 14OFST_BYP_ENR/W0hOffset Bypass EnableOverrides the offset register with the ADC_BYP.DATA value. When using this bit, the ADC_BYP.DATA field is processed as 2's complement. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time.0h = Offset bypass disabled (default) 1h = Offset bypass enabled 0h = Offset bypass disabled (default)1h = Offset bypass enabled 13 DIS_GND_SAMP R/W 0h Disable GND SamplingThis bit disables the sampling of GND during SAR activity. The sampling of GND is used to fully discharge the sampling CAP to reduce channel crosstalk. 0h = GND sampling enabled (default) 1h = GND sampling disabled 13DIS_GND_SAMPR/W0hDisable GND SamplingThis bit disables the sampling of GND during SAR activity. The sampling of GND is used to fully discharge the sampling CAP to reduce channel crosstalk. 0h = GND sampling enabled (default) 1h = GND sampling disabled 0h = GND sampling enabled (default)1h = GND sampling disabled 12 RESERVED R 0h 12RESERVEDR0h 11-0 DATA R/W 0h Bypass Data 11-0DATAR/W0hBypass Data FORCE_FAIL Register (Offset = 2Fh) [Reset = 0000h] Return to the Register Map . Force failures for fault detection. FORCE_FAIL Register Field Descriptions Bit Field Type Reset Description 15 CRC_FLT R/W 0h Force CRC Failure on SDO by Inverting the CRC Byte 0h = No force failure of CRC (default) 1h = Force failure of CRC 14 VREF_FLT R/W 0h Force Reference Voltage Failure. Analog signal.0h = No force failure of VREF (default) 1h = Force failure of VREF 13 THERM_ERR_FLT R/W 0h Force Temperature > 130°C Thermal Error. Analog signal.0h = No force temperature > 130°C error (default) 1h = Force temperature > 130°C error 12 THERM_WARN_FLT R/W 0h Force Temperature > 85°C thermal Warning. Analog signal.0h = No force temperature > 85°C warning (default) 1h = Force temperature > 85°C warning 11-10 RESERVED R/W 0h 9 SD4_HI_FLT R/W 0h SD4 (VOUT) High Limit Failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 8 SD4_LO_FLT R/W 0h SD4 (VOUT) Low limit failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 7 SD3_HI_FLT R/W 0h SD3 (ZTAT) High Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 6 SD3_LO_FLT R/W 0h SD3 (ZTAT) Low Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 5 SD2_HI_FLT R/W 0h SD2 (VDD) High Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 4 SD2_LO_FLT R/W 0h SD2 (VDD) Low Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 3 SD1_HI_FLT R/W 0h SD1 (PVDD) High Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 2 SD1_LO_FLT R/W 0h SD1 (PVDD) Low Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 1 SD0_HI_FLT R/W 0h SD0 (VREF) High Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 0 SD0_LO_FLT R/W 0h SD0 (VREF) Low Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) FORCE_FAIL Register (Offset = 2Fh) [Reset = 0000h] FORCE_FAILReturn to the Register Map . Register Map Register MapForce failures for fault detection. FORCE_FAIL Register Field Descriptions Bit Field Type Reset Description 15 CRC_FLT R/W 0h Force CRC Failure on SDO by Inverting the CRC Byte 0h = No force failure of CRC (default) 1h = Force failure of CRC 14 VREF_FLT R/W 0h Force Reference Voltage Failure. Analog signal.0h = No force failure of VREF (default) 1h = Force failure of VREF 13 THERM_ERR_FLT R/W 0h Force Temperature > 130°C Thermal Error. Analog signal.0h = No force temperature > 130°C error (default) 1h = Force temperature > 130°C error 12 THERM_WARN_FLT R/W 0h Force Temperature > 85°C thermal Warning. Analog signal.0h = No force temperature > 85°C warning (default) 1h = Force temperature > 85°C warning 11-10 RESERVED R/W 0h 9 SD4_HI_FLT R/W 0h SD4 (VOUT) High Limit Failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 8 SD4_LO_FLT R/W 0h SD4 (VOUT) Low limit failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 7 SD3_HI_FLT R/W 0h SD3 (ZTAT) High Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 6 SD3_LO_FLT R/W 0h SD3 (ZTAT) Low Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 5 SD2_HI_FLT R/W 0h SD2 (VDD) High Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 4 SD2_LO_FLT R/W 0h SD2 (VDD) Low Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 3 SD1_HI_FLT R/W 0h SD1 (PVDD) High Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 2 SD1_LO_FLT R/W 0h SD1 (PVDD) Low Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 1 SD0_HI_FLT R/W 0h SD0 (VREF) High Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 0 SD0_LO_FLT R/W 0h SD0 (VREF) Low Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) FORCE_FAIL Register Field Descriptions Bit Field Type Reset Description 15 CRC_FLT R/W 0h Force CRC Failure on SDO by Inverting the CRC Byte 0h = No force failure of CRC (default) 1h = Force failure of CRC 14 VREF_FLT R/W 0h Force Reference Voltage Failure. Analog signal.0h = No force failure of VREF (default) 1h = Force failure of VREF 13 THERM_ERR_FLT R/W 0h Force Temperature > 130°C Thermal Error. Analog signal.0h = No force temperature > 130°C error (default) 1h = Force temperature > 130°C error 12 THERM_WARN_FLT R/W 0h Force Temperature > 85°C thermal Warning. Analog signal.0h = No force temperature > 85°C warning (default) 1h = Force temperature > 85°C warning 11-10 RESERVED R/W 0h 9 SD4_HI_FLT R/W 0h SD4 (VOUT) High Limit Failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 8 SD4_LO_FLT R/W 0h SD4 (VOUT) Low limit failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 7 SD3_HI_FLT R/W 0h SD3 (ZTAT) High Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 6 SD3_LO_FLT R/W 0h SD3 (ZTAT) Low Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 5 SD2_HI_FLT R/W 0h SD2 (VDD) High Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 4 SD2_LO_FLT R/W 0h SD2 (VDD) Low Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 3 SD1_HI_FLT R/W 0h SD1 (PVDD) High Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 2 SD1_LO_FLT R/W 0h SD1 (PVDD) Low Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 1 SD0_HI_FLT R/W 0h SD0 (VREF) High Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 0 SD0_LO_FLT R/W 0h SD0 (VREF) Low Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15 CRC_FLT R/W 0h Force CRC Failure on SDO by Inverting the CRC Byte 0h = No force failure of CRC (default) 1h = Force failure of CRC 14 VREF_FLT R/W 0h Force Reference Voltage Failure. Analog signal.0h = No force failure of VREF (default) 1h = Force failure of VREF 13 THERM_ERR_FLT R/W 0h Force Temperature > 130°C Thermal Error. Analog signal.0h = No force temperature > 130°C error (default) 1h = Force temperature > 130°C error 12 THERM_WARN_FLT R/W 0h Force Temperature > 85°C thermal Warning. Analog signal.0h = No force temperature > 85°C warning (default) 1h = Force temperature > 85°C warning 11-10 RESERVED R/W 0h 9 SD4_HI_FLT R/W 0h SD4 (VOUT) High Limit Failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 8 SD4_LO_FLT R/W 0h SD4 (VOUT) Low limit failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 7 SD3_HI_FLT R/W 0h SD3 (ZTAT) High Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 6 SD3_LO_FLT R/W 0h SD3 (ZTAT) Low Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 5 SD2_HI_FLT R/W 0h SD2 (VDD) High Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 4 SD2_LO_FLT R/W 0h SD2 (VDD) Low Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 3 SD1_HI_FLT R/W 0h SD1 (PVDD) High Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 2 SD1_LO_FLT R/W 0h SD1 (PVDD) Low Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 1 SD0_HI_FLT R/W 0h SD0 (VREF) High Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 0 SD0_LO_FLT R/W 0h SD0 (VREF) Low Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 15 CRC_FLT R/W 0h Force CRC Failure on SDO by Inverting the CRC Byte 0h = No force failure of CRC (default) 1h = Force failure of CRC 15CRC_FLTR/W0hForce CRC Failure on SDO by Inverting the CRC Byte 0h = No force failure of CRC (default) 1h = Force failure of CRC 0h = No force failure of CRC (default)1h = Force failure of CRC 14 VREF_FLT R/W 0h Force Reference Voltage Failure. Analog signal.0h = No force failure of VREF (default) 1h = Force failure of VREF 14VREF_FLTR/W0hForce Reference Voltage Failure. Analog signal.0h = No force failure of VREF (default) 1h = Force failure of VREF 0h = No force failure of VREF (default)1h = Force failure of VREF 13 THERM_ERR_FLT R/W 0h Force Temperature > 130°C Thermal Error. Analog signal.0h = No force temperature > 130°C error (default) 1h = Force temperature > 130°C error 13THERM_ERR_FLTR/W0hForce Temperature > 130°C Thermal Error. Analog signal.0h = No force temperature > 130°C error (default) 1h = Force temperature > 130°C error 0h = No force temperature > 130°C error (default)1h = Force temperature > 130°C error 12 THERM_WARN_FLT R/W 0h Force Temperature > 85°C thermal Warning. Analog signal.0h = No force temperature > 85°C warning (default) 1h = Force temperature > 85°C warning 12THERM_WARN_FLTR/W0hForce Temperature > 85°C thermal Warning. Analog signal.0h = No force temperature > 85°C warning (default) 1h = Force temperature > 85°C warning 0h = No force temperature > 85°C warning (default)1h = Force temperature > 85°C warning 11-10 RESERVED R/W 0h 11-10RESERVEDR/W0h 9 SD4_HI_FLT R/W 0h SD4 (VOUT) High Limit Failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 9SD4_HI_FLTR/W0hSD4 (VOUT) High Limit Failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 0h = No force failure of SD4 (VOUT) (default)1h = Force failure of SD4 (VOUT) 8 SD4_LO_FLT R/W 0h SD4 (VOUT) Low limit failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 8SD4_LO_FLTR/W0hSD4 (VOUT) Low limit failure. ADC measurement.0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 0h = No force failure of SD4 (VOUT) (default)1h = Force failure of SD4 (VOUT) 7 SD3_HI_FLT R/W 0h SD3 (ZTAT) High Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 7SD3_HI_FLTR/W0hSD3 (ZTAT) High Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 0h = No force failure of SD3 (ZTAT) (default)1h = Force failure of SD3 (ZTAT) 6 SD3_LO_FLT R/W 0h SD3 (ZTAT) Low Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 6SD3_LO_FLTR/W0hSD3 (ZTAT) Low Limit Failure. ADC measurement.0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 0h = No force failure of SD3 (ZTAT) (default)1h = Force failure of SD3 (ZTAT) 5 SD2_HI_FLT R/W 0h SD2 (VDD) High Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 5SD2_HI_FLTR/W0hSD2 (VDD) High Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 0h = No force failure of SD2 (VDD) (default)1h = Force failure of SD2 (VDD) 4 SD2_LO_FLT R/W 0h SD2 (VDD) Low Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 4SD2_LO_FLTR/W0hSD2 (VDD) Low Limit Failure. ADC measurement.0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 0h = No force failure of SD2 (VDD) (default)1h = Force failure of SD2 (VDD) 3 SD1_HI_FLT R/W 0h SD1 (PVDD) High Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 3SD1_HI_FLTR/W0hSD1 (PVDD) High Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 0h = No force failure of SD1 (PVDD) (default)1h = Force failure of SD1 (PVDD) 2 SD1_LO_FLT R/W 0h SD1 (PVDD) Low Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 2SD1_LO_FLTR/W0hSD1 (PVDD) Low Limit Failure. ADC measurement.0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 0h = No force failure of SD1 (PVDD) (default)1h = Force failure of SD1 (PVDD) 1 SD0_HI_FLT R/W 0h SD0 (VREF) High Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 1SD0_HI_FLTR/W0hSD0 (VREF) High Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 0h = No force failure of SD0 (VREF) (default)1h = Force failure of SD0 (VREF) 0 SD0_LO_FLT R/W 0h SD0 (VREF) Low Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 0SD0_LO_FLTR/W0hSD0 (VREF) Low Limit Failure. ADC measurement.0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 0h = No force failure of SD0 (VREF) (default)1h = Force failure of SD0 (VREF) TIMER_CFG_0 Register (Offset = 3Bh) [Reset = 0000h] Return to the Register Map . TIMER Configuration 0. TIMER CONFIG 0 Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED TO 0h 3-2 CLK_SEL R/W 0h Clock SelectSelects the timer clock frequency. 0h = None (default) 1h = 1.2288 MHz 2h = 1.200 kHz 3h = 1.171 Hz 1 INVERT R/W 0h Invert OutputInvert the Timer output. By default, the output is set to 1 when the counter is ≥ SET_TIME (3Dh). 0 ENABLE R/W 0h Timer Enable The CLK_OUT pin must also be configured to output the Timer. TIMER_CFG_0 Register (Offset = 3Bh) [Reset = 0000h] TIMER_CFG_0Return to the Register Map . Register Map Register MapTIMER Configuration 0. TIMER CONFIG 0 Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED TO 0h 3-2 CLK_SEL R/W 0h Clock SelectSelects the timer clock frequency. 0h = None (default) 1h = 1.2288 MHz 2h = 1.200 kHz 3h = 1.171 Hz 1 INVERT R/W 0h Invert OutputInvert the Timer output. By default, the output is set to 1 when the counter is ≥ SET_TIME (3Dh). 0 ENABLE R/W 0h Timer Enable The CLK_OUT pin must also be configured to output the Timer. TIMER CONFIG 0 Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED TO 0h 3-2 CLK_SEL R/W 0h Clock SelectSelects the timer clock frequency. 0h = None (default) 1h = 1.2288 MHz 2h = 1.200 kHz 3h = 1.171 Hz 1 INVERT R/W 0h Invert OutputInvert the Timer output. By default, the output is set to 1 when the counter is ≥ SET_TIME (3Dh). 0 ENABLE R/W 0h Timer Enable The CLK_OUT pin must also be configured to output the Timer. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-4 RESERVED TO 0h 3-2 CLK_SEL R/W 0h Clock SelectSelects the timer clock frequency. 0h = None (default) 1h = 1.2288 MHz 2h = 1.200 kHz 3h = 1.171 Hz 1 INVERT R/W 0h Invert OutputInvert the Timer output. By default, the output is set to 1 when the counter is ≥ SET_TIME (3Dh). 0 ENABLE R/W 0h Timer Enable The CLK_OUT pin must also be configured to output the Timer. 15-4 RESERVED TO 0h 15-4RESERVEDTO0h 3-2 CLK_SEL R/W 0h Clock SelectSelects the timer clock frequency. 0h = None (default) 1h = 1.2288 MHz 2h = 1.200 kHz 3h = 1.171 Hz 3-2CLK_SELR/W0hClock SelectSelects the timer clock frequency. 0h = None (default) 1h = 1.2288 MHz 2h = 1.200 kHz 3h = 1.171 Hz Selects the timer clock frequency.0h = None (default)1h = 1.2288 MHz2h = 1.200 kHz3h = 1.171 Hz 1 INVERT R/W 0h Invert OutputInvert the Timer output. By default, the output is set to 1 when the counter is ≥ SET_TIME (3Dh). 1INVERTR/W0hInvert OutputInvert the Timer output. By default, the output is set to 1 when the counter is ≥ SET_TIME (3Dh). Invert the Timer output. By default, the output is set to 1 when the counter is ≥ SET_TIME (3Dh). 0 ENABLE R/W 0h Timer Enable The CLK_OUT pin must also be configured to output the Timer. 0ENABLER/W0hTimer Enable The CLK_OUT pin must also be configured to output the Timer. The CLK_OUT pin must also be configured to output the Timer. TIMER_CFG_1 Register (Offset = 3Ch) [Reset = 0000h] Return to the Register Map . TIMER Configuration 1. TIMER CONFIG 1 Register Field Descriptions Bit Field Type Reset Description 15-0 PERIOD R/W 0h This field defines the period of the timer. The period is the product of (PERIOD + 1) and the clock period of CLK_SEL. For example, CLK_SEL = 2h (1200 Hz), The period is (PERIOD + 1) × 853 ms. TIMER_CFG_1 Register (Offset = 3Ch) [Reset = 0000h] TIMER_CFG_1Return to the Register Map . Register Map Register MapTIMER Configuration 1. TIMER CONFIG 1 Register Field Descriptions Bit Field Type Reset Description 15-0 PERIOD R/W 0h This field defines the period of the timer. The period is the product of (PERIOD + 1) and the clock period of CLK_SEL. For example, CLK_SEL = 2h (1200 Hz), The period is (PERIOD + 1) × 853 ms. TIMER CONFIG 1 Register Field Descriptions Bit Field Type Reset Description 15-0 PERIOD R/W 0h This field defines the period of the timer. The period is the product of (PERIOD + 1) and the clock period of CLK_SEL. For example, CLK_SEL = 2h (1200 Hz), The period is (PERIOD + 1) × 853 ms. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 PERIOD R/W 0h This field defines the period of the timer. The period is the product of (PERIOD + 1) and the clock period of CLK_SEL. For example, CLK_SEL = 2h (1200 Hz), The period is (PERIOD + 1) × 853 ms. 15-0 PERIOD R/W 0h This field defines the period of the timer. The period is the product of (PERIOD + 1) and the clock period of CLK_SEL. For example, CLK_SEL = 2h (1200 Hz), The period is (PERIOD + 1) × 853 ms. 15-0PERIODR/W0h This field defines the period of the timer. The period is the product of (PERIOD + 1) and the clock period of CLK_SEL. For example, CLK_SEL = 2h (1200 Hz), The period is (PERIOD + 1) × 853 ms. This field defines the period of the timer. The period is the product of (PERIOD + 1) and the clock period of CLK_SEL. For example, CLK_SEL = 2h (1200 Hz), The period is (PERIOD + 1) × 853 ms. TIMER_CFG_2 Register (Offset = 3Dh) [Reset = 0000h] Return to the Register Map . TIMER Configuration 2. TIMER CONFIG 2 Register Field Descriptions Bit Field Type Reset Description 15-0 SET_TIME R/W 0h The SET_TIME determine when the output of the timer goes high. The bits define the duty cycle of the timer (PERIOD – SET_TIME). The timer starts out as 0 and transitions to 1 when the SET_TIME is met. The polarity of the timer can be inverted using the TIMER_CFG_0.INVERT bit. TIMER_CFG_2 Register (Offset = 3Dh) [Reset = 0000h] TIMER_CFG_2Return to the Register Map . Register Map Register MapTIMER Configuration 2. TIMER CONFIG 2 Register Field Descriptions Bit Field Type Reset Description 15-0 SET_TIME R/W 0h The SET_TIME determine when the output of the timer goes high. The bits define the duty cycle of the timer (PERIOD – SET_TIME). The timer starts out as 0 and transitions to 1 when the SET_TIME is met. The polarity of the timer can be inverted using the TIMER_CFG_0.INVERT bit. TIMER CONFIG 2 Register Field Descriptions Bit Field Type Reset Description 15-0 SET_TIME R/W 0h The SET_TIME determine when the output of the timer goes high. The bits define the duty cycle of the timer (PERIOD – SET_TIME). The timer starts out as 0 and transitions to 1 when the SET_TIME is met. The polarity of the timer can be inverted using the TIMER_CFG_0.INVERT bit. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 SET_TIME R/W 0h The SET_TIME determine when the output of the timer goes high. The bits define the duty cycle of the timer (PERIOD – SET_TIME). The timer starts out as 0 and transitions to 1 when the SET_TIME is met. The polarity of the timer can be inverted using the TIMER_CFG_0.INVERT bit. 15-0 SET_TIME R/W 0h The SET_TIME determine when the output of the timer goes high. The bits define the duty cycle of the timer (PERIOD – SET_TIME). The timer starts out as 0 and transitions to 1 when the SET_TIME is met. The polarity of the timer can be inverted using the TIMER_CFG_0.INVERT bit. 15-0SET_TIMER/W0hThe SET_TIME determine when the output of the timer goes high. The bits define the duty cycle of the timer (PERIOD – SET_TIME). The timer starts out as 0 and transitions to 1 when the SET_TIME is met. The polarity of the timer can be inverted using the TIMER_CFG_0.INVERT bit. CRC_RD Register (Offset = 3Eh) [Reset = 0000h] Return to the Register Map . CRC read. CRC Read Register Field Descriptions Bit Field Type Reset Description 15-0 CRC R/O 0h Calculated CRC for RBIST or SHADOWLOAD. Final value is calculated internally. This value changes while RBIST or shadow load are running. CRC_RD Register (Offset = 3Eh) [Reset = 0000h] CRC_RDReturn to the Register Map . Register Map Register MapCRC read. CRC Read Register Field Descriptions Bit Field Type Reset Description 15-0 CRC R/O 0h Calculated CRC for RBIST or SHADOWLOAD. Final value is calculated internally. This value changes while RBIST or shadow load are running. CRC Read Register Field Descriptions Bit Field Type Reset Description 15-0 CRC R/O 0h Calculated CRC for RBIST or SHADOWLOAD. Final value is calculated internally. This value changes while RBIST or shadow load are running. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 CRC R/O 0h Calculated CRC for RBIST or SHADOWLOAD. Final value is calculated internally. This value changes while RBIST or shadow load are running. 15-0 CRC R/O 0h Calculated CRC for RBIST or SHADOWLOAD. Final value is calculated internally. This value changes while RBIST or shadow load are running. 15-0CRCR/O0hCalculated CRC for RBIST or SHADOWLOAD. Final value is calculated internally. This value changes while RBIST or shadow load are running. RBIST_CRC Register (Offset = 3Fh) [Reset = 0000h] Return to the Register Map . RBIST CRC. RBIST CRC Register Field Descriptions Bit Field Type Reset Description 15-0 RBIST CRC R/W 0h Calculated CRC for Register RBIST RBIST_CRC Register (Offset = 3Fh) [Reset = 0000h] RBIST_CRCReturn to the Register Map . Register Map Register MapRBIST CRC. RBIST CRC Register Field Descriptions Bit Field Type Reset Description 15-0 RBIST CRC R/W 0h Calculated CRC for Register RBIST RBIST CRC Register Field Descriptions Bit Field Type Reset Description 15-0 RBIST CRC R/W 0h Calculated CRC for Register RBIST Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 15-0 RBIST CRC R/W 0h Calculated CRC for Register RBIST 15-0 RBIST CRC R/W 0h Calculated CRC for Register RBIST 15-0RBIST CRCR/W0hCalculated CRC for Register RBIST Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Application Information The AFEx82H1 are extremely low-power 16-bit and 14-bit voltage output DACs. The DACs support an output range of 0 V to 2.5 V. These devices have an onboard oscillator and an optional precision internal reference. This DAC is designed for analog voltage or current output modules. These devices also feature a SAR ADC that is used to measure internal and external nodes for making diagnostic measurements with fault detection and alarm actions. Use these diagnostic measurements together with the CRC and watchdog timer monitoring for device and system monitoring for functional safety. The AFEx82H1 devices support modem functionality with the Highway Addressable Remote Transducer (HART) Protocol through SPI or UART communications. A HART interface is created through modulation and demodulation using the SPI or UART. Demodulate the input through band-pass filtering internal or external to the device. The PVDD power supply has an operating range of 2.7 V to 5.5 V. The VDD is powered from an onboard LDO. Run the digital interface supply, IOVDD, from 1.71 V to 5.5 V. Multichannel Configuration The integration of receive and transmit FIFOs for HART communication enables easy scalability in multichannel configurations using the SPI only interface. Because CS low is required for communication and SDO can be set to a tri-state condition, only individual CS signals are required from the microcontroller for all the AFEx82H1 devices in the system. The SDI, SDO, and SCLK signals can be combined. All the individual ALARM pins can be wired-OR together. This minimizes the number of microcontroller GPIO signals required for communication, as well as the number of isolation channels for isolated systems. The multichannel configuration block diagram is shown in . Multichannel Configuration Typical Application This design example shows a loop-powered, 4-mA to 20-mA field transmitter featuring the AFE882H1. The AFE782H1 can also be used in this design for lower-resolution applications. This design example creates a simple HART-enabled loop controller that can be used for most field sensors in two-wire, current-loop applications. The design accepts bus voltages from 15 V to 36 V, while regulating the loop-current representation of a sensor to a post-calibration accuracy of less than 0.1% full-scale range (FSR) of total error at room temperature. The high integration in the system allows for a compact circuit, making this device an excellent choice for field transmitters where space is a concern. In field-transmitter applications, the current-loop transmitter, microcontroller, sensors, and analog front end are all required to consume less than the minimum bus current of 3 mA. Use an efficient low-power DC/DC converter instead of an LDO in the system to extend the current budget and allow more current for sensors and the AFE. shows the schematic diagram for the loop-powered, 4-mA to 20-mA field transmitter. 4-mA to 20-mA Current Transmitter AFEx82H1 in a 4-mA to 20-mA Current Transmitter Design Requirements The design requirements are: Transmitter with a current output range of 4 mA to 20 mA to represent a process variable signal Out-of-range current output capability below 3.6 mA and above 21 mA for NAMUR NE43 sensor fault signal levels Total on-board current less than or equal to 3 mA to operate the board, but allow for low out-of-range outputs Operation with standard industrial automation supply voltages from 15 V to 36 V Current and voltage outputs with TUE less than 0.5% at 25°C after calibration Detailed Design Procedure shows a block diagram of a loop-powered, 4-mA to 20-mA current transmitter. Block Diagram of a Loop-Powered, 4-mA to 20-mA Current Transmitter The terminals connected to the loop are shown on the right side of the block diagram. This connection to the loop powers the entire transmitter. A bridge rectifier at the input protects against reverse connection to the loop. The rectified loop voltage powers a start-up circuit that provides power to an LDO, that in turn powers the AFE882H1 and an MCU. The AFE882H1 controls the loop current through the voltage-to-current (V-to-I) converter block. The DAC voltage sets the output from 0 V to 2.5 V. The output is sent through a V-to-I converter block using an OPA333 and an NPN bipolar junction transistor (BJT). The HART signal is not received at the positive terminal of the 4-mA to 20-mA connections, but instead is received after the loop-protection rectifier. This HART signal input is capacitively coupled to this LOOP+ internal node of the circuit as shown in . The HART signal output is modulated onto the loop current from the AFE882H1 through the V-to-I converter circuit. Current Loop Control The DAC of the AFE882H1 sets an output voltage from 0 V to 2.5 V. shows the V-to-I circuit that sets the loop current from the DAC output voltage. Current Loop Control for the AFE882H1 Transmitter In this circuit, the loop current is set by the addition of the currents of V-to-I conversion from the output of VREFIO and the DAC VOUT. The current generated from these AFE882H1 outputs are analyzed separately. First, the voltage from VREFIO is placed across a 412-kΩ resistor. This 1.25-V reference voltage creates a current that is directed into the summing node of an OPA333 amplifier that is set to ground. The voltage at LOOP– contributed from this current is calculated in . V L O O P – =   – V V R E F I O 412   k Ω × 20   k Ω =   – 1.25   V × 0.04854 = – 0.06068   V From the feedback of the OPA333, the loop voltage from is placed across the 20-Ω resistor and sets the current through the loop as shows. I L O O P _ V R E F I O = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   0.06068   V × ( 1 20   Ω   +   1 20   k Ω   ) =   3.037   m A This 3-mA current acts as a starting current for the loop. When the AFE882H1 DAC output is 0 V, this is the current on the loop. In addition to this initial current, the AFE882H1 DAC output also controls the loop current. The VOUT voltage is set across 120 kΩ of resistance (from the 20 kΩ plus 100 kΩ of series resistance). The opposite end of the 120 kΩ of resistance is set to ground by the feedback of the OPA333. Similar to the calculations in and , the voltage at VOUT sets a loop current, as and show. V L O O P – = – V O U T 120   k Ω   ×   20   k Ω   =   – V O U T   ×   0.1667 I L O O P _ V O U T = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   V O U T ×   0.1667   × ( 1 20   Ω   +   1 20   k Ω   ) When the DAC output voltage is set to 0 V, the contribution to the loop current is basically 0 mA. When the DAC output voltage is set to 2.5 V, the contribution to the loop current is 20.85 mA. As mentioned previously, the total loop current is the sum of the contribution of the current created from the VREFIO voltage and the VOUT voltage. Using these voltages, the loop current has a range from 3.037 mA to 23.89 mA. The AFE882H1 DAC output voltage is set through a 16-bit output code. Therefore, this final conversion from the DAC code to the loop current is set based on . I L O O P =   I L O O P _ V R E F I O + I L O O P _ V O U T   = 3.037   m A   +   ( D A C   C o d e × 20.85   m A 2 16 ) In 4‑mA to 20‑mA systems, the nominal output operates from 4 mA as the low output and 20 mA as the high output. However, systems sometimes use current outputs that are outside this range to indicate different error conditions. Loop currents of 3.375 mA and 21.75 mA are often used to indicate different loop errors. shows different loop output currents, along with the DAC code and voltages used. DAC Voltage Output and Loop Current Based on DAC Output Codes OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA) DAC minimum 0x0000 0 3.037 Error low 0x0426 0.04051 3.375 In-range minimum 0x0BD2 0.1154 4 In-range midscale 0x6E07 1.0745 12 In-range maximum 0xD03C 2.0335 20 Error high 0xE5B7 2.2433 21.75 DAC maximum 0xFFFF 2.5 23.891 Among the passive devices included in the design, choose current-setting resistors with tight tolerances to achieve high accuracy and low drift. These resistors discussed in the previous equations are primarily responsible for setting the gain of the current loop, and therefore, the current magnitude of the loop. HART Connections Connections of the HART signal to the loop are done through the AFE882H1 MOD_OUT and RX_IN pins. Similar to converting the VOUT pin voltage to the loop current magnitude, the HART output from the MOD_OUT pin is converted from a voltage to a current. A dc-blocking capacitor of 1000 pF is used to couple in the HART signal, without the dc output offset from the MOD_OUT pin. From MOD_OUT, the HART sinusoid nominal output is 500 mVPP. shows that this VMOD HART sinusoid voltage is set across a 499-kΩ resistor to create signal voltage VLOOPAC superimposed onto VLOOP–. V L O O P _ A C = V M O D 499   k Ω   ×   20   k Ω   =   500   m V P P 499   k Ω   ×   20   k Ω =   20.04   m V P P   The VLOOP_AC voltage sets the HART-modulated loop current that flows from ground to LOOP– through the 20-Ω resistor. This current is sourced from ground but controlled by the current sunk from Q4 coming from the start-up circuit. calculates the total loop current based on the 20 mVPP of VLOOP_AC. I L O O P _ A C =   V L O O P _ A C × ( 1 20   Ω   +   1 20   k Ω   )   =   1   m A P P Using the 1000-pF capacitor as a dc-blocking capacitor and the 499-kΩ resistor, the 500-mVPP MOD_OUT signal is converted to a 1-mAPP HART signal on the current loop. HART signals are received by the AFE882H1 through the RX_IN pin. A dc-blocking capacitor for the HART input at RX_IN is shown with a series resistance of 1 kΩ in . A diode clamps the pin to the device supply and the resistance limits the input current. This configuration protects the RX_IN from damage from an overvoltage event at the start up of the circuit. Input Protection and Rectification shows the simple protection scheme implemented in the design to mitigate issues that arise from voltage and current transients on the bus. These transients have two main components: high-frequency and high-energy. These two components can be leveraged with a strategy of attenuation and diversion by the protection circuitry to deliver robust immunity. Loop Input Protection Attenuation uses passive components, primarily resistors and capacitors, to attenuate high-frequency transients and to limit series current. Use ferrite beads to maintain dc accuracy while still delivering the ability to limit current from high-frequency transients. This circuit uses a capacitor placed across the input terminals, as well as ferrite beads in series with the terminals. Diversion capitalizes on the high-voltage properties of the transient signals by using a diode to clamp the transient within supply voltages, or to divert the energy away from the system. Transient voltage suppressor (TVS) diodes help protect against transients because TVS diodes break down very quickly and often feature high power ratings that are critical to survive multiple transient strikes. A rectifier is also implemented for reverse polarity protection so that the design can be connected to the bus regardless of the pin orientation or polarity without damage to the design. System Current Budget Power consumption is an important consideration when designing two-wire transmitters. Power supplied from the loop must power all the circuitry related to the transmitter and sensor. The minimum loop current in two-wire applications is typically 4 mA. However, for error indications, this current is as low as 3.375 mA. Therefore, the power budget of all transducer circuitry is designed to be less than the maximum allowable system power budget of 3 mA. #GUID-CAE82FB7-B01A-4571-9D73-DAAED50E22B5/TABLE_B41_5GJ_RRB lists the specified maximum quiescent current of all included active components (provided from the respective data sheets). Typical Component Currents DEVICE DESCRIPTION TYPICAL CURRENT (µA) TPS7A0533 LDO 4 AFE882H1 16-bit DAC 180 OPA333 (2) Operational amplifier 17 (each) MSP430 Microcontroller Dependent on firmware Application Curves DAC Code to Loop Current RTS Start Timing RTS Stop Timing CD Start Timing CD Stop Timing Initialization Setup This section describes several recommendations to set up the AFEx82H1. The AFEx82H1 power up with the CRC enabled. If the device is intended to be run without the CRC, the CRC must be disabled by setting the CRC_EN bit to 0h in the CONFIG register. Be aware that the command to write to this register is first done with the CRC enabled. The CRC byte must be appended to the command for the device to interpret the command correctly. To disable the CRC after start up, write 0x02 0x00 0x26 0x24 to the device. The first three bytes write the command, while the last byte is the CRC byte. For more information on the CRC, see the communication description in . The AFEx82H1 also power up with the SDO pin disabled. The SDO pin is required for reading from any of the device registers, as well as reading any data from the ADC in SPI mode. The SDO pin is enabled by writing 0h into the DSDO bit in the CONFIG register. See also and . To enable the ADC, first enable the ADC buffer by writing 0h into the BUF_PD bit in the ADC_CFG register. For information about using the ADC in different modes of operation, see . Power Supply Recommendations The AFEx82H1 can operate within a single-supply range of 2.7 V to 5.5 V applied to the PVDD pin. When 2.7 V to 5.5 V is provided to PVDD, an internal LDO is enabled that drives VDD internally. VDD pin must have 1 μF to 10 μF of capacitance for operation. The digital interface supply, IOVDD, can operate with a supply range of 1.71 V to 5.5 V. Switching power supplies and DC/DC converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes. This noise can easily couple into the DAC output voltage or current through various paths between the power connections and analog output. To further reduce noise, include bulk and local decoupling capacitors. The current consumption on the PVDD and IOVDD pins, the short-circuit current limit for the voltage output, and the current ranges for the current output are listed in the Electrical Characteristics . The power supply must meet the requirements listed in the Recommended Operating Conditions . Layout Layout Guidelines To maximize the performance of the AFEx82H1 in any application, follow good layout practices and proper circuit design. The following recommendations are specific to the device: For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane is not always practical. If ground-plane separation is necessary, make a direct connection of the planes at the DAC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops. IOVDD and PVDD must have 100-nF decoupling capacitors local to the respective pins. VDD must have at least a 1-μF decoupling capacitor used for the internal LDO. Use a high-quality ceramic-type NP0 or X7R capacitor for best performance across temperature and a very low dissipation factor. Place a 100-nF reference capacitor close to the VREFIO pin. Avoid routing switching signals near the reference input. Maintain proper placement for the digital and analog sections with respect to the digital and analog components. Separate the analog and digital circuitry for less coupling into neighboring blocks and to minimize the interaction between analog and digital return currents. For designs that include protection circuits: Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devices Use large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O pins. Layout Example Layout Example Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Application Information The AFEx82H1 are extremely low-power 16-bit and 14-bit voltage output DACs. The DACs support an output range of 0 V to 2.5 V. These devices have an onboard oscillator and an optional precision internal reference. This DAC is designed for analog voltage or current output modules. These devices also feature a SAR ADC that is used to measure internal and external nodes for making diagnostic measurements with fault detection and alarm actions. Use these diagnostic measurements together with the CRC and watchdog timer monitoring for device and system monitoring for functional safety. The AFEx82H1 devices support modem functionality with the Highway Addressable Remote Transducer (HART) Protocol through SPI or UART communications. A HART interface is created through modulation and demodulation using the SPI or UART. Demodulate the input through band-pass filtering internal or external to the device. The PVDD power supply has an operating range of 2.7 V to 5.5 V. The VDD is powered from an onboard LDO. Run the digital interface supply, IOVDD, from 1.71 V to 5.5 V. Multichannel Configuration The integration of receive and transmit FIFOs for HART communication enables easy scalability in multichannel configurations using the SPI only interface. Because CS low is required for communication and SDO can be set to a tri-state condition, only individual CS signals are required from the microcontroller for all the AFEx82H1 devices in the system. The SDI, SDO, and SCLK signals can be combined. All the individual ALARM pins can be wired-OR together. This minimizes the number of microcontroller GPIO signals required for communication, as well as the number of isolation channels for isolated systems. The multichannel configuration block diagram is shown in . Multichannel Configuration Application Information The AFEx82H1 are extremely low-power 16-bit and 14-bit voltage output DACs. The DACs support an output range of 0 V to 2.5 V. These devices have an onboard oscillator and an optional precision internal reference. This DAC is designed for analog voltage or current output modules. These devices also feature a SAR ADC that is used to measure internal and external nodes for making diagnostic measurements with fault detection and alarm actions. Use these diagnostic measurements together with the CRC and watchdog timer monitoring for device and system monitoring for functional safety. The AFEx82H1 devices support modem functionality with the Highway Addressable Remote Transducer (HART) Protocol through SPI or UART communications. A HART interface is created through modulation and demodulation using the SPI or UART. Demodulate the input through band-pass filtering internal or external to the device. The PVDD power supply has an operating range of 2.7 V to 5.5 V. The VDD is powered from an onboard LDO. Run the digital interface supply, IOVDD, from 1.71 V to 5.5 V. The AFEx82H1 are extremely low-power 16-bit and 14-bit voltage output DACs. The DACs support an output range of 0 V to 2.5 V. These devices have an onboard oscillator and an optional precision internal reference. This DAC is designed for analog voltage or current output modules. These devices also feature a SAR ADC that is used to measure internal and external nodes for making diagnostic measurements with fault detection and alarm actions. Use these diagnostic measurements together with the CRC and watchdog timer monitoring for device and system monitoring for functional safety. The AFEx82H1 devices support modem functionality with the Highway Addressable Remote Transducer (HART) Protocol through SPI or UART communications. A HART interface is created through modulation and demodulation using the SPI or UART. Demodulate the input through band-pass filtering internal or external to the device. The PVDD power supply has an operating range of 2.7 V to 5.5 V. The VDD is powered from an onboard LDO. Run the digital interface supply, IOVDD, from 1.71 V to 5.5 V. The AFEx82H1 are extremely low-power 16-bit and 14-bit voltage output DACs. The DACs support an output range of 0 V to 2.5 V. These devices have an onboard oscillator and an optional precision internal reference. This DAC is designed for analog voltage or current output modules. These devices also feature a SAR ADC that is used to measure internal and external nodes for making diagnostic measurements with fault detection and alarm actions. Use these diagnostic measurements together with the CRC and watchdog timer monitoring for device and system monitoring for functional safety. AFEx82H1The AFEx82H1 devices support modem functionality with the Highway Addressable Remote Transducer (HART) Protocol through SPI or UART communications. A HART interface is created through modulation and demodulation using the SPI or UART. Demodulate the input through band-pass filtering internal or external to the device.AFEx82H1The PVDD power supply has an operating range of 2.7 V to 5.5 V. The VDD is powered from an onboard LDO. Run the digital interface supply, IOVDD, from 1.71 V to 5.5 V. Multichannel Configuration The integration of receive and transmit FIFOs for HART communication enables easy scalability in multichannel configurations using the SPI only interface. Because CS low is required for communication and SDO can be set to a tri-state condition, only individual CS signals are required from the microcontroller for all the AFEx82H1 devices in the system. The SDI, SDO, and SCLK signals can be combined. All the individual ALARM pins can be wired-OR together. This minimizes the number of microcontroller GPIO signals required for communication, as well as the number of isolation channels for isolated systems. The multichannel configuration block diagram is shown in . Multichannel Configuration Multichannel Configuration The integration of receive and transmit FIFOs for HART communication enables easy scalability in multichannel configurations using the SPI only interface. Because CS low is required for communication and SDO can be set to a tri-state condition, only individual CS signals are required from the microcontroller for all the AFEx82H1 devices in the system. The SDI, SDO, and SCLK signals can be combined. All the individual ALARM pins can be wired-OR together. This minimizes the number of microcontroller GPIO signals required for communication, as well as the number of isolation channels for isolated systems. The multichannel configuration block diagram is shown in . Multichannel Configuration The integration of receive and transmit FIFOs for HART communication enables easy scalability in multichannel configurations using the SPI only interface. Because CS low is required for communication and SDO can be set to a tri-state condition, only individual CS signals are required from the microcontroller for all the AFEx82H1 devices in the system. The SDI, SDO, and SCLK signals can be combined. All the individual ALARM pins can be wired-OR together. This minimizes the number of microcontroller GPIO signals required for communication, as well as the number of isolation channels for isolated systems. The multichannel configuration block diagram is shown in . Multichannel Configuration The integration of receive and transmit FIFOs for HART communication enables easy scalability in multichannel configurations using the SPI only interface. Because CS low is required for communication and SDO can be set to a tri-state condition, only individual CS signals are required from the microcontroller for all the AFEx82H1 devices in the system. The SDI, SDO, and SCLK signals can be combined. All the individual ALARM pins can be wired-OR together. This minimizes the number of microcontroller GPIO signals required for communication, as well as the number of isolation channels for isolated systems. The multichannel configuration block diagram is shown in . The integration of receive and transmit FIFOs for HART communication enables easy scalability in multichannel configurations using the SPI only interface. CSCSAFEx82H1ALARM Multichannel Configuration Multichannel Configuration Typical Application This design example shows a loop-powered, 4-mA to 20-mA field transmitter featuring the AFE882H1. The AFE782H1 can also be used in this design for lower-resolution applications. This design example creates a simple HART-enabled loop controller that can be used for most field sensors in two-wire, current-loop applications. The design accepts bus voltages from 15 V to 36 V, while regulating the loop-current representation of a sensor to a post-calibration accuracy of less than 0.1% full-scale range (FSR) of total error at room temperature. The high integration in the system allows for a compact circuit, making this device an excellent choice for field transmitters where space is a concern. In field-transmitter applications, the current-loop transmitter, microcontroller, sensors, and analog front end are all required to consume less than the minimum bus current of 3 mA. Use an efficient low-power DC/DC converter instead of an LDO in the system to extend the current budget and allow more current for sensors and the AFE. shows the schematic diagram for the loop-powered, 4-mA to 20-mA field transmitter. 4-mA to 20-mA Current Transmitter AFEx82H1 in a 4-mA to 20-mA Current Transmitter Design Requirements The design requirements are: Transmitter with a current output range of 4 mA to 20 mA to represent a process variable signal Out-of-range current output capability below 3.6 mA and above 21 mA for NAMUR NE43 sensor fault signal levels Total on-board current less than or equal to 3 mA to operate the board, but allow for low out-of-range outputs Operation with standard industrial automation supply voltages from 15 V to 36 V Current and voltage outputs with TUE less than 0.5% at 25°C after calibration Detailed Design Procedure shows a block diagram of a loop-powered, 4-mA to 20-mA current transmitter. Block Diagram of a Loop-Powered, 4-mA to 20-mA Current Transmitter The terminals connected to the loop are shown on the right side of the block diagram. This connection to the loop powers the entire transmitter. A bridge rectifier at the input protects against reverse connection to the loop. The rectified loop voltage powers a start-up circuit that provides power to an LDO, that in turn powers the AFE882H1 and an MCU. The AFE882H1 controls the loop current through the voltage-to-current (V-to-I) converter block. The DAC voltage sets the output from 0 V to 2.5 V. The output is sent through a V-to-I converter block using an OPA333 and an NPN bipolar junction transistor (BJT). The HART signal is not received at the positive terminal of the 4-mA to 20-mA connections, but instead is received after the loop-protection rectifier. This HART signal input is capacitively coupled to this LOOP+ internal node of the circuit as shown in . The HART signal output is modulated onto the loop current from the AFE882H1 through the V-to-I converter circuit. Current Loop Control The DAC of the AFE882H1 sets an output voltage from 0 V to 2.5 V. shows the V-to-I circuit that sets the loop current from the DAC output voltage. Current Loop Control for the AFE882H1 Transmitter In this circuit, the loop current is set by the addition of the currents of V-to-I conversion from the output of VREFIO and the DAC VOUT. The current generated from these AFE882H1 outputs are analyzed separately. First, the voltage from VREFIO is placed across a 412-kΩ resistor. This 1.25-V reference voltage creates a current that is directed into the summing node of an OPA333 amplifier that is set to ground. The voltage at LOOP– contributed from this current is calculated in . V L O O P – =   – V V R E F I O 412   k Ω × 20   k Ω =   – 1.25   V × 0.04854 = – 0.06068   V From the feedback of the OPA333, the loop voltage from is placed across the 20-Ω resistor and sets the current through the loop as shows. I L O O P _ V R E F I O = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   0.06068   V × ( 1 20   Ω   +   1 20   k Ω   ) =   3.037   m A This 3-mA current acts as a starting current for the loop. When the AFE882H1 DAC output is 0 V, this is the current on the loop. In addition to this initial current, the AFE882H1 DAC output also controls the loop current. The VOUT voltage is set across 120 kΩ of resistance (from the 20 kΩ plus 100 kΩ of series resistance). The opposite end of the 120 kΩ of resistance is set to ground by the feedback of the OPA333. Similar to the calculations in and , the voltage at VOUT sets a loop current, as and show. V L O O P – = – V O U T 120   k Ω   ×   20   k Ω   =   – V O U T   ×   0.1667 I L O O P _ V O U T = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   V O U T ×   0.1667   × ( 1 20   Ω   +   1 20   k Ω   ) When the DAC output voltage is set to 0 V, the contribution to the loop current is basically 0 mA. When the DAC output voltage is set to 2.5 V, the contribution to the loop current is 20.85 mA. As mentioned previously, the total loop current is the sum of the contribution of the current created from the VREFIO voltage and the VOUT voltage. Using these voltages, the loop current has a range from 3.037 mA to 23.89 mA. The AFE882H1 DAC output voltage is set through a 16-bit output code. Therefore, this final conversion from the DAC code to the loop current is set based on . I L O O P =   I L O O P _ V R E F I O + I L O O P _ V O U T   = 3.037   m A   +   ( D A C   C o d e × 20.85   m A 2 16 ) In 4‑mA to 20‑mA systems, the nominal output operates from 4 mA as the low output and 20 mA as the high output. However, systems sometimes use current outputs that are outside this range to indicate different error conditions. Loop currents of 3.375 mA and 21.75 mA are often used to indicate different loop errors. shows different loop output currents, along with the DAC code and voltages used. DAC Voltage Output and Loop Current Based on DAC Output Codes OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA) DAC minimum 0x0000 0 3.037 Error low 0x0426 0.04051 3.375 In-range minimum 0x0BD2 0.1154 4 In-range midscale 0x6E07 1.0745 12 In-range maximum 0xD03C 2.0335 20 Error high 0xE5B7 2.2433 21.75 DAC maximum 0xFFFF 2.5 23.891 Among the passive devices included in the design, choose current-setting resistors with tight tolerances to achieve high accuracy and low drift. These resistors discussed in the previous equations are primarily responsible for setting the gain of the current loop, and therefore, the current magnitude of the loop. HART Connections Connections of the HART signal to the loop are done through the AFE882H1 MOD_OUT and RX_IN pins. Similar to converting the VOUT pin voltage to the loop current magnitude, the HART output from the MOD_OUT pin is converted from a voltage to a current. A dc-blocking capacitor of 1000 pF is used to couple in the HART signal, without the dc output offset from the MOD_OUT pin. From MOD_OUT, the HART sinusoid nominal output is 500 mVPP. shows that this VMOD HART sinusoid voltage is set across a 499-kΩ resistor to create signal voltage VLOOPAC superimposed onto VLOOP–. V L O O P _ A C = V M O D 499   k Ω   ×   20   k Ω   =   500   m V P P 499   k Ω   ×   20   k Ω =   20.04   m V P P   The VLOOP_AC voltage sets the HART-modulated loop current that flows from ground to LOOP– through the 20-Ω resistor. This current is sourced from ground but controlled by the current sunk from Q4 coming from the start-up circuit. calculates the total loop current based on the 20 mVPP of VLOOP_AC. I L O O P _ A C =   V L O O P _ A C × ( 1 20   Ω   +   1 20   k Ω   )   =   1   m A P P Using the 1000-pF capacitor as a dc-blocking capacitor and the 499-kΩ resistor, the 500-mVPP MOD_OUT signal is converted to a 1-mAPP HART signal on the current loop. HART signals are received by the AFE882H1 through the RX_IN pin. A dc-blocking capacitor for the HART input at RX_IN is shown with a series resistance of 1 kΩ in . A diode clamps the pin to the device supply and the resistance limits the input current. This configuration protects the RX_IN from damage from an overvoltage event at the start up of the circuit. Input Protection and Rectification shows the simple protection scheme implemented in the design to mitigate issues that arise from voltage and current transients on the bus. These transients have two main components: high-frequency and high-energy. These two components can be leveraged with a strategy of attenuation and diversion by the protection circuitry to deliver robust immunity. Loop Input Protection Attenuation uses passive components, primarily resistors and capacitors, to attenuate high-frequency transients and to limit series current. Use ferrite beads to maintain dc accuracy while still delivering the ability to limit current from high-frequency transients. This circuit uses a capacitor placed across the input terminals, as well as ferrite beads in series with the terminals. Diversion capitalizes on the high-voltage properties of the transient signals by using a diode to clamp the transient within supply voltages, or to divert the energy away from the system. Transient voltage suppressor (TVS) diodes help protect against transients because TVS diodes break down very quickly and often feature high power ratings that are critical to survive multiple transient strikes. A rectifier is also implemented for reverse polarity protection so that the design can be connected to the bus regardless of the pin orientation or polarity without damage to the design. System Current Budget Power consumption is an important consideration when designing two-wire transmitters. Power supplied from the loop must power all the circuitry related to the transmitter and sensor. The minimum loop current in two-wire applications is typically 4 mA. However, for error indications, this current is as low as 3.375 mA. Therefore, the power budget of all transducer circuitry is designed to be less than the maximum allowable system power budget of 3 mA. #GUID-CAE82FB7-B01A-4571-9D73-DAAED50E22B5/TABLE_B41_5GJ_RRB lists the specified maximum quiescent current of all included active components (provided from the respective data sheets). Typical Component Currents DEVICE DESCRIPTION TYPICAL CURRENT (µA) TPS7A0533 LDO 4 AFE882H1 16-bit DAC 180 OPA333 (2) Operational amplifier 17 (each) MSP430 Microcontroller Dependent on firmware Application Curves DAC Code to Loop Current RTS Start Timing RTS Stop Timing CD Start Timing CD Stop Timing Typical Application This design example shows a loop-powered, 4-mA to 20-mA field transmitter featuring the AFE882H1. The AFE782H1 can also be used in this design for lower-resolution applications. This design example creates a simple HART-enabled loop controller that can be used for most field sensors in two-wire, current-loop applications. The design accepts bus voltages from 15 V to 36 V, while regulating the loop-current representation of a sensor to a post-calibration accuracy of less than 0.1% full-scale range (FSR) of total error at room temperature. The high integration in the system allows for a compact circuit, making this device an excellent choice for field transmitters where space is a concern. In field-transmitter applications, the current-loop transmitter, microcontroller, sensors, and analog front end are all required to consume less than the minimum bus current of 3 mA. Use an efficient low-power DC/DC converter instead of an LDO in the system to extend the current budget and allow more current for sensors and the AFE. shows the schematic diagram for the loop-powered, 4-mA to 20-mA field transmitter. This design example shows a loop-powered, 4-mA to 20-mA field transmitter featuring the AFE882H1. The AFE782H1 can also be used in this design for lower-resolution applications. This design example creates a simple HART-enabled loop controller that can be used for most field sensors in two-wire, current-loop applications. The design accepts bus voltages from 15 V to 36 V, while regulating the loop-current representation of a sensor to a post-calibration accuracy of less than 0.1% full-scale range (FSR) of total error at room temperature. The high integration in the system allows for a compact circuit, making this device an excellent choice for field transmitters where space is a concern. In field-transmitter applications, the current-loop transmitter, microcontroller, sensors, and analog front end are all required to consume less than the minimum bus current of 3 mA. Use an efficient low-power DC/DC converter instead of an LDO in the system to extend the current budget and allow more current for sensors and the AFE. shows the schematic diagram for the loop-powered, 4-mA to 20-mA field transmitter. This design example shows a loop-powered, 4-mA to 20-mA field transmitter featuring the AFE882H1. The AFE782H1 can also be used in this design for lower-resolution applications.This design example creates a simple HART-enabled loop controller that can be used for most field sensors in two-wire, current-loop applications. The design accepts bus voltages from 15 V to 36 V, while regulating the loop-current representation of a sensor to a post-calibration accuracy of less than 0.1% full-scale range (FSR) of total error at room temperature. The high integration in the system allows for a compact circuit, making this device an excellent choice for field transmitters where space is a concern. In field-transmitter applications, the current-loop transmitter, microcontroller, sensors, and analog front end are all required to consume less than the minimum bus current of 3 mA. Use an efficient low-power DC/DC converter instead of an LDO in the system to extend the current budget and allow more current for sensors and the AFE. shows the schematic diagram for the loop-powered, 4-mA to 20-mA field transmitter. 4-mA to 20-mA Current Transmitter AFEx82H1 in a 4-mA to 20-mA Current Transmitter Design Requirements The design requirements are: Transmitter with a current output range of 4 mA to 20 mA to represent a process variable signal Out-of-range current output capability below 3.6 mA and above 21 mA for NAMUR NE43 sensor fault signal levels Total on-board current less than or equal to 3 mA to operate the board, but allow for low out-of-range outputs Operation with standard industrial automation supply voltages from 15 V to 36 V Current and voltage outputs with TUE less than 0.5% at 25°C after calibration Detailed Design Procedure shows a block diagram of a loop-powered, 4-mA to 20-mA current transmitter. Block Diagram of a Loop-Powered, 4-mA to 20-mA Current Transmitter The terminals connected to the loop are shown on the right side of the block diagram. This connection to the loop powers the entire transmitter. A bridge rectifier at the input protects against reverse connection to the loop. The rectified loop voltage powers a start-up circuit that provides power to an LDO, that in turn powers the AFE882H1 and an MCU. The AFE882H1 controls the loop current through the voltage-to-current (V-to-I) converter block. The DAC voltage sets the output from 0 V to 2.5 V. The output is sent through a V-to-I converter block using an OPA333 and an NPN bipolar junction transistor (BJT). The HART signal is not received at the positive terminal of the 4-mA to 20-mA connections, but instead is received after the loop-protection rectifier. This HART signal input is capacitively coupled to this LOOP+ internal node of the circuit as shown in . The HART signal output is modulated onto the loop current from the AFE882H1 through the V-to-I converter circuit. Current Loop Control The DAC of the AFE882H1 sets an output voltage from 0 V to 2.5 V. shows the V-to-I circuit that sets the loop current from the DAC output voltage. Current Loop Control for the AFE882H1 Transmitter In this circuit, the loop current is set by the addition of the currents of V-to-I conversion from the output of VREFIO and the DAC VOUT. The current generated from these AFE882H1 outputs are analyzed separately. First, the voltage from VREFIO is placed across a 412-kΩ resistor. This 1.25-V reference voltage creates a current that is directed into the summing node of an OPA333 amplifier that is set to ground. The voltage at LOOP– contributed from this current is calculated in . V L O O P – =   – V V R E F I O 412   k Ω × 20   k Ω =   – 1.25   V × 0.04854 = – 0.06068   V From the feedback of the OPA333, the loop voltage from is placed across the 20-Ω resistor and sets the current through the loop as shows. I L O O P _ V R E F I O = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   0.06068   V × ( 1 20   Ω   +   1 20   k Ω   ) =   3.037   m A This 3-mA current acts as a starting current for the loop. When the AFE882H1 DAC output is 0 V, this is the current on the loop. In addition to this initial current, the AFE882H1 DAC output also controls the loop current. The VOUT voltage is set across 120 kΩ of resistance (from the 20 kΩ plus 100 kΩ of series resistance). The opposite end of the 120 kΩ of resistance is set to ground by the feedback of the OPA333. Similar to the calculations in and , the voltage at VOUT sets a loop current, as and show. V L O O P – = – V O U T 120   k Ω   ×   20   k Ω   =   – V O U T   ×   0.1667 I L O O P _ V O U T = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   V O U T ×   0.1667   × ( 1 20   Ω   +   1 20   k Ω   ) When the DAC output voltage is set to 0 V, the contribution to the loop current is basically 0 mA. When the DAC output voltage is set to 2.5 V, the contribution to the loop current is 20.85 mA. As mentioned previously, the total loop current is the sum of the contribution of the current created from the VREFIO voltage and the VOUT voltage. Using these voltages, the loop current has a range from 3.037 mA to 23.89 mA. The AFE882H1 DAC output voltage is set through a 16-bit output code. Therefore, this final conversion from the DAC code to the loop current is set based on . I L O O P =   I L O O P _ V R E F I O + I L O O P _ V O U T   = 3.037   m A   +   ( D A C   C o d e × 20.85   m A 2 16 ) In 4‑mA to 20‑mA systems, the nominal output operates from 4 mA as the low output and 20 mA as the high output. However, systems sometimes use current outputs that are outside this range to indicate different error conditions. Loop currents of 3.375 mA and 21.75 mA are often used to indicate different loop errors. shows different loop output currents, along with the DAC code and voltages used. DAC Voltage Output and Loop Current Based on DAC Output Codes OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA) DAC minimum 0x0000 0 3.037 Error low 0x0426 0.04051 3.375 In-range minimum 0x0BD2 0.1154 4 In-range midscale 0x6E07 1.0745 12 In-range maximum 0xD03C 2.0335 20 Error high 0xE5B7 2.2433 21.75 DAC maximum 0xFFFF 2.5 23.891 Among the passive devices included in the design, choose current-setting resistors with tight tolerances to achieve high accuracy and low drift. These resistors discussed in the previous equations are primarily responsible for setting the gain of the current loop, and therefore, the current magnitude of the loop. HART Connections Connections of the HART signal to the loop are done through the AFE882H1 MOD_OUT and RX_IN pins. Similar to converting the VOUT pin voltage to the loop current magnitude, the HART output from the MOD_OUT pin is converted from a voltage to a current. A dc-blocking capacitor of 1000 pF is used to couple in the HART signal, without the dc output offset from the MOD_OUT pin. From MOD_OUT, the HART sinusoid nominal output is 500 mVPP. shows that this VMOD HART sinusoid voltage is set across a 499-kΩ resistor to create signal voltage VLOOPAC superimposed onto VLOOP–. V L O O P _ A C = V M O D 499   k Ω   ×   20   k Ω   =   500   m V P P 499   k Ω   ×   20   k Ω =   20.04   m V P P   The VLOOP_AC voltage sets the HART-modulated loop current that flows from ground to LOOP– through the 20-Ω resistor. This current is sourced from ground but controlled by the current sunk from Q4 coming from the start-up circuit. calculates the total loop current based on the 20 mVPP of VLOOP_AC. I L O O P _ A C =   V L O O P _ A C × ( 1 20   Ω   +   1 20   k Ω   )   =   1   m A P P Using the 1000-pF capacitor as a dc-blocking capacitor and the 499-kΩ resistor, the 500-mVPP MOD_OUT signal is converted to a 1-mAPP HART signal on the current loop. HART signals are received by the AFE882H1 through the RX_IN pin. A dc-blocking capacitor for the HART input at RX_IN is shown with a series resistance of 1 kΩ in . A diode clamps the pin to the device supply and the resistance limits the input current. This configuration protects the RX_IN from damage from an overvoltage event at the start up of the circuit. Input Protection and Rectification shows the simple protection scheme implemented in the design to mitigate issues that arise from voltage and current transients on the bus. These transients have two main components: high-frequency and high-energy. These two components can be leveraged with a strategy of attenuation and diversion by the protection circuitry to deliver robust immunity. Loop Input Protection Attenuation uses passive components, primarily resistors and capacitors, to attenuate high-frequency transients and to limit series current. Use ferrite beads to maintain dc accuracy while still delivering the ability to limit current from high-frequency transients. This circuit uses a capacitor placed across the input terminals, as well as ferrite beads in series with the terminals. Diversion capitalizes on the high-voltage properties of the transient signals by using a diode to clamp the transient within supply voltages, or to divert the energy away from the system. Transient voltage suppressor (TVS) diodes help protect against transients because TVS diodes break down very quickly and often feature high power ratings that are critical to survive multiple transient strikes. A rectifier is also implemented for reverse polarity protection so that the design can be connected to the bus regardless of the pin orientation or polarity without damage to the design. System Current Budget Power consumption is an important consideration when designing two-wire transmitters. Power supplied from the loop must power all the circuitry related to the transmitter and sensor. The minimum loop current in two-wire applications is typically 4 mA. However, for error indications, this current is as low as 3.375 mA. Therefore, the power budget of all transducer circuitry is designed to be less than the maximum allowable system power budget of 3 mA. #GUID-CAE82FB7-B01A-4571-9D73-DAAED50E22B5/TABLE_B41_5GJ_RRB lists the specified maximum quiescent current of all included active components (provided from the respective data sheets). Typical Component Currents DEVICE DESCRIPTION TYPICAL CURRENT (µA) TPS7A0533 LDO 4 AFE882H1 16-bit DAC 180 OPA333 (2) Operational amplifier 17 (each) MSP430 Microcontroller Dependent on firmware Application Curves DAC Code to Loop Current RTS Start Timing RTS Stop Timing CD Start Timing CD Stop Timing 4-mA to 20-mA Current Transmitter AFEx82H1 in a 4-mA to 20-mA Current Transmitter AFEx82H1 in a 4-mA to 20-mA Current Transmitter AFEx82H1 in a 4-mA to 20-mA Current Transmitter AFEx82H1 in a 4-mA to 20-mA Current TransmitterAFEx82H1 Design Requirements The design requirements are: Transmitter with a current output range of 4 mA to 20 mA to represent a process variable signal Out-of-range current output capability below 3.6 mA and above 21 mA for NAMUR NE43 sensor fault signal levels Total on-board current less than or equal to 3 mA to operate the board, but allow for low out-of-range outputs Operation with standard industrial automation supply voltages from 15 V to 36 V Current and voltage outputs with TUE less than 0.5% at 25°C after calibration Design Requirements The design requirements are: Transmitter with a current output range of 4 mA to 20 mA to represent a process variable signal Out-of-range current output capability below 3.6 mA and above 21 mA for NAMUR NE43 sensor fault signal levels Total on-board current less than or equal to 3 mA to operate the board, but allow for low out-of-range outputs Operation with standard industrial automation supply voltages from 15 V to 36 V Current and voltage outputs with TUE less than 0.5% at 25°C after calibration The design requirements are: Transmitter with a current output range of 4 mA to 20 mA to represent a process variable signal Out-of-range current output capability below 3.6 mA and above 21 mA for NAMUR NE43 sensor fault signal levels Total on-board current less than or equal to 3 mA to operate the board, but allow for low out-of-range outputs Operation with standard industrial automation supply voltages from 15 V to 36 V Current and voltage outputs with TUE less than 0.5% at 25°C after calibration The design requirements are: Transmitter with a current output range of 4 mA to 20 mA to represent a process variable signal Out-of-range current output capability below 3.6 mA and above 21 mA for NAMUR NE43 sensor fault signal levels Total on-board current less than or equal to 3 mA to operate the board, but allow for low out-of-range outputs Operation with standard industrial automation supply voltages from 15 V to 36 V Current and voltage outputs with TUE less than 0.5% at 25°C after calibration Transmitter with a current output range of 4 mA to 20 mA to represent a process variable signalOut-of-range current output capability below 3.6 mA and above 21 mA for NAMUR NE43 sensor fault signal levelsTotal on-board current less than or equal to 3 mA to operate the board, but allow for low out-of-range outputsOperation with standard industrial automation supply voltages from 15 V to 36 VCurrent and voltage outputs with TUE less than 0.5% at 25°C after calibration Detailed Design Procedure shows a block diagram of a loop-powered, 4-mA to 20-mA current transmitter. Block Diagram of a Loop-Powered, 4-mA to 20-mA Current Transmitter The terminals connected to the loop are shown on the right side of the block diagram. This connection to the loop powers the entire transmitter. A bridge rectifier at the input protects against reverse connection to the loop. The rectified loop voltage powers a start-up circuit that provides power to an LDO, that in turn powers the AFE882H1 and an MCU. The AFE882H1 controls the loop current through the voltage-to-current (V-to-I) converter block. The DAC voltage sets the output from 0 V to 2.5 V. The output is sent through a V-to-I converter block using an OPA333 and an NPN bipolar junction transistor (BJT). The HART signal is not received at the positive terminal of the 4-mA to 20-mA connections, but instead is received after the loop-protection rectifier. This HART signal input is capacitively coupled to this LOOP+ internal node of the circuit as shown in . The HART signal output is modulated onto the loop current from the AFE882H1 through the V-to-I converter circuit. Current Loop Control The DAC of the AFE882H1 sets an output voltage from 0 V to 2.5 V. shows the V-to-I circuit that sets the loop current from the DAC output voltage. Current Loop Control for the AFE882H1 Transmitter In this circuit, the loop current is set by the addition of the currents of V-to-I conversion from the output of VREFIO and the DAC VOUT. The current generated from these AFE882H1 outputs are analyzed separately. First, the voltage from VREFIO is placed across a 412-kΩ resistor. This 1.25-V reference voltage creates a current that is directed into the summing node of an OPA333 amplifier that is set to ground. The voltage at LOOP– contributed from this current is calculated in . V L O O P – =   – V V R E F I O 412   k Ω × 20   k Ω =   – 1.25   V × 0.04854 = – 0.06068   V From the feedback of the OPA333, the loop voltage from is placed across the 20-Ω resistor and sets the current through the loop as shows. I L O O P _ V R E F I O = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   0.06068   V × ( 1 20   Ω   +   1 20   k Ω   ) =   3.037   m A This 3-mA current acts as a starting current for the loop. When the AFE882H1 DAC output is 0 V, this is the current on the loop. In addition to this initial current, the AFE882H1 DAC output also controls the loop current. The VOUT voltage is set across 120 kΩ of resistance (from the 20 kΩ plus 100 kΩ of series resistance). The opposite end of the 120 kΩ of resistance is set to ground by the feedback of the OPA333. Similar to the calculations in and , the voltage at VOUT sets a loop current, as and show. V L O O P – = – V O U T 120   k Ω   ×   20   k Ω   =   – V O U T   ×   0.1667 I L O O P _ V O U T = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   V O U T ×   0.1667   × ( 1 20   Ω   +   1 20   k Ω   ) When the DAC output voltage is set to 0 V, the contribution to the loop current is basically 0 mA. When the DAC output voltage is set to 2.5 V, the contribution to the loop current is 20.85 mA. As mentioned previously, the total loop current is the sum of the contribution of the current created from the VREFIO voltage and the VOUT voltage. Using these voltages, the loop current has a range from 3.037 mA to 23.89 mA. The AFE882H1 DAC output voltage is set through a 16-bit output code. Therefore, this final conversion from the DAC code to the loop current is set based on . I L O O P =   I L O O P _ V R E F I O + I L O O P _ V O U T   = 3.037   m A   +   ( D A C   C o d e × 20.85   m A 2 16 ) In 4‑mA to 20‑mA systems, the nominal output operates from 4 mA as the low output and 20 mA as the high output. However, systems sometimes use current outputs that are outside this range to indicate different error conditions. Loop currents of 3.375 mA and 21.75 mA are often used to indicate different loop errors. shows different loop output currents, along with the DAC code and voltages used. DAC Voltage Output and Loop Current Based on DAC Output Codes OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA) DAC minimum 0x0000 0 3.037 Error low 0x0426 0.04051 3.375 In-range minimum 0x0BD2 0.1154 4 In-range midscale 0x6E07 1.0745 12 In-range maximum 0xD03C 2.0335 20 Error high 0xE5B7 2.2433 21.75 DAC maximum 0xFFFF 2.5 23.891 Among the passive devices included in the design, choose current-setting resistors with tight tolerances to achieve high accuracy and low drift. These resistors discussed in the previous equations are primarily responsible for setting the gain of the current loop, and therefore, the current magnitude of the loop. HART Connections Connections of the HART signal to the loop are done through the AFE882H1 MOD_OUT and RX_IN pins. Similar to converting the VOUT pin voltage to the loop current magnitude, the HART output from the MOD_OUT pin is converted from a voltage to a current. A dc-blocking capacitor of 1000 pF is used to couple in the HART signal, without the dc output offset from the MOD_OUT pin. From MOD_OUT, the HART sinusoid nominal output is 500 mVPP. shows that this VMOD HART sinusoid voltage is set across a 499-kΩ resistor to create signal voltage VLOOPAC superimposed onto VLOOP–. V L O O P _ A C = V M O D 499   k Ω   ×   20   k Ω   =   500   m V P P 499   k Ω   ×   20   k Ω =   20.04   m V P P   The VLOOP_AC voltage sets the HART-modulated loop current that flows from ground to LOOP– through the 20-Ω resistor. This current is sourced from ground but controlled by the current sunk from Q4 coming from the start-up circuit. calculates the total loop current based on the 20 mVPP of VLOOP_AC. I L O O P _ A C =   V L O O P _ A C × ( 1 20   Ω   +   1 20   k Ω   )   =   1   m A P P Using the 1000-pF capacitor as a dc-blocking capacitor and the 499-kΩ resistor, the 500-mVPP MOD_OUT signal is converted to a 1-mAPP HART signal on the current loop. HART signals are received by the AFE882H1 through the RX_IN pin. A dc-blocking capacitor for the HART input at RX_IN is shown with a series resistance of 1 kΩ in . A diode clamps the pin to the device supply and the resistance limits the input current. This configuration protects the RX_IN from damage from an overvoltage event at the start up of the circuit. Input Protection and Rectification shows the simple protection scheme implemented in the design to mitigate issues that arise from voltage and current transients on the bus. These transients have two main components: high-frequency and high-energy. These two components can be leveraged with a strategy of attenuation and diversion by the protection circuitry to deliver robust immunity. Loop Input Protection Attenuation uses passive components, primarily resistors and capacitors, to attenuate high-frequency transients and to limit series current. Use ferrite beads to maintain dc accuracy while still delivering the ability to limit current from high-frequency transients. This circuit uses a capacitor placed across the input terminals, as well as ferrite beads in series with the terminals. Diversion capitalizes on the high-voltage properties of the transient signals by using a diode to clamp the transient within supply voltages, or to divert the energy away from the system. Transient voltage suppressor (TVS) diodes help protect against transients because TVS diodes break down very quickly and often feature high power ratings that are critical to survive multiple transient strikes. A rectifier is also implemented for reverse polarity protection so that the design can be connected to the bus regardless of the pin orientation or polarity without damage to the design. System Current Budget Power consumption is an important consideration when designing two-wire transmitters. Power supplied from the loop must power all the circuitry related to the transmitter and sensor. The minimum loop current in two-wire applications is typically 4 mA. However, for error indications, this current is as low as 3.375 mA. Therefore, the power budget of all transducer circuitry is designed to be less than the maximum allowable system power budget of 3 mA. #GUID-CAE82FB7-B01A-4571-9D73-DAAED50E22B5/TABLE_B41_5GJ_RRB lists the specified maximum quiescent current of all included active components (provided from the respective data sheets). Typical Component Currents DEVICE DESCRIPTION TYPICAL CURRENT (µA) TPS7A0533 LDO 4 AFE882H1 16-bit DAC 180 OPA333 (2) Operational amplifier 17 (each) MSP430 Microcontroller Dependent on firmware Detailed Design Procedure shows a block diagram of a loop-powered, 4-mA to 20-mA current transmitter. Block Diagram of a Loop-Powered, 4-mA to 20-mA Current Transmitter The terminals connected to the loop are shown on the right side of the block diagram. This connection to the loop powers the entire transmitter. A bridge rectifier at the input protects against reverse connection to the loop. The rectified loop voltage powers a start-up circuit that provides power to an LDO, that in turn powers the AFE882H1 and an MCU. The AFE882H1 controls the loop current through the voltage-to-current (V-to-I) converter block. The DAC voltage sets the output from 0 V to 2.5 V. The output is sent through a V-to-I converter block using an OPA333 and an NPN bipolar junction transistor (BJT). The HART signal is not received at the positive terminal of the 4-mA to 20-mA connections, but instead is received after the loop-protection rectifier. This HART signal input is capacitively coupled to this LOOP+ internal node of the circuit as shown in . The HART signal output is modulated onto the loop current from the AFE882H1 through the V-to-I converter circuit. shows a block diagram of a loop-powered, 4-mA to 20-mA current transmitter. Block Diagram of a Loop-Powered, 4-mA to 20-mA Current Transmitter The terminals connected to the loop are shown on the right side of the block diagram. This connection to the loop powers the entire transmitter. A bridge rectifier at the input protects against reverse connection to the loop. The rectified loop voltage powers a start-up circuit that provides power to an LDO, that in turn powers the AFE882H1 and an MCU. The AFE882H1 controls the loop current through the voltage-to-current (V-to-I) converter block. The DAC voltage sets the output from 0 V to 2.5 V. The output is sent through a V-to-I converter block using an OPA333 and an NPN bipolar junction transistor (BJT). The HART signal is not received at the positive terminal of the 4-mA to 20-mA connections, but instead is received after the loop-protection rectifier. This HART signal input is capacitively coupled to this LOOP+ internal node of the circuit as shown in . The HART signal output is modulated onto the loop current from the AFE882H1 through the V-to-I converter circuit. shows a block diagram of a loop-powered, 4-mA to 20-mA current transmitter. Block Diagram of a Loop-Powered, 4-mA to 20-mA Current Transmitter Block Diagram of a Loop-Powered, 4-mA to 20-mA Current TransmitterThe terminals connected to the loop are shown on the right side of the block diagram. This connection to the loop powers the entire transmitter. A bridge rectifier at the input protects against reverse connection to the loop. The rectified loop voltage powers a start-up circuit that provides power to an LDO, that in turn powers the AFE882H1 and an MCU.AFE882H1The AFE882H1 controls the loop current through the voltage-to-current (V-to-I) converter block. The DAC voltage sets the output from 0 V to 2.5 V. The output is sent through a V-to-I converter block using an OPA333 and an NPN bipolar junction transistor (BJT). AFE882H1OPA333The HART signal is not received at the positive terminal of the 4-mA to 20-mA connections, but instead is received after the loop-protection rectifier. This HART signal input is capacitively coupled to this LOOP+ internal node of the circuit as shown in . The HART signal output is modulated onto the loop current from the AFE882H1 through the V-to-I converter circuit.AFE882H1 Current Loop Control The DAC of the AFE882H1 sets an output voltage from 0 V to 2.5 V. shows the V-to-I circuit that sets the loop current from the DAC output voltage. Current Loop Control for the AFE882H1 Transmitter In this circuit, the loop current is set by the addition of the currents of V-to-I conversion from the output of VREFIO and the DAC VOUT. The current generated from these AFE882H1 outputs are analyzed separately. First, the voltage from VREFIO is placed across a 412-kΩ resistor. This 1.25-V reference voltage creates a current that is directed into the summing node of an OPA333 amplifier that is set to ground. The voltage at LOOP– contributed from this current is calculated in . V L O O P – =   – V V R E F I O 412   k Ω × 20   k Ω =   – 1.25   V × 0.04854 = – 0.06068   V From the feedback of the OPA333, the loop voltage from is placed across the 20-Ω resistor and sets the current through the loop as shows. I L O O P _ V R E F I O = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   0.06068   V × ( 1 20   Ω   +   1 20   k Ω   ) =   3.037   m A This 3-mA current acts as a starting current for the loop. When the AFE882H1 DAC output is 0 V, this is the current on the loop. In addition to this initial current, the AFE882H1 DAC output also controls the loop current. The VOUT voltage is set across 120 kΩ of resistance (from the 20 kΩ plus 100 kΩ of series resistance). The opposite end of the 120 kΩ of resistance is set to ground by the feedback of the OPA333. Similar to the calculations in and , the voltage at VOUT sets a loop current, as and show. V L O O P – = – V O U T 120   k Ω   ×   20   k Ω   =   – V O U T   ×   0.1667 I L O O P _ V O U T = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   V O U T ×   0.1667   × ( 1 20   Ω   +   1 20   k Ω   ) When the DAC output voltage is set to 0 V, the contribution to the loop current is basically 0 mA. When the DAC output voltage is set to 2.5 V, the contribution to the loop current is 20.85 mA. As mentioned previously, the total loop current is the sum of the contribution of the current created from the VREFIO voltage and the VOUT voltage. Using these voltages, the loop current has a range from 3.037 mA to 23.89 mA. The AFE882H1 DAC output voltage is set through a 16-bit output code. Therefore, this final conversion from the DAC code to the loop current is set based on . I L O O P =   I L O O P _ V R E F I O + I L O O P _ V O U T   = 3.037   m A   +   ( D A C   C o d e × 20.85   m A 2 16 ) In 4‑mA to 20‑mA systems, the nominal output operates from 4 mA as the low output and 20 mA as the high output. However, systems sometimes use current outputs that are outside this range to indicate different error conditions. Loop currents of 3.375 mA and 21.75 mA are often used to indicate different loop errors. shows different loop output currents, along with the DAC code and voltages used. DAC Voltage Output and Loop Current Based on DAC Output Codes OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA) DAC minimum 0x0000 0 3.037 Error low 0x0426 0.04051 3.375 In-range minimum 0x0BD2 0.1154 4 In-range midscale 0x6E07 1.0745 12 In-range maximum 0xD03C 2.0335 20 Error high 0xE5B7 2.2433 21.75 DAC maximum 0xFFFF 2.5 23.891 Among the passive devices included in the design, choose current-setting resistors with tight tolerances to achieve high accuracy and low drift. These resistors discussed in the previous equations are primarily responsible for setting the gain of the current loop, and therefore, the current magnitude of the loop. Current Loop Control The DAC of the AFE882H1 sets an output voltage from 0 V to 2.5 V. shows the V-to-I circuit that sets the loop current from the DAC output voltage. Current Loop Control for the AFE882H1 Transmitter In this circuit, the loop current is set by the addition of the currents of V-to-I conversion from the output of VREFIO and the DAC VOUT. The current generated from these AFE882H1 outputs are analyzed separately. First, the voltage from VREFIO is placed across a 412-kΩ resistor. This 1.25-V reference voltage creates a current that is directed into the summing node of an OPA333 amplifier that is set to ground. The voltage at LOOP– contributed from this current is calculated in . V L O O P – =   – V V R E F I O 412   k Ω × 20   k Ω =   – 1.25   V × 0.04854 = – 0.06068   V From the feedback of the OPA333, the loop voltage from is placed across the 20-Ω resistor and sets the current through the loop as shows. I L O O P _ V R E F I O = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   0.06068   V × ( 1 20   Ω   +   1 20   k Ω   ) =   3.037   m A This 3-mA current acts as a starting current for the loop. When the AFE882H1 DAC output is 0 V, this is the current on the loop. In addition to this initial current, the AFE882H1 DAC output also controls the loop current. The VOUT voltage is set across 120 kΩ of resistance (from the 20 kΩ plus 100 kΩ of series resistance). The opposite end of the 120 kΩ of resistance is set to ground by the feedback of the OPA333. Similar to the calculations in and , the voltage at VOUT sets a loop current, as and show. V L O O P – = – V O U T 120   k Ω   ×   20   k Ω   =   – V O U T   ×   0.1667 I L O O P _ V O U T = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   V O U T ×   0.1667   × ( 1 20   Ω   +   1 20   k Ω   ) When the DAC output voltage is set to 0 V, the contribution to the loop current is basically 0 mA. When the DAC output voltage is set to 2.5 V, the contribution to the loop current is 20.85 mA. As mentioned previously, the total loop current is the sum of the contribution of the current created from the VREFIO voltage and the VOUT voltage. Using these voltages, the loop current has a range from 3.037 mA to 23.89 mA. The AFE882H1 DAC output voltage is set through a 16-bit output code. Therefore, this final conversion from the DAC code to the loop current is set based on . I L O O P =   I L O O P _ V R E F I O + I L O O P _ V O U T   = 3.037   m A   +   ( D A C   C o d e × 20.85   m A 2 16 ) In 4‑mA to 20‑mA systems, the nominal output operates from 4 mA as the low output and 20 mA as the high output. However, systems sometimes use current outputs that are outside this range to indicate different error conditions. Loop currents of 3.375 mA and 21.75 mA are often used to indicate different loop errors. shows different loop output currents, along with the DAC code and voltages used. DAC Voltage Output and Loop Current Based on DAC Output Codes OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA) DAC minimum 0x0000 0 3.037 Error low 0x0426 0.04051 3.375 In-range minimum 0x0BD2 0.1154 4 In-range midscale 0x6E07 1.0745 12 In-range maximum 0xD03C 2.0335 20 Error high 0xE5B7 2.2433 21.75 DAC maximum 0xFFFF 2.5 23.891 Among the passive devices included in the design, choose current-setting resistors with tight tolerances to achieve high accuracy and low drift. These resistors discussed in the previous equations are primarily responsible for setting the gain of the current loop, and therefore, the current magnitude of the loop. The DAC of the AFE882H1 sets an output voltage from 0 V to 2.5 V. shows the V-to-I circuit that sets the loop current from the DAC output voltage. Current Loop Control for the AFE882H1 Transmitter In this circuit, the loop current is set by the addition of the currents of V-to-I conversion from the output of VREFIO and the DAC VOUT. The current generated from these AFE882H1 outputs are analyzed separately. First, the voltage from VREFIO is placed across a 412-kΩ resistor. This 1.25-V reference voltage creates a current that is directed into the summing node of an OPA333 amplifier that is set to ground. The voltage at LOOP– contributed from this current is calculated in . V L O O P – =   – V V R E F I O 412   k Ω × 20   k Ω =   – 1.25   V × 0.04854 = – 0.06068   V From the feedback of the OPA333, the loop voltage from is placed across the 20-Ω resistor and sets the current through the loop as shows. I L O O P _ V R E F I O = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   0.06068   V × ( 1 20   Ω   +   1 20   k Ω   ) =   3.037   m A This 3-mA current acts as a starting current for the loop. When the AFE882H1 DAC output is 0 V, this is the current on the loop. In addition to this initial current, the AFE882H1 DAC output also controls the loop current. The VOUT voltage is set across 120 kΩ of resistance (from the 20 kΩ plus 100 kΩ of series resistance). The opposite end of the 120 kΩ of resistance is set to ground by the feedback of the OPA333. Similar to the calculations in and , the voltage at VOUT sets a loop current, as and show. V L O O P – = – V O U T 120   k Ω   ×   20   k Ω   =   – V O U T   ×   0.1667 I L O O P _ V O U T = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   V O U T ×   0.1667   × ( 1 20   Ω   +   1 20   k Ω   ) When the DAC output voltage is set to 0 V, the contribution to the loop current is basically 0 mA. When the DAC output voltage is set to 2.5 V, the contribution to the loop current is 20.85 mA. As mentioned previously, the total loop current is the sum of the contribution of the current created from the VREFIO voltage and the VOUT voltage. Using these voltages, the loop current has a range from 3.037 mA to 23.89 mA. The AFE882H1 DAC output voltage is set through a 16-bit output code. Therefore, this final conversion from the DAC code to the loop current is set based on . I L O O P =   I L O O P _ V R E F I O + I L O O P _ V O U T   = 3.037   m A   +   ( D A C   C o d e × 20.85   m A 2 16 ) In 4‑mA to 20‑mA systems, the nominal output operates from 4 mA as the low output and 20 mA as the high output. However, systems sometimes use current outputs that are outside this range to indicate different error conditions. Loop currents of 3.375 mA and 21.75 mA are often used to indicate different loop errors. shows different loop output currents, along with the DAC code and voltages used. DAC Voltage Output and Loop Current Based on DAC Output Codes OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA) DAC minimum 0x0000 0 3.037 Error low 0x0426 0.04051 3.375 In-range minimum 0x0BD2 0.1154 4 In-range midscale 0x6E07 1.0745 12 In-range maximum 0xD03C 2.0335 20 Error high 0xE5B7 2.2433 21.75 DAC maximum 0xFFFF 2.5 23.891 Among the passive devices included in the design, choose current-setting resistors with tight tolerances to achieve high accuracy and low drift. These resistors discussed in the previous equations are primarily responsible for setting the gain of the current loop, and therefore, the current magnitude of the loop. The DAC of the AFE882H1 sets an output voltage from 0 V to 2.5 V. shows the V-to-I circuit that sets the loop current from the DAC output voltage.AFE882H1 Current Loop Control for the AFE882H1 Transmitter Current Loop Control for the AFE882H1 TransmitterAFE882H1In this circuit, the loop current is set by the addition of the currents of V-to-I conversion from the output of VREFIO and the DAC VOUT. The current generated from these AFE882H1 outputs are analyzed separately.AFE882H1First, the voltage from VREFIO is placed across a 412-kΩ resistor. This 1.25-V reference voltage creates a current that is directed into the summing node of an OPA333 amplifier that is set to ground. The voltage at LOOP– contributed from this current is calculated in . V L O O P – =   – V V R E F I O 412   k Ω × 20   k Ω =   – 1.25   V × 0.04854 = – 0.06068   V V L O O P – =   – V V R E F I O 412   k Ω × 20   k Ω =   – 1.25   V × 0.04854 = – 0.06068   V V L O O P – =   – V V R E F I O 412   k Ω × 20   k Ω =   – 1.25   V × 0.04854 = – 0.06068   V V L O O P – V V L O O P – LOOP–=  – V V R E F I O 412   k Ω – V V R E F I O – V V R E F I O V V V R E F I O VREFIO 412   k Ω 412 kΩ×20 kΩ= –1.25 V×0.04854=–0.06068 VFrom the feedback of the OPA333, the loop voltage from is placed across the 20-Ω resistor and sets the current through the loop as shows. I L O O P _ V R E F I O = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   0.06068   V × ( 1 20   Ω   +   1 20   k Ω   ) =   3.037   m A I L O O P _ V R E F I O = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   0.06068   V × ( 1 20   Ω   +   1 20   k Ω   ) =   3.037   m A I L O O P _ V R E F I O = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   0.06068   V × ( 1 20   Ω   +   1 20   k Ω   ) =   3.037   m A I L O O P _ V R E F I O I I L O O P _ V R E F I O LOOP_VREFIO=( – V L O O P – 20   Ω – V L O O P – – V L O O P – V V L O O P – LOOP– 20   Ω 20 Ω ) + ( – V L O O P – 20   k Ω – V L O O P – – V L O O P – V V L O O P – LOOP– 20   k Ω 20 kΩ)= 0.06068 V×( 1 20   Ω 1 1 20   Ω 20 Ω +  1 20   k Ω 1 1 20   k Ω 20 kΩ )= 3.037 mAThis 3-mA current acts as a starting current for the loop. When the AFE882H1 DAC output is 0 V, this is the current on the loop.AFE882H1In addition to this initial current, the AFE882H1 DAC output also controls the loop current. The VOUT voltage is set across 120 kΩ of resistance (from the 20 kΩ plus 100 kΩ of series resistance). The opposite end of the 120 kΩ of resistance is set to ground by the feedback of the OPA333. Similar to the calculations in and , the voltage at VOUT sets a loop current, as and show.AFE882H1 V L O O P – = – V O U T 120   k Ω   ×   20   k Ω   =   – V O U T   ×   0.1667 V L O O P – = – V O U T 120   k Ω   ×   20   k Ω   =   – V O U T   ×   0.1667 V L O O P – = – V O U T 120   k Ω   ×   20   k Ω   =   – V O U T   ×   0.1667 V L O O P – V V L O O P – LOOP–= – V O U T 120   k Ω – V O U T –VOUT 120   k Ω 120 kΩ × 20 kΩ = –VOUT × 0.1667 I L O O P _ V O U T = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   V O U T ×   0.1667   × ( 1 20   Ω   +   1 20   k Ω   ) I L O O P _ V O U T = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   V O U T ×   0.1667   × ( 1 20   Ω   +   1 20   k Ω   ) I L O O P _ V O U T = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   V O U T ×   0.1667   × ( 1 20   Ω   +   1 20   k Ω   ) I L O O P _ V O U T I I L O O P _ V O U T LOOP_VOUT=( – V L O O P – 20   Ω – V L O O P – – V L O O P – V V L O O P – LOOP– 20   Ω 20 Ω ) + ( – V L O O P – 20   k Ω – V L O O P – – V L O O P – V V L O O P – LOOP– 20   k Ω 20 kΩ)= VOUT× 0.1667 ×( 1 20   Ω 1 1 20   Ω 20 Ω +  1 20   k Ω 1 1 20   k Ω 20 kΩ )When the DAC output voltage is set to 0 V, the contribution to the loop current is basically 0 mA. When the DAC output voltage is set to 2.5 V, the contribution to the loop current is 20.85 mA.As mentioned previously, the total loop current is the sum of the contribution of the current created from the VREFIO voltage and the VOUT voltage. Using these voltages, the loop current has a range from 3.037 mA to 23.89 mA. The AFE882H1 DAC output voltage is set through a 16-bit output code. Therefore, this final conversion from the DAC code to the loop current is set based on .AFE882H1 I L O O P =   I L O O P _ V R E F I O + I L O O P _ V O U T   = 3.037   m A   +   ( D A C   C o d e × 20.85   m A 2 16 ) I L O O P =   I L O O P _ V R E F I O + I L O O P _ V O U T   = 3.037   m A   +   ( D A C   C o d e × 20.85   m A 2 16 ) I L O O P =   I L O O P _ V R E F I O + I L O O P _ V O U T   = 3.037   m A   +   ( D A C   C o d e × 20.85   m A 2 16 ) I L O O P I I L O O P LOOP=  I L O O P _ V R E F I O I I L O O P _ V R E F I O LOOP_VREFIO+ I L O O P _ V O U T I I L O O P _ V O U T LOOP_VOUT =3.037 mA + (DAC Code× 20.85   m A 2 16 20.85   m A 20.85 mA 2 16 2 16 2 2 16 16)In 4‑mA to 20‑mA systems, the nominal output operates from 4 mA as the low output and 20 mA as the high output. However, systems sometimes use current outputs that are outside this range to indicate different error conditions. Loop currents of 3.375 mA and 21.75 mA are often used to indicate different loop errors. shows different loop output currents, along with the DAC code and voltages used. DAC Voltage Output and Loop Current Based on DAC Output Codes OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA) DAC minimum 0x0000 0 3.037 Error low 0x0426 0.04051 3.375 In-range minimum 0x0BD2 0.1154 4 In-range midscale 0x6E07 1.0745 12 In-range maximum 0xD03C 2.0335 20 Error high 0xE5B7 2.2433 21.75 DAC maximum 0xFFFF 2.5 23.891 DAC Voltage Output and Loop Current Based on DAC Output Codes OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA) DAC minimum 0x0000 0 3.037 Error low 0x0426 0.04051 3.375 In-range minimum 0x0BD2 0.1154 4 In-range midscale 0x6E07 1.0745 12 In-range maximum 0xD03C 2.0335 20 Error high 0xE5B7 2.2433 21.75 DAC maximum 0xFFFF 2.5 23.891 OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA) OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA) OUTPUT CONDITIONDAC CODEDAC OUTPUT (V)LOOP CURRENT (mA) DAC minimum 0x0000 0 3.037 Error low 0x0426 0.04051 3.375 In-range minimum 0x0BD2 0.1154 4 In-range midscale 0x6E07 1.0745 12 In-range maximum 0xD03C 2.0335 20 Error high 0xE5B7 2.2433 21.75 DAC maximum 0xFFFF 2.5 23.891 DAC minimum 0x0000 0 3.037 DAC minimum0x000003.037 Error low 0x0426 0.04051 3.375 Error low0x04260.040513.375 In-range minimum 0x0BD2 0.1154 4 In-range minimum0x0BD20.11544 In-range midscale 0x6E07 1.0745 12 In-range midscale0x6E071.074512 In-range maximum 0xD03C 2.0335 20 In-range maximum0xD03C2.033520 Error high 0xE5B7 2.2433 21.75 Error high0xE5B72.243321.75 DAC maximum 0xFFFF 2.5 23.891 DAC maximum0xFFFF2.523.891Among the passive devices included in the design, choose current-setting resistors with tight tolerances to achieve high accuracy and low drift. These resistors discussed in the previous equations are primarily responsible for setting the gain of the current loop, and therefore, the current magnitude of the loop. HART Connections Connections of the HART signal to the loop are done through the AFE882H1 MOD_OUT and RX_IN pins. Similar to converting the VOUT pin voltage to the loop current magnitude, the HART output from the MOD_OUT pin is converted from a voltage to a current. A dc-blocking capacitor of 1000 pF is used to couple in the HART signal, without the dc output offset from the MOD_OUT pin. From MOD_OUT, the HART sinusoid nominal output is 500 mVPP. shows that this VMOD HART sinusoid voltage is set across a 499-kΩ resistor to create signal voltage VLOOPAC superimposed onto VLOOP–. V L O O P _ A C = V M O D 499   k Ω   ×   20   k Ω   =   500   m V P P 499   k Ω   ×   20   k Ω =   20.04   m V P P   The VLOOP_AC voltage sets the HART-modulated loop current that flows from ground to LOOP– through the 20-Ω resistor. This current is sourced from ground but controlled by the current sunk from Q4 coming from the start-up circuit. calculates the total loop current based on the 20 mVPP of VLOOP_AC. I L O O P _ A C =   V L O O P _ A C × ( 1 20   Ω   +   1 20   k Ω   )   =   1   m A P P Using the 1000-pF capacitor as a dc-blocking capacitor and the 499-kΩ resistor, the 500-mVPP MOD_OUT signal is converted to a 1-mAPP HART signal on the current loop. HART signals are received by the AFE882H1 through the RX_IN pin. A dc-blocking capacitor for the HART input at RX_IN is shown with a series resistance of 1 kΩ in . A diode clamps the pin to the device supply and the resistance limits the input current. This configuration protects the RX_IN from damage from an overvoltage event at the start up of the circuit. HART Connections Connections of the HART signal to the loop are done through the AFE882H1 MOD_OUT and RX_IN pins. Similar to converting the VOUT pin voltage to the loop current magnitude, the HART output from the MOD_OUT pin is converted from a voltage to a current. A dc-blocking capacitor of 1000 pF is used to couple in the HART signal, without the dc output offset from the MOD_OUT pin. From MOD_OUT, the HART sinusoid nominal output is 500 mVPP. shows that this VMOD HART sinusoid voltage is set across a 499-kΩ resistor to create signal voltage VLOOPAC superimposed onto VLOOP–. V L O O P _ A C = V M O D 499   k Ω   ×   20   k Ω   =   500   m V P P 499   k Ω   ×   20   k Ω =   20.04   m V P P   The VLOOP_AC voltage sets the HART-modulated loop current that flows from ground to LOOP– through the 20-Ω resistor. This current is sourced from ground but controlled by the current sunk from Q4 coming from the start-up circuit. calculates the total loop current based on the 20 mVPP of VLOOP_AC. I L O O P _ A C =   V L O O P _ A C × ( 1 20   Ω   +   1 20   k Ω   )   =   1   m A P P Using the 1000-pF capacitor as a dc-blocking capacitor and the 499-kΩ resistor, the 500-mVPP MOD_OUT signal is converted to a 1-mAPP HART signal on the current loop. HART signals are received by the AFE882H1 through the RX_IN pin. A dc-blocking capacitor for the HART input at RX_IN is shown with a series resistance of 1 kΩ in . A diode clamps the pin to the device supply and the resistance limits the input current. This configuration protects the RX_IN from damage from an overvoltage event at the start up of the circuit. Connections of the HART signal to the loop are done through the AFE882H1 MOD_OUT and RX_IN pins. Similar to converting the VOUT pin voltage to the loop current magnitude, the HART output from the MOD_OUT pin is converted from a voltage to a current. A dc-blocking capacitor of 1000 pF is used to couple in the HART signal, without the dc output offset from the MOD_OUT pin. From MOD_OUT, the HART sinusoid nominal output is 500 mVPP. shows that this VMOD HART sinusoid voltage is set across a 499-kΩ resistor to create signal voltage VLOOPAC superimposed onto VLOOP–. V L O O P _ A C = V M O D 499   k Ω   ×   20   k Ω   =   500   m V P P 499   k Ω   ×   20   k Ω =   20.04   m V P P   The VLOOP_AC voltage sets the HART-modulated loop current that flows from ground to LOOP– through the 20-Ω resistor. This current is sourced from ground but controlled by the current sunk from Q4 coming from the start-up circuit. calculates the total loop current based on the 20 mVPP of VLOOP_AC. I L O O P _ A C =   V L O O P _ A C × ( 1 20   Ω   +   1 20   k Ω   )   =   1   m A P P Using the 1000-pF capacitor as a dc-blocking capacitor and the 499-kΩ resistor, the 500-mVPP MOD_OUT signal is converted to a 1-mAPP HART signal on the current loop. HART signals are received by the AFE882H1 through the RX_IN pin. A dc-blocking capacitor for the HART input at RX_IN is shown with a series resistance of 1 kΩ in . A diode clamps the pin to the device supply and the resistance limits the input current. This configuration protects the RX_IN from damage from an overvoltage event at the start up of the circuit. Connections of the HART signal to the loop are done through the AFE882H1 MOD_OUT and RX_IN pins. Similar to converting the VOUT pin voltage to the loop current magnitude, the HART output from the MOD_OUT pin is converted from a voltage to a current. A dc-blocking capacitor of 1000 pF is used to couple in the HART signal, without the dc output offset from the MOD_OUT pin. From MOD_OUT, the HART sinusoid nominal output is 500 mVPP. shows that this VMOD HART sinusoid voltage is set across a 499-kΩ resistor to create signal voltage VLOOPAC superimposed onto VLOOP–.AFE882H1PPMODLOOPACLOOP– V L O O P _ A C = V M O D 499   k Ω   ×   20   k Ω   =   500   m V P P 499   k Ω   ×   20   k Ω =   20.04   m V P P   V L O O P _ A C = V M O D 499   k Ω   ×   20   k Ω   =   500   m V P P 499   k Ω   ×   20   k Ω =   20.04   m V P P   V L O O P _ A C = V M O D 499   k Ω   ×   20   k Ω   =   500   m V P P 499   k Ω   ×   20   k Ω =   20.04   m V P P   V L O O P _ A C V V L O O P _ A C LOOP_AC= V M O D 499   k Ω V M O D V M O D V V M O D MOD 499   k Ω 499 kΩ × 20 kΩ =  500   m V P P 499   k Ω 500   m V P P 500  m V P P m V mV P P PP 499   k Ω 499 kΩ × 20 kΩ= 20.04  m V P P m V mV P P PP The VLOOP_AC voltage sets the HART-modulated loop current that flows from ground to LOOP– through the 20-Ω resistor. This current is sourced from ground but controlled by the current sunk from Q4 coming from the start-up circuit. calculates the total loop current based on the 20 mVPP of VLOOP_AC.LOOP_ACPPLOOP_AC I L O O P _ A C =   V L O O P _ A C × ( 1 20   Ω   +   1 20   k Ω   )   =   1   m A P P I L O O P _ A C =   V L O O P _ A C × ( 1 20   Ω   +   1 20   k Ω   )   =   1   m A P P I L O O P _ A C =   V L O O P _ A C × ( 1 20   Ω   +   1 20   k Ω   )   =   1   m A P P I L O O P _ A C I I L O O P _ A C LOOP_AC=  V L O O P _ A C V V L O O P _ A C LOOP_AC×( 1 20   Ω 1 1 20   Ω 20 Ω +  1 20   k Ω 1 1 20   k Ω 20 kΩ ) = 1   m A P P   m A  mA P P PPUsing the 1000-pF capacitor as a dc-blocking capacitor and the 499-kΩ resistor, the 500-mVPP MOD_OUT signal is converted to a 1-mAPP HART signal on the current loop.PPPPHART signals are received by the AFE882H1 through the RX_IN pin. A dc-blocking capacitor for the HART input at RX_IN is shown with a series resistance of 1 kΩ in . A diode clamps the pin to the device supply and the resistance limits the input current. This configuration protects the RX_IN from damage from an overvoltage event at the start up of the circuit.AFE882H1 Input Protection and Rectification shows the simple protection scheme implemented in the design to mitigate issues that arise from voltage and current transients on the bus. These transients have two main components: high-frequency and high-energy. These two components can be leveraged with a strategy of attenuation and diversion by the protection circuitry to deliver robust immunity. Loop Input Protection Attenuation uses passive components, primarily resistors and capacitors, to attenuate high-frequency transients and to limit series current. Use ferrite beads to maintain dc accuracy while still delivering the ability to limit current from high-frequency transients. This circuit uses a capacitor placed across the input terminals, as well as ferrite beads in series with the terminals. Diversion capitalizes on the high-voltage properties of the transient signals by using a diode to clamp the transient within supply voltages, or to divert the energy away from the system. Transient voltage suppressor (TVS) diodes help protect against transients because TVS diodes break down very quickly and often feature high power ratings that are critical to survive multiple transient strikes. A rectifier is also implemented for reverse polarity protection so that the design can be connected to the bus regardless of the pin orientation or polarity without damage to the design. Input Protection and Rectification shows the simple protection scheme implemented in the design to mitigate issues that arise from voltage and current transients on the bus. These transients have two main components: high-frequency and high-energy. These two components can be leveraged with a strategy of attenuation and diversion by the protection circuitry to deliver robust immunity. Loop Input Protection Attenuation uses passive components, primarily resistors and capacitors, to attenuate high-frequency transients and to limit series current. Use ferrite beads to maintain dc accuracy while still delivering the ability to limit current from high-frequency transients. This circuit uses a capacitor placed across the input terminals, as well as ferrite beads in series with the terminals. Diversion capitalizes on the high-voltage properties of the transient signals by using a diode to clamp the transient within supply voltages, or to divert the energy away from the system. Transient voltage suppressor (TVS) diodes help protect against transients because TVS diodes break down very quickly and often feature high power ratings that are critical to survive multiple transient strikes. A rectifier is also implemented for reverse polarity protection so that the design can be connected to the bus regardless of the pin orientation or polarity without damage to the design. shows the simple protection scheme implemented in the design to mitigate issues that arise from voltage and current transients on the bus. These transients have two main components: high-frequency and high-energy. These two components can be leveraged with a strategy of attenuation and diversion by the protection circuitry to deliver robust immunity. Loop Input Protection Attenuation uses passive components, primarily resistors and capacitors, to attenuate high-frequency transients and to limit series current. Use ferrite beads to maintain dc accuracy while still delivering the ability to limit current from high-frequency transients. This circuit uses a capacitor placed across the input terminals, as well as ferrite beads in series with the terminals. Diversion capitalizes on the high-voltage properties of the transient signals by using a diode to clamp the transient within supply voltages, or to divert the energy away from the system. Transient voltage suppressor (TVS) diodes help protect against transients because TVS diodes break down very quickly and often feature high power ratings that are critical to survive multiple transient strikes. A rectifier is also implemented for reverse polarity protection so that the design can be connected to the bus regardless of the pin orientation or polarity without damage to the design. shows the simple protection scheme implemented in the design to mitigate issues that arise from voltage and current transients on the bus. These transients have two main components: high-frequency and high-energy. These two components can be leveraged with a strategy of attenuation and diversion by the protection circuitry to deliver robust immunity. Loop Input Protection Loop Input ProtectionAttenuation uses passive components, primarily resistors and capacitors, to attenuate high-frequency transients and to limit series current. Use ferrite beads to maintain dc accuracy while still delivering the ability to limit current from high-frequency transients. This circuit uses a capacitor placed across the input terminals, as well as ferrite beads in series with the terminals.Diversion capitalizes on the high-voltage properties of the transient signals by using a diode to clamp the transient within supply voltages, or to divert the energy away from the system. Transient voltage suppressor (TVS) diodes help protect against transients because TVS diodes break down very quickly and often feature high power ratings that are critical to survive multiple transient strikes.A rectifier is also implemented for reverse polarity protection so that the design can be connected to the bus regardless of the pin orientation or polarity without damage to the design. System Current Budget Power consumption is an important consideration when designing two-wire transmitters. Power supplied from the loop must power all the circuitry related to the transmitter and sensor. The minimum loop current in two-wire applications is typically 4 mA. However, for error indications, this current is as low as 3.375 mA. Therefore, the power budget of all transducer circuitry is designed to be less than the maximum allowable system power budget of 3 mA. #GUID-CAE82FB7-B01A-4571-9D73-DAAED50E22B5/TABLE_B41_5GJ_RRB lists the specified maximum quiescent current of all included active components (provided from the respective data sheets). Typical Component Currents DEVICE DESCRIPTION TYPICAL CURRENT (µA) TPS7A0533 LDO 4 AFE882H1 16-bit DAC 180 OPA333 (2) Operational amplifier 17 (each) MSP430 Microcontroller Dependent on firmware System Current Budget Power consumption is an important consideration when designing two-wire transmitters. Power supplied from the loop must power all the circuitry related to the transmitter and sensor. The minimum loop current in two-wire applications is typically 4 mA. However, for error indications, this current is as low as 3.375 mA. Therefore, the power budget of all transducer circuitry is designed to be less than the maximum allowable system power budget of 3 mA. #GUID-CAE82FB7-B01A-4571-9D73-DAAED50E22B5/TABLE_B41_5GJ_RRB lists the specified maximum quiescent current of all included active components (provided from the respective data sheets). Typical Component Currents DEVICE DESCRIPTION TYPICAL CURRENT (µA) TPS7A0533 LDO 4 AFE882H1 16-bit DAC 180 OPA333 (2) Operational amplifier 17 (each) MSP430 Microcontroller Dependent on firmware Power consumption is an important consideration when designing two-wire transmitters. Power supplied from the loop must power all the circuitry related to the transmitter and sensor. The minimum loop current in two-wire applications is typically 4 mA. However, for error indications, this current is as low as 3.375 mA. Therefore, the power budget of all transducer circuitry is designed to be less than the maximum allowable system power budget of 3 mA. #GUID-CAE82FB7-B01A-4571-9D73-DAAED50E22B5/TABLE_B41_5GJ_RRB lists the specified maximum quiescent current of all included active components (provided from the respective data sheets). Typical Component Currents DEVICE DESCRIPTION TYPICAL CURRENT (µA) TPS7A0533 LDO 4 AFE882H1 16-bit DAC 180 OPA333 (2) Operational amplifier 17 (each) MSP430 Microcontroller Dependent on firmware Power consumption is an important consideration when designing two-wire transmitters. Power supplied from the loop must power all the circuitry related to the transmitter and sensor. The minimum loop current in two-wire applications is typically 4 mA. However, for error indications, this current is as low as 3.375 mA. Therefore, the power budget of all transducer circuitry is designed to be less than the maximum allowable system power budget of 3 mA. #GUID-CAE82FB7-B01A-4571-9D73-DAAED50E22B5/TABLE_B41_5GJ_RRB lists the specified maximum quiescent current of all included active components (provided from the respective data sheets).#GUID-CAE82FB7-B01A-4571-9D73-DAAED50E22B5/TABLE_B41_5GJ_RRB Typical Component Currents DEVICE DESCRIPTION TYPICAL CURRENT (µA) TPS7A0533 LDO 4 AFE882H1 16-bit DAC 180 OPA333 (2) Operational amplifier 17 (each) MSP430 Microcontroller Dependent on firmware Typical Component Currents DEVICE DESCRIPTION TYPICAL CURRENT (µA) TPS7A0533 LDO 4 AFE882H1 16-bit DAC 180 OPA333 (2) Operational amplifier 17 (each) MSP430 Microcontroller Dependent on firmware DEVICE DESCRIPTION TYPICAL CURRENT (µA) DEVICE DESCRIPTION TYPICAL CURRENT (µA) DEVICEDESCRIPTIONTYPICAL CURRENT (µA) TPS7A0533 LDO 4 AFE882H1 16-bit DAC 180 OPA333 (2) Operational amplifier 17 (each) MSP430 Microcontroller Dependent on firmware TPS7A0533 LDO 4 TPS7A0533 TPS7A0533LDO4 AFE882H1 16-bit DAC 180 AFE882H1 AFE882H116-bit DAC180 OPA333 (2) Operational amplifier 17 (each) OPA333 (2)OPA333Operational amplifier17 (each) MSP430 Microcontroller Dependent on firmware MSP430 MSP430MicrocontrollerDependent on firmware Application Curves DAC Code to Loop Current RTS Start Timing RTS Stop Timing CD Start Timing CD Stop Timing Application Curves DAC Code to Loop Current RTS Start Timing RTS Stop Timing CD Start Timing CD Stop Timing DAC Code to Loop Current RTS Start Timing RTS Stop Timing CD Start Timing CD Stop Timing DAC Code to Loop Current RTS Start Timing RTS Stop Timing CD Start Timing CD Stop Timing DAC Code to Loop Current DAC Code to Loop Current RTS Start Timing RTS Start TimingRTS RTS Stop Timing RTS Stop TimingRTS CD Start Timing CD Start Timing CD Stop Timing CD Stop Timing Initialization Setup This section describes several recommendations to set up the AFEx82H1. The AFEx82H1 power up with the CRC enabled. If the device is intended to be run without the CRC, the CRC must be disabled by setting the CRC_EN bit to 0h in the CONFIG register. Be aware that the command to write to this register is first done with the CRC enabled. The CRC byte must be appended to the command for the device to interpret the command correctly. To disable the CRC after start up, write 0x02 0x00 0x26 0x24 to the device. The first three bytes write the command, while the last byte is the CRC byte. For more information on the CRC, see the communication description in . The AFEx82H1 also power up with the SDO pin disabled. The SDO pin is required for reading from any of the device registers, as well as reading any data from the ADC in SPI mode. The SDO pin is enabled by writing 0h into the DSDO bit in the CONFIG register. See also and . To enable the ADC, first enable the ADC buffer by writing 0h into the BUF_PD bit in the ADC_CFG register. For information about using the ADC in different modes of operation, see . Initialization Setup This section describes several recommendations to set up the AFEx82H1. The AFEx82H1 power up with the CRC enabled. If the device is intended to be run without the CRC, the CRC must be disabled by setting the CRC_EN bit to 0h in the CONFIG register. Be aware that the command to write to this register is first done with the CRC enabled. The CRC byte must be appended to the command for the device to interpret the command correctly. To disable the CRC after start up, write 0x02 0x00 0x26 0x24 to the device. The first three bytes write the command, while the last byte is the CRC byte. For more information on the CRC, see the communication description in . The AFEx82H1 also power up with the SDO pin disabled. The SDO pin is required for reading from any of the device registers, as well as reading any data from the ADC in SPI mode. The SDO pin is enabled by writing 0h into the DSDO bit in the CONFIG register. See also and . To enable the ADC, first enable the ADC buffer by writing 0h into the BUF_PD bit in the ADC_CFG register. For information about using the ADC in different modes of operation, see . This section describes several recommendations to set up the AFEx82H1. The AFEx82H1 power up with the CRC enabled. If the device is intended to be run without the CRC, the CRC must be disabled by setting the CRC_EN bit to 0h in the CONFIG register. Be aware that the command to write to this register is first done with the CRC enabled. The CRC byte must be appended to the command for the device to interpret the command correctly. To disable the CRC after start up, write 0x02 0x00 0x26 0x24 to the device. The first three bytes write the command, while the last byte is the CRC byte. For more information on the CRC, see the communication description in . The AFEx82H1 also power up with the SDO pin disabled. The SDO pin is required for reading from any of the device registers, as well as reading any data from the ADC in SPI mode. The SDO pin is enabled by writing 0h into the DSDO bit in the CONFIG register. See also and . To enable the ADC, first enable the ADC buffer by writing 0h into the BUF_PD bit in the ADC_CFG register. For information about using the ADC in different modes of operation, see . This section describes several recommendations to set up the AFEx82H1.AFEx82H1The AFEx82H1 power up with the CRC enabled. If the device is intended to be run without the CRC, the CRC must be disabled by setting the CRC_EN bit to 0h in the CONFIG register. Be aware that the command to write to this register is first done with the CRC enabled. The CRC byte must be appended to the command for the device to interpret the command correctly. To disable the CRC after start up, write 0x02 0x00 0x26 0x24 to the device. The first three bytes write the command, while the last byte is the CRC byte. For more information on the CRC, see the communication description in .AFEx82H1The AFEx82H1 also power up with the SDO pin disabled. The SDO pin is required for reading from any of the device registers, as well as reading any data from the ADC in SPI mode. The SDO pin is enabled by writing 0h into the DSDO bit in the CONFIG register. See also and .AFEx82H1To enable the ADC, first enable the ADC buffer by writing 0h into the BUF_PD bit in the ADC_CFG register. For information about using the ADC in different modes of operation, see . Power Supply Recommendations The AFEx82H1 can operate within a single-supply range of 2.7 V to 5.5 V applied to the PVDD pin. When 2.7 V to 5.5 V is provided to PVDD, an internal LDO is enabled that drives VDD internally. VDD pin must have 1 μF to 10 μF of capacitance for operation. The digital interface supply, IOVDD, can operate with a supply range of 1.71 V to 5.5 V. Switching power supplies and DC/DC converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes. This noise can easily couple into the DAC output voltage or current through various paths between the power connections and analog output. To further reduce noise, include bulk and local decoupling capacitors. The current consumption on the PVDD and IOVDD pins, the short-circuit current limit for the voltage output, and the current ranges for the current output are listed in the Electrical Characteristics . The power supply must meet the requirements listed in the Recommended Operating Conditions . Power Supply Recommendations The AFEx82H1 can operate within a single-supply range of 2.7 V to 5.5 V applied to the PVDD pin. When 2.7 V to 5.5 V is provided to PVDD, an internal LDO is enabled that drives VDD internally. VDD pin must have 1 μF to 10 μF of capacitance for operation. The digital interface supply, IOVDD, can operate with a supply range of 1.71 V to 5.5 V. Switching power supplies and DC/DC converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes. This noise can easily couple into the DAC output voltage or current through various paths between the power connections and analog output. To further reduce noise, include bulk and local decoupling capacitors. The current consumption on the PVDD and IOVDD pins, the short-circuit current limit for the voltage output, and the current ranges for the current output are listed in the Electrical Characteristics . The power supply must meet the requirements listed in the Recommended Operating Conditions . The AFEx82H1 can operate within a single-supply range of 2.7 V to 5.5 V applied to the PVDD pin. When 2.7 V to 5.5 V is provided to PVDD, an internal LDO is enabled that drives VDD internally. VDD pin must have 1 μF to 10 μF of capacitance for operation. The digital interface supply, IOVDD, can operate with a supply range of 1.71 V to 5.5 V. Switching power supplies and DC/DC converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes. This noise can easily couple into the DAC output voltage or current through various paths between the power connections and analog output. To further reduce noise, include bulk and local decoupling capacitors. The current consumption on the PVDD and IOVDD pins, the short-circuit current limit for the voltage output, and the current ranges for the current output are listed in the Electrical Characteristics . The power supply must meet the requirements listed in the Recommended Operating Conditions . The AFEx82H1 can operate within a single-supply range of 2.7 V to 5.5 V applied to the PVDD pin. When 2.7 V to 5.5 V is provided to PVDD, an internal LDO is enabled that drives VDD internally. VDD pin must have 1 μF to 10 μF of capacitance for operation. AFEx82H1The digital interface supply, IOVDD, can operate with a supply range of 1.71 V to 5.5 V.Switching power supplies and DC/DC converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes. This noise can easily couple into the DAC output voltage or current through various paths between the power connections and analog output. To further reduce noise, include bulk and local decoupling capacitors. The current consumption on the PVDD and IOVDD pins, the short-circuit current limit for the voltage output, and the current ranges for the current output are listed in the Electrical Characteristics . The power supply must meet the requirements listed in the Recommended Operating Conditions . Electrical Characteristics Electrical Characteristics Recommended Operating Conditions Recommended Operating Conditions Layout Layout Guidelines To maximize the performance of the AFEx82H1 in any application, follow good layout practices and proper circuit design. The following recommendations are specific to the device: For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane is not always practical. If ground-plane separation is necessary, make a direct connection of the planes at the DAC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops. IOVDD and PVDD must have 100-nF decoupling capacitors local to the respective pins. VDD must have at least a 1-μF decoupling capacitor used for the internal LDO. Use a high-quality ceramic-type NP0 or X7R capacitor for best performance across temperature and a very low dissipation factor. Place a 100-nF reference capacitor close to the VREFIO pin. Avoid routing switching signals near the reference input. Maintain proper placement for the digital and analog sections with respect to the digital and analog components. Separate the analog and digital circuitry for less coupling into neighboring blocks and to minimize the interaction between analog and digital return currents. For designs that include protection circuits: Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devices Use large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O pins. Layout Example Layout Example Layout Layout Guidelines To maximize the performance of the AFEx82H1 in any application, follow good layout practices and proper circuit design. The following recommendations are specific to the device: For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane is not always practical. If ground-plane separation is necessary, make a direct connection of the planes at the DAC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops. IOVDD and PVDD must have 100-nF decoupling capacitors local to the respective pins. VDD must have at least a 1-μF decoupling capacitor used for the internal LDO. Use a high-quality ceramic-type NP0 or X7R capacitor for best performance across temperature and a very low dissipation factor. Place a 100-nF reference capacitor close to the VREFIO pin. Avoid routing switching signals near the reference input. Maintain proper placement for the digital and analog sections with respect to the digital and analog components. Separate the analog and digital circuitry for less coupling into neighboring blocks and to minimize the interaction between analog and digital return currents. For designs that include protection circuits: Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devices Use large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O pins. Layout Guidelines To maximize the performance of the AFEx82H1 in any application, follow good layout practices and proper circuit design. The following recommendations are specific to the device: For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane is not always practical. If ground-plane separation is necessary, make a direct connection of the planes at the DAC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops. IOVDD and PVDD must have 100-nF decoupling capacitors local to the respective pins. VDD must have at least a 1-μF decoupling capacitor used for the internal LDO. Use a high-quality ceramic-type NP0 or X7R capacitor for best performance across temperature and a very low dissipation factor. Place a 100-nF reference capacitor close to the VREFIO pin. Avoid routing switching signals near the reference input. Maintain proper placement for the digital and analog sections with respect to the digital and analog components. Separate the analog and digital circuitry for less coupling into neighboring blocks and to minimize the interaction between analog and digital return currents. For designs that include protection circuits: Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devices Use large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O pins. To maximize the performance of the AFEx82H1 in any application, follow good layout practices and proper circuit design. The following recommendations are specific to the device: For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane is not always practical. If ground-plane separation is necessary, make a direct connection of the planes at the DAC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops. IOVDD and PVDD must have 100-nF decoupling capacitors local to the respective pins. VDD must have at least a 1-μF decoupling capacitor used for the internal LDO. Use a high-quality ceramic-type NP0 or X7R capacitor for best performance across temperature and a very low dissipation factor. Place a 100-nF reference capacitor close to the VREFIO pin. Avoid routing switching signals near the reference input. Maintain proper placement for the digital and analog sections with respect to the digital and analog components. Separate the analog and digital circuitry for less coupling into neighboring blocks and to minimize the interaction between analog and digital return currents. For designs that include protection circuits: Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devices Use large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O pins. To maximize the performance of the AFEx82H1 in any application, follow good layout practices and proper circuit design. The following recommendations are specific to the device: For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane is not always practical. If ground-plane separation is necessary, make a direct connection of the planes at the DAC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops. IOVDD and PVDD must have 100-nF decoupling capacitors local to the respective pins. VDD must have at least a 1-μF decoupling capacitor used for the internal LDO. Use a high-quality ceramic-type NP0 or X7R capacitor for best performance across temperature and a very low dissipation factor. Place a 100-nF reference capacitor close to the VREFIO pin. Avoid routing switching signals near the reference input. Maintain proper placement for the digital and analog sections with respect to the digital and analog components. Separate the analog and digital circuitry for less coupling into neighboring blocks and to minimize the interaction between analog and digital return currents. For designs that include protection circuits: Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devices Use large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O pins. AFEx82H1 For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane is not always practical. If ground-plane separation is necessary, make a direct connection of the planes at the DAC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops. IOVDD and PVDD must have 100-nF decoupling capacitors local to the respective pins. VDD must have at least a 1-μF decoupling capacitor used for the internal LDO. Use a high-quality ceramic-type NP0 or X7R capacitor for best performance across temperature and a very low dissipation factor. Place a 100-nF reference capacitor close to the VREFIO pin. Avoid routing switching signals near the reference input. Maintain proper placement for the digital and analog sections with respect to the digital and analog components. Separate the analog and digital circuitry for less coupling into neighboring blocks and to minimize the interaction between analog and digital return currents. For designs that include protection circuits: Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devices Use large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O pins. For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane is not always practical. If ground-plane separation is necessary, make a direct connection of the planes at the DAC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops.IOVDD and PVDD must have 100-nF decoupling capacitors local to the respective pins. VDD must have at least a 1-μF decoupling capacitor used for the internal LDO. Use a high-quality ceramic-type NP0 or X7R capacitor for best performance across temperature and a very low dissipation factor.Place a 100-nF reference capacitor close to the VREFIO pin.Avoid routing switching signals near the reference input. Maintain proper placement for the digital and analog sections with respect to the digital and analog components. Separate the analog and digital circuitry for less coupling into neighboring blocks and to minimize the interaction between analog and digital return currents.For designs that include protection circuits: Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devices Use large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O pins. Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devices Use large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O pins. Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devicesUse large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O pins. Layout Example Layout Example Layout Example Layout Example Layout Example Layout Example Layout Example Device and Documentation Support Documentation Support Related Documentation For related documentation see the following: Texas Instruments, AFE882H1 Evaluation Module User's Guide Texas Instruments, REF35 Ultra Low-Power, High-Precision Voltage Reference data sheet Texas Instruments, XTR305 Industrial Analog Current or Voltage Output Driver data sheet Texas Instruments, ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and Reference data sheet Texas Instruments, TPS7A16 60-V, 5-µA IQ, 100-mA, Low-Dropout Voltage Regulator With Enable and Power-Good data sheet Texas Instruments, TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response data sheet Texas Instruments, ISO7021 Ultra-Low Power Two-Channel Digital Isolator data sheet Texas Instruments, Isolated, Ultra-Low Power Design for 4- to 20-mA Loop Powered Transmitters design guide Texas Instruments, Isolated Loop Powered Thermocouple Transmitter design guide Texas Instruments, Small Form Factor, 2-Wire, 4- to 20-mA Current-Loop, RTD Temperature Transmitter design guide Texas Instruments, Isolated Power and Data Interface for Low-power Applications reference design Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power Applications design guide Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support Documentation Support Related Documentation For related documentation see the following: Texas Instruments, AFE882H1 Evaluation Module User's Guide Texas Instruments, REF35 Ultra Low-Power, High-Precision Voltage Reference data sheet Texas Instruments, XTR305 Industrial Analog Current or Voltage Output Driver data sheet Texas Instruments, ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and Reference data sheet Texas Instruments, TPS7A16 60-V, 5-µA IQ, 100-mA, Low-Dropout Voltage Regulator With Enable and Power-Good data sheet Texas Instruments, TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response data sheet Texas Instruments, ISO7021 Ultra-Low Power Two-Channel Digital Isolator data sheet Texas Instruments, Isolated, Ultra-Low Power Design for 4- to 20-mA Loop Powered Transmitters design guide Texas Instruments, Isolated Loop Powered Thermocouple Transmitter design guide Texas Instruments, Small Form Factor, 2-Wire, 4- to 20-mA Current-Loop, RTD Temperature Transmitter design guide Texas Instruments, Isolated Power and Data Interface for Low-power Applications reference design Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power Applications design guide Documentation Support Related Documentation For related documentation see the following: Texas Instruments, AFE882H1 Evaluation Module User's Guide Texas Instruments, REF35 Ultra Low-Power, High-Precision Voltage Reference data sheet Texas Instruments, XTR305 Industrial Analog Current or Voltage Output Driver data sheet Texas Instruments, ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and Reference data sheet Texas Instruments, TPS7A16 60-V, 5-µA IQ, 100-mA, Low-Dropout Voltage Regulator With Enable and Power-Good data sheet Texas Instruments, TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response data sheet Texas Instruments, ISO7021 Ultra-Low Power Two-Channel Digital Isolator data sheet Texas Instruments, Isolated, Ultra-Low Power Design for 4- to 20-mA Loop Powered Transmitters design guide Texas Instruments, Isolated Loop Powered Thermocouple Transmitter design guide Texas Instruments, Small Form Factor, 2-Wire, 4- to 20-mA Current-Loop, RTD Temperature Transmitter design guide Texas Instruments, Isolated Power and Data Interface for Low-power Applications reference design Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power Applications design guide Related Documentation For related documentation see the following: Texas Instruments, AFE882H1 Evaluation Module User's Guide Texas Instruments, REF35 Ultra Low-Power, High-Precision Voltage Reference data sheet Texas Instruments, XTR305 Industrial Analog Current or Voltage Output Driver data sheet Texas Instruments, ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and Reference data sheet Texas Instruments, TPS7A16 60-V, 5-µA IQ, 100-mA, Low-Dropout Voltage Regulator With Enable and Power-Good data sheet Texas Instruments, TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response data sheet Texas Instruments, ISO7021 Ultra-Low Power Two-Channel Digital Isolator data sheet Texas Instruments, Isolated, Ultra-Low Power Design for 4- to 20-mA Loop Powered Transmitters design guide Texas Instruments, Isolated Loop Powered Thermocouple Transmitter design guide Texas Instruments, Small Form Factor, 2-Wire, 4- to 20-mA Current-Loop, RTD Temperature Transmitter design guide Texas Instruments, Isolated Power and Data Interface for Low-power Applications reference design Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power Applications design guide For related documentation see the following: Texas Instruments, AFE882H1 Evaluation Module User's Guide Texas Instruments, REF35 Ultra Low-Power, High-Precision Voltage Reference data sheet Texas Instruments, XTR305 Industrial Analog Current or Voltage Output Driver data sheet Texas Instruments, ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and Reference data sheet Texas Instruments, TPS7A16 60-V, 5-µA IQ, 100-mA, Low-Dropout Voltage Regulator With Enable and Power-Good data sheet Texas Instruments, TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response data sheet Texas Instruments, ISO7021 Ultra-Low Power Two-Channel Digital Isolator data sheet Texas Instruments, Isolated, Ultra-Low Power Design for 4- to 20-mA Loop Powered Transmitters design guide Texas Instruments, Isolated Loop Powered Thermocouple Transmitter design guide Texas Instruments, Small Form Factor, 2-Wire, 4- to 20-mA Current-Loop, RTD Temperature Transmitter design guide Texas Instruments, Isolated Power and Data Interface for Low-power Applications reference design Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power Applications design guide For related documentation see the following: Texas Instruments, AFE882H1 Evaluation Module User's Guide Texas Instruments, REF35 Ultra Low-Power, High-Precision Voltage Reference data sheet Texas Instruments, XTR305 Industrial Analog Current or Voltage Output Driver data sheet Texas Instruments, ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and Reference data sheet Texas Instruments, TPS7A16 60-V, 5-µA IQ, 100-mA, Low-Dropout Voltage Regulator With Enable and Power-Good data sheet Texas Instruments, TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response data sheet Texas Instruments, ISO7021 Ultra-Low Power Two-Channel Digital Isolator data sheet Texas Instruments, Isolated, Ultra-Low Power Design for 4- to 20-mA Loop Powered Transmitters design guide Texas Instruments, Isolated Loop Powered Thermocouple Transmitter design guide Texas Instruments, Small Form Factor, 2-Wire, 4- to 20-mA Current-Loop, RTD Temperature Transmitter design guide Texas Instruments, Isolated Power and Data Interface for Low-power Applications reference design Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power Applications design guide Texas Instruments, AFE882H1 Evaluation Module User's Guide Texas Instruments, REF35 Ultra Low-Power, High-Precision Voltage Reference data sheet Texas Instruments, XTR305 Industrial Analog Current or Voltage Output Driver data sheet Texas Instruments, ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and Reference data sheet Texas Instruments, TPS7A16 60-V, 5-µA IQ, 100-mA, Low-Dropout Voltage Regulator With Enable and Power-Good data sheet Texas Instruments, TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response data sheet Texas Instruments, ISO7021 Ultra-Low Power Two-Channel Digital Isolator data sheet Texas Instruments, Isolated, Ultra-Low Power Design for 4- to 20-mA Loop Powered Transmitters design guide Texas Instruments, Isolated Loop Powered Thermocouple Transmitter design guide Texas Instruments, Small Form Factor, 2-Wire, 4- to 20-mA Current-Loop, RTD Temperature Transmitter design guide Texas Instruments, Isolated Power and Data Interface for Low-power Applications reference design Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power Applications design guide Texas Instruments, AFE882H1 Evaluation Module User's Guide AFE882H1 Evaluation Module User's GuideTexas Instruments, REF35 Ultra Low-Power, High-Precision Voltage Reference data sheet REF35 Ultra Low-Power, High-Precision Voltage Reference data sheetTexas Instruments, XTR305 Industrial Analog Current or Voltage Output Driver data sheet XTR305 Industrial Analog Current or Voltage Output Driver data sheetTexas Instruments, ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and Reference data sheet ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and Reference data sheetTexas Instruments, TPS7A16 60-V, 5-µA IQ, 100-mA, Low-Dropout Voltage Regulator With Enable and Power-Good data sheet TPS7A16 60-V, 5-µA IQ, 100-mA, Low-Dropout Voltage Regulator With Enable and Power-Good data sheetTexas Instruments, TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response data sheet TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response data sheetTexas Instruments, ISO7021 Ultra-Low Power Two-Channel Digital Isolator data sheet ISO7021 Ultra-Low Power Two-Channel Digital Isolator data sheetTexas Instruments, Isolated, Ultra-Low Power Design for 4- to 20-mA Loop Powered Transmitters design guide Isolated, Ultra-Low Power Design for 4- to 20-mA Loop Powered Transmitters design guideTexas Instruments, Isolated Loop Powered Thermocouple Transmitter design guide Isolated Loop Powered Thermocouple Transmitter design guideTexas Instruments, Small Form Factor, 2-Wire, 4- to 20-mA Current-Loop, RTD Temperature Transmitter design guide Small Form Factor, 2-Wire, 4- to 20-mA Current-Loop, RTD Temperature Transmitter design guideTexas Instruments, Isolated Power and Data Interface for Low-power Applications reference design Isolated Power and Data Interface for Low-power Applications reference designTexas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power Applications design guide Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power Applications design guide Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotifications Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. Revision History DATE REVISION NOTES * Initial release. Revision History DATE REVISION NOTES * Initial release. DATE REVISION NOTES * Initial release. DATE REVISION NOTES * Initial release. DATE REVISION NOTES * Initial release. DATE REVISION NOTES DATE REVISION NOTES DATEREVISIONNOTES * Initial release. * Initial release. *Initial release. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 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IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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Valid SDO output is driven only when CS = 0 and CONFIG.DSDO = 0; otherwise, the SDO pin remains Hi-Z to save power. The SDO data bits are left-justified within the frame, meaning the most significant bit is produced on the line (subject to timing details) when CS is asserted low (bit is driven by falling edge of CS). The subsequent bits in the frame are driven by the rising SCLK edge when CONFIG.FSDO = 0 (default). To drive the SDO data on the falling edge of SCLK, set CONFIG.FSDO = 1. This setting effectively gives the SDO data an additional ½ clock period for setup time, but at the expense of hold time.

The frame output on SDO contains the command bit of the input that generated the frame (previous input frame), followed by seven status bits (see Figure 6-29). When an input frame CRC error is detected, the status bit CRC_ERR = 1. If there is no input frame CRC error, then CRC_ERR = 0. See Table 6-13 for details.