SLASF43 December   2023 AFE782H1 , AFE882H1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Timing Diagrams
    8. 5.8  Typical Characteristics: VOUT DAC
    9. 5.9  Typical Characteristics: ADC
    10. 5.10 Typical Characteristics: Reference
    11. 5.11 Typical Characteristics: HART Modem
    12. 5.12 Typical Characteristics: Power Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Buffer Amplifier
        3. 6.3.1.3 DAC Transfer Function
        4. 6.3.1.4 DAC Gain and Offset Calibration
        5. 6.3.1.5 Programmable Slew Rate
        6. 6.3.1.6 DAC Register Structure and CLEAR State
      2. 6.3.2  Analog-to-Digital Converter (ADC) Overview
        1. 6.3.2.1 ADC Operation
        2. 6.3.2.2 ADC Custom Channel Sequencer
        3. 6.3.2.3 ADC Synchronization
        4. 6.3.2.4 ADC Offset Calibration
        5. 6.3.2.5 External Monitoring Inputs
        6. 6.3.2.6 Temperature Sensor
        7. 6.3.2.7 Self-Diagnostic Multiplexer
        8. 6.3.2.8 ADC Bypass
      3. 6.3.3  Programmable Out-of-Range Alarms
        1. 6.3.3.1 Alarm-Based Interrupts
        2. 6.3.3.2 Alarm Action Configuration Register
        3. 6.3.3.3 Alarm Voltage Generator
        4. 6.3.3.4 Temperature Sensor Alarm Function
        5. 6.3.3.5 Internal Reference Alarm Function
        6. 6.3.3.6 ADC Alarm Function
        7. 6.3.3.7 Fault Detection
      4. 6.3.4  IRQ
      5. 6.3.5  HART Interface
        1. 6.3.5.1  FIFO Buffers
          1. 6.3.5.1.1 FIFO Buffer Access
          2. 6.3.5.1.2 FIFO Buffer Flags
        2. 6.3.5.2  HART Modulator
        3. 6.3.5.3  HART Demodulator
        4. 6.3.5.4  HART Modem Modes
          1. 6.3.5.4.1 Half-Duplex Mode
          2. 6.3.5.4.2 Full-Duplex Mode
        5. 6.3.5.5  HART Modulation and Demodulation Arbitration
          1. 6.3.5.5.1 HART Receive Mode
          2. 6.3.5.5.2 HART Transmit Mode
        6. 6.3.5.6  HART Modulator Timing and Preamble Requirements
        7. 6.3.5.7  HART Demodulator Timing and Preamble Requirements
        8. 6.3.5.8  IRQ Configuration for HART Communication
        9. 6.3.5.9  HART Communication Using the SPI
        10. 6.3.5.10 HART Communication Using UART
        11. 6.3.5.11 Memory Built-In Self-Test (MBIST)
      6. 6.3.6  Internal Reference
      7. 6.3.7  Integrated Precision Oscillator
      8. 6.3.8  Precision Oscillator Diagnostics
      9. 6.3.9  One-Time Programmable (OTP) Memory
      10. 6.3.10 GPIO
      11. 6.3.11 Timer
      12. 6.3.12 Unique Chip Identifier (ID)
      13. 6.3.13 Scratch Pad Register
    4. 6.4 Device Functional Modes
      1. 6.4.1 DAC Power-Down Mode
      2. 6.4.2 Register Built-In Self-Test (RBIST)
      3. 6.4.3 Reset
    5. 6.5 Programming
      1. 6.5.1 Communication Setup
        1. 6.5.1.1 SPI Mode
        2. 6.5.1.2 UART Mode
        3. 6.5.1.3 SPI Plus UART Mode
        4. 6.5.1.4 HART Functionality Setup Options
      2. 6.5.2 GPIO Programming
      3. 6.5.3 Serial Peripheral Interface (SPI)
        1. 6.5.3.1 SPI Frame Definition
        2. 6.5.3.2 SPI Read and Write
        3. 6.5.3.3 Frame Error Checking
        4. 6.5.3.4 Synchronization
      4. 6.5.4 UART Interface
        1. 6.5.4.1 UART Break Mode (UBM)
          1. 6.5.4.1.1 Interface With FIFO Buffers and Register Map
      5. 6.5.5 Status Bits
      6. 6.5.6 Watchdog Timer
  8. 7 Register Maps
    1. 7.1 AFEx82H1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Current Loop Control
          2. 8.2.1.2.2 HART Connections
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RRU|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.2.2 ADC Custom Channel Sequencer

The device uses a custom channel sequencer to control the multiplexer of the ADC. The ADC sequencer allows the user to specify which channels are converted. The sequencer consists of 16 indexed slots with programmable start and stop index fields to configure the start and stop conversion points.

In direct-mode conversion, the ADC converts from the start index to the stop index once and then stops. In auto-mode conversion, the ADC converts from the start to stop index repeatedly until the ADC is stopped. Figure 6-37 shows the indexed custom channel sequence slots available in the device.

GUID-20220626-SS0I-GMKQ-9CKM-TXDVZTW6K9J1-low.svg Figure 6-9 ADC MUX Control

Table 6-3 lists the ADC input channel assignments for the sequencer.

Table 6-3 Indexed Custom Channel Sequence
CCS POINTER CHANNEL CONV_RATE RANGE
0 OFFSET 2560 Hz VREF
1 AIN0 Programmable Programmable
2 AIN1 Programmable Programmable
3 TEMP 2560 Hz VREF
4 SD0 (VREF) 2560 Hz VREF
5 SD1 (PVDD) 2560 Hz VREF
6 SD2 (VDD) 2560 Hz VREF
7 SD3 (ZTAT) 2560 Hz VREF
8 SD4 (VOUT) 2560 Hz

2 × VREF
9-15 GND 2560 Hz VREF

Use the ADC_INDEX_CFG register to select the channels. The order of the channels is fixed and shown in Table 6-3. Then, use ADC_INDEX_CFG.START and ADC_INDEX_CFG.STOP to select the range of indices to convert. If these two values are the same, then the ADC only converts a single channel. If the START and STOP values are different, then the ADC cycles through the corresponding indices. By default, all channels are configured to be converted; START = 0 and STOP = 8. If the AIN1 channel is not configured as an ADC input, then the result for this channel is 0x000. The minimum time for a conversion is still allotted to AIN1 if the channel is within the START and STOP range. If START is configured to be greater than STOP, then the device interprets the conversion sequence as if START = STOP.

In direct mode, each selected channel in the ADC_INDEX_CFG register is converted once per TRIGGER.ADC command. In auto mode, each channel selected in the ADC_INDEX_CFG register is converted once; after the last channel, the loop is repeated as long as the ADC is enabled. In auto mode, writing to TRIGGER.ADC = 1 starts the conversions. Writing TRIGGER.ADC = 0 disables the ADC after the current channel being converted finishes. In direct mode, writing TRIGGER.ADC = 1 starts the sequence. When the sequence ends, then TRIGGER.ADC is self-cleared.

A minimum of 20 clock cycles is required to perform one conversion. The ADC clock is derived from the internal oscillator and divided by 16, which gives an ADC clock frequency of 1.2288 MHz / 16 = 76.8 kHz, for a clock period = 13.02 μs.

Each of the internal nodes has a fixed conversion rate. Pins AIN0 and AIN1 have programmable conversion rates (see also the ADC_CFG register). Pins AIN0 and AIN1 also have a configurable range. The input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit.

If any ADC configuration bits are changed, the following sequence is recommended:

  1. Disable the ADC
  2. Wait for ADC_BUSY to go low
  3. Change the configuration
  4. Restart the conversions

ADC_BUSY can be monitored in the GEN_STATUS register.

If the ADC is configured for direct mode (ADC_CFG.DIRECT_MODE = 1), then after setting the desired channels to convert, write a 1 to TRIGGER.ADC. This bit is self-cleared when the sequence is finished converting. This command converts all the selected channels once. To initiate another conversion of the channels, send another TRIGGER.ADC command.