SPRS653E February   2010  – March 2014 AM1808

PRODUCTION DATA.  

  1. 1 AM1808 ARM Microprocessor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 Memory Map Summary
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Pin Multiplexing Control
    7. 3.7 Terminal Functions
      1. 3.7.1  Device Reset and JTAG
      2. 3.7.2  High-Frequency Oscillator and PLL
      3. 3.7.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.7.4  DEEPSLEEP Power Control
      5. 3.7.5  External Memory Interface A (EMIFA)
      6. 3.7.6  DDR2/mDDR Memory Controller
      7. 3.7.7  Serial Peripheral Interface Modules (SPI)
      8. 3.7.8  Programmable Real-Time Unit (PRU)
      9. 3.7.9  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      10. 3.7.10 Enhanced Pulse Width Modulators (eHRPWM)
      11. 3.7.11 Boot
      12. 3.7.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      13. 3.7.13 Inter-Integrated Circuit Modules(I2C0, I2C1)
      14. 3.7.14 Timers
      15. 3.7.15 Multichannel Audio Serial Ports (McASP)
      16. 3.7.16 Multichannel Buffered Serial Ports (McBSP)
      17. 3.7.17 Universal Serial Bus Modules (USB0, USB1)
      18. 3.7.18 Ethernet Media Access Controller (EMAC)
      19. 3.7.19 Multimedia Card/Secure Digital (MMC/SD)
      20. 3.7.20 Liquid Crystal Display Controller(LCD)
      21. 3.7.21 Serial ATA Controller (SATA)
      22. 3.7.22 Universal Host-Port Interface (UHPI)
      23. 3.7.23 Universal Parallel Port (uPP)
      24. 3.7.24 Video Port Interface (VPIF)
      25. 3.7.25 General Purpose Input Output
      26. 3.7.26 Reserved and No Connect
      27. 3.7.27 Supply and Ground
    8. 3.8 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 ARM CPU Interrupts
        1. 6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 6.7.1.2 AINTC Hardware Vector Generation
        3. 6.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 6.7.1.4 AINTC System Interrupt Assignments
        5. 6.7.1.5 AINTC Memory Map
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. 6.8.1.1 Module States
    9. 6.9  EDMA
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 External Memory Interface Register Descriptions
      5. 6.10.5 EMIFA Electrical Data/Timing
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1. 6.11.3.1  DDR2/mDDR Interface Schematic
        2. 6.11.3.2  Compatible JEDEC DDR2/mDDR Devices
        3. 6.11.3.3  PCB Stackup
        4. 6.11.3.4  Placement
        5. 6.11.3.5  DDR2/mDDR Keep Out Region
        6. 6.11.3.6  Bulk Bypass Capacitors
        7. 6.11.3.7  High-Speed Bypass Capacitors
        8. 6.11.3.8  Net Classes
        9. 6.11.3.9  DDR2/mDDR Signal Termination
        10. 6.11.3.10 VREF Routing
        11. 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
        12. 6.11.3.12 MDDR/DDR2 Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
    14. 6.14 Serial ATA Controller (SATA)
      1. 6.14.1 SATA Register Descriptions
      2. 6.14.2 SATA Interface
        1. 6.14.2.1 SATA Interface Schematic
        2. 6.14.2.2 Compatible SATA Components and Modes
        3. 6.14.2.3 PCB Stackup Specifications
        4. 6.14.2.4 Routing Specifications
        5. 6.14.2.5 Coupling Capacitors
        6. 6.14.2.6 SATA Interface Clock Source requirements
      3. 6.14.3 SATA Unused Signal Configuration
    15. 6.15 Multichannel Audio Serial Port (McASP)
      1. 6.15.1 McASP Peripheral Registers Description(s)
      2. 6.15.2 McASP Electrical Data/Timing
        1. 6.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
    16. 6.16 Multichannel Buffered Serial Port (McBSP)
      1. 6.16.1 McBSP Peripheral Register Description(s)
      2. 6.16.2 McBSP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Buffered Serial Port (McBSP) Timing
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
    18. 6.18 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.18.1 I2C Device-Specific Information
      2. 6.18.2 I2C Peripheral Registers Description(s)
      3. 6.18.3 I2C Electrical Data/Timing
        1. 6.18.3.1 Inter-Integrated Circuit (I2C) Timing
    19. 6.19 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.19.1 UART Peripheral Registers Description(s)
      2. 6.19.2 UART Electrical Data/Timing
    20. 6.20 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
      1. 6.20.1 USB Peripheral Registers Description(s)
      2. 6.20.2 USB0 [USB2.0] Electrical Data/Timing
    21. 6.21 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]
    22. 6.22 Ethernet Media Access Controller (EMAC)
      1. 6.22.1 EMAC Peripheral Register Description(s)
      2. 6.22.2 EMAC Electrical Data/Timing
    23. 6.23 Management Data Input/Output (MDIO)
      1. 6.23.1 MDIO Registers
      2. 6.23.2 Management Data Input/Output (MDIO) Electrical Data/Timing
    24. 6.24 LCD Controller (LCDC)
      1. 6.24.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.24.2 LCD Raster Mode
    25. 6.25 Host-Port Interface (UHPI)
      1. 6.25.1 HPI Device-Specific Information
      2. 6.25.2 HPI Peripheral Register Description(s)
      3. 6.25.3 HPI Electrical Data/Timing
    26. 6.26 Universal Parallel Port (uPP)
      1. 6.26.1 uPP Register Descriptions
      2. 6.26.2 uPP Electrical Data/Timing
    27. 6.27 Video Port Interface (VPIF)
      1. 6.27.1 VPIF Register Descriptions
      2. 6.27.2 VPIF Electrical Data/Timing
    28. 6.28 Enhanced Capture (eCAP) Peripheral
    29. 6.29 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.29.1 eHRPWM Register Descriptions
      2. 6.29.2 Enhanced Pulse Width Modulator (eHRPWM) Timing
      3. 6.29.3 Trip-Zone Input Timing
    30. 6.30 Timers
      1. 6.30.1 Timer Electrical Data/Timing
    31. 6.31 Real Time Clock (RTC)
      1. 6.31.1 Clock Source
      2. 6.31.2 Real-Time Clock Register Descriptions
    32. 6.32 General-Purpose Input/Output (GPIO)
      1. 6.32.1 GPIO Register Description(s)
      2. 6.32.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 6.32.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    33. 6.33 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.33.1 PRUSS Register Descriptions
    34. 6.34 Emulation Logic
      1. 6.34.1 JTAG Port Description
      2. 6.34.2 Scan Chain Configuration Parameters
      3. 6.34.3 Initial Scan Chain Configuration
        1. 6.34.3.1 Adding TAPS to the Scan Chain
      4. 6.34.4 IEEE 1149.1 JTAG
        1. 6.34.4.1 JTAG Peripheral Register Description(s) - JTAG ID Register (DEVIDR0)
        2. 6.34.4.2 JTAG Test-Port Electrical Data/Timing
      5. 6.34.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZCE Package
    2. 8.2 Thermal Data for ZWT Package

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCE|361
  • ZWT|361
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Revision History

This data manual revision history highlights the changes made to the SPRS653D device-specific data manual to make it an SPRS653E revision.

Table 2-1 Revision History

SEE ADDITIONS/MODIFICATIONS/DELETIONS
Global
  • Turned on Navigation Icons on top of first page
  • Moved Trademarks information from first page to within Section 7, Device and Documentation Support.
  • Moved ESDS Warning to within Section 7, Device and Documentation Support.
  • Updated Features, Applications, and Description for consistency and translation.
Section 1.3
Description		 Added NEW Device Information Table.
Section 3.7
Terminal Functions		 Table 3-3thruTable 3-27:
  • Updated/Changed footnote beginning with "IPD = Internal Pulldown resistor..."; added sentence "For more detailed information on pullup/pulldown..."
Section 3.7.17
Universal Serial Bus Modules (USB0, USB1)		 Table 3-19, Universal Serial Bus (USB) Terminal Functions
  • Updated/Changed the capacitor value in USB0_VDDA12 pin DESCRIPTION from "1 μF" to "0.22-μF"
Section 3.8
Unused Pin Configurations		 Table 3-30, Unused USB0 and USB1 Signal Configurations:
  • Updated/Changed USB0_VDDA12 row by combining two columns and changing text from "...to an external filter capacitor" to "...to an external 0.22-μF filter capacitor"
Section 5
Specifications		 Updated/Changed title from "Device Operating Conditions" to "Specifications"
Section 5.2, Handling Ratings:
  • Split handling, ratings, and certifications from the Abs Max table and placed in NEW Handling Ratings table.
Section 5.4
Notes on Recommended Power-On Hours		 Table 5-1, Recommended Power-On Hours:
  • Updated/Changed all applicable Silicon Revisions from "B" to "B/E"
Section 6.10.5
EMIFA Electrical/Timing		 Figure 6-12, Asynchronous Memory Read Timing for EMIFA:
  • Added vertical lines to show difference between Setup, Strobe, and Hold
Figure 6-13, Asynchronous Memory Write Timing for EMIFA:
  • Added vertical lines to show difference between Setup, Strobe, and Hold
Section 6.14.2.4
Routing Specifications		 Table 6-45, SATA Routing Specifications:
  • Added NEW footnote beginning with "The SATA_REFCLK(P/N)..."
Section 7.1.2
Device and Development-Support Tool Nomenclature		 Figure 7-1, Device Nomenclature:
  • Added "E = Silicon Revision 2.3" under SILICON REVISION
Section 7.6
Glossary		 Added NEW section.