SPRSP65G April 2021 – May 2024 AM2431 , AM2432 , AM2434
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
OUTPUT CONDITIONS | |||||
CL | Output load capacitance | 2 | 5 | pF | |
PCB CONNECTIVITY REQUIREMENTS | |||||
td(Trace Mismatch) | Propagation delay mismatch across all traces | VDDSHV3 = 1.8V | 200 | ps | |
VDDSHV3 =3.3V | 100 | ps |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
1.8V Mode | |||||
DBTR1 | tc(TRC_CLK) | Cycle time, TRC_CLK | 6.50 | ns | |
DBTR2 | tw(TRC_CLKH) | Pulse width, TRC_CLK high | 2.50 | ns | |
DBTR3 | tw(TRC_CLKL) | Pulse width, TRC_CLK low | 2.50 | ns | |
DBTR4 | tosu(TRC_DATAV-TRC_CLK) | Output setup time, TRC_DATA valid to TRC_CLK edge | 0.81 | ns | |
DBTR5 | toh(TRC_CLK-TRC_DATAI) | Output hold time, TRC_CLK edge to TRC_DATA invalid | 0.81 | ns | |
DBTR6 | tosu(TRC_CTLV-TRC_CLK) | Output setup time, TRC_CTL valid to TRC_CLK edge | 0.81 | ns | |
DBTR7 | toh(TRC_CLK-TRC_CTLI) | Output hold time, TRC_CLK edge to TRC_CTL invalid | 0.81 | ns | |
3.3V Mode | |||||
DBTR1 | tc(TRC_CLK) | Cycle time, TRC_CLK | 8.67 | ns | |
DBTR2 | tw(TRC_CLKH) | Pulse width, TRC_CLK high | 3.58 | ns | |
DBTR3 | tw(TRC_CLKL) | Pulse width, TRC_CLK low | 3.58 | ns | |
DBTR4 | tosu(TRC_DATAV-TRC_CLK) | Output setup time, TRC_DATA valid to TRC_CLK edge | 1.08 | ns | |
DBTR5 | toh(TRC_CLK-TRC_DATAI) | Output hold time, TRC_CLK edge to TRC_DATA invalid | 1.08 | ns | |
DBTR6 | tosu(TRC_CTLV-TRC_CLK) | Output setup time, TRC_CTL valid to TRC_CLK edge | 1.08 | ns | |
DBTR7 | toh(TRC_CLK-TRC_CTLI) | Output hold time, TRC_CLK edge to TRC_CTL invalid | 1.08 | ns |