SWRS245B December   2021  – December 2023 AM2732 , AM2732-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 AM273x ZCE Pin Diagram
      2. 5.1.2 AM273x NZN Pin Diagram
    2. 5.2 Pin Attributes (AM273x ZCE, NZN Packages)
      1.      13
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC Signal Descriptions
        1.       16
      2. 5.3.2  CPTS Signal Descriptions
        1.       18
      3. 5.3.3  CSI 2.0 Signal Descriptions
        1.       20
      4. 5.3.4  DMM Signal Descriptions
        1.       22
      5. 5.3.5  ECAP Signal Descriptions
        1.       24
      6. 5.3.6  EPWM Signal Descriptions
        1.       26
        2.       27
        3.       28
        4.       29
      7. 5.3.7  GPIO Signal Descriptions
        1.       31
        2.       32
      8. 5.3.8  I2C Signal Descriptions
        1.       34
        2.       35
        3.       36
      9. 5.3.9  Clock Signal Descriptions
        1.       38
        2.       39
      10. 5.3.10 JTAG Signal Descriptions
        1.       41
      11. 5.3.11 LVDS Signal Descriptions
        1.       43
      12. 5.3.12 MCAN Signal Descriptions
        1.       45
        2.       46
      13. 5.3.13 MCASP Signal Descriptions
        1.       48
        2.       49
        3.       50
      14. 5.3.14 Ethernet Signal Descriptions
        1.       52
        2.       53
        3.       54
        4.       55
      15. 5.3.15 GPIO Signal Descriptions
        1.       57
        2.       58
      16. 5.3.16 Power Supply Signal Descriptions
        1.       60
      17. 5.3.17 QSPI Signal Descriptions
        1.       62
      18. 5.3.18 Reserverd Signal Descriptions
        1.       64
      19. 5.3.19 UART Signal Descriptions
        1.       66
        2.       67
      20. 5.3.20 SPI Signal Descriptions
        1.       69
        2.       70
        3.       71
        4.       72
      21. 5.3.21 System Signal Descriptions
        1.       74
      22. 5.3.22 Trace Signal Descriptions
        1.       76
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings - Automotive
    3. 6.3  Power-On Hours (POH)
      1. 6.3.1 Automotive Temperature Profile
      2. 6.3.2 Industrial Temperature Profile
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Power Supply Specifications
    7. 6.7  I/O Buffer Type and Voltage Rail Dependency
    8. 6.8  CPU Specifications
    9. 6.9  Thermal Resistance Characteristics for nFBGA Package [ZCE285A]
    10. 6.10 Thermal Resistance Characteristics for nFBGA Package [NZN225A]
    11. 6.11 Power Consumption Summary
    12. 6.12 Timing and Switching Characteristics
      1. 6.12.1 Power Supply Sequencing and Reset Timing
      2. 6.12.2 Clock Specifications
      3. 6.12.3 Peripheral Information
        1. 6.12.3.1  QSPI Flash Memory Peripheral
          1. 6.12.3.1.1 QSPI Timing Conditions
          2. 6.12.3.1.2 QSPI Timing Requirements
          3. 6.12.3.1.3 QSPI Switching Characteristics
        2. 6.12.3.2  MIBSPI Peripheral
          1. 6.12.3.2.1 SPI Timing Conditions
          2. 6.12.3.2.2 SPI Master Mode Timing and Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 6.12.3.2.3 SPI Master Mode Timing and Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          4. 6.12.3.2.4 SPI Slave Mode Timing and Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        3. 6.12.3.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
          1. 6.12.3.3.1  RGMII/GMII/MII Timing Conditions
          2. 6.12.3.3.2  RGMII Transmit Clock Switching Characteristics
          3. 6.12.3.3.3  RGMII Transmit Data and Control Switching Characteristics
          4. 6.12.3.3.4  RGMII Recieve Clock Timing Requirements
          5. 6.12.3.3.5  RGMII Recieve Data and Control Timing Requirements
          6. 6.12.3.3.6  RMII Transmit Clock Switching Characteristics
          7. 6.12.3.3.7  RMII Transmit Data and Control Switching Characteristics
          8. 6.12.3.3.8  RMII Receive Clock Timing Requirements
          9. 6.12.3.3.9  RMII Receive Data and Control Timing Requirements
          10. 6.12.3.3.10 MII Transmit Switching Characteristics
          11. 6.12.3.3.11 MII Receive Clock Timing Requirements
          12. 6.12.3.3.12 MII Receive Timing Requirements
          13. 6.12.3.3.13 MII Transmit Clock Timing Requirements
          14. 6.12.3.3.14 MDIO Interface Timings
        4. 6.12.3.4  LVDS/Aurora Instrumentation and Measurement Peripheral
          1. 6.12.3.4.1 LVDS Interface Configuration
          2. 6.12.3.4.2 LVDS Interface Timings
        5. 6.12.3.5  UART Peripheral
          1. 6.12.3.5.1 UART Timing Requirements
        6. 6.12.3.6  I2C Protocol Definition
          1. 6.12.3.6.1 I2C Timing Requirements #GUID-D615B3D8-5F52-430D-93CB-70204118ACE4/T4362547-185
        7. 6.12.3.7  Controller Area Network - Flexible Data-Rate (CAN-FD)
          1. 6.12.3.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
        8. 6.12.3.8  CSI-2 Peripheral
        9. 6.12.3.9  General Purpose ADC (GPADC)
        10. 6.12.3.10 Enhanced Pulse-Width Modulator (ePWM)
        11. 6.12.3.11 Enhanced Capture (eCAP)
        12. 6.12.3.12 General-Purpose Input/Output
          1. 6.12.3.12.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-1BEBEADE-CEC6-42DA-A124-5081550EEDD7/T4362547-45 #GUID-1BEBEADE-CEC6-42DA-A124-5081550EEDD7/T4362547-50
      4. 6.12.4 Emulation and Debug
        1. 6.12.4.1 Emulation and Debug Description
        2. 6.12.4.2 JTAG Interface
          1. 6.12.4.2.1 Timing Requirements for IEEE 1149.1 JTAG
          2. 6.12.4.2.2 Switching Characteristics for IEEE 1149.1 JTAG
        3. 6.12.4.3 ETM Trace Interface
          1. 6.12.4.3.1 ETM TRACE Timing Requirements
          2. 6.12.4.3.2 ETM TRACE Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Main Subsystem
    3. 7.3 DSP Subsystem
    4. 7.4 Radar Control Subsystem
    5. 7.5 Other Subsystems
      1. 7.5.1 Radar A2D Data Format Over CSI2 Interface
      2. 7.5.2 ADC Channels (Service) for User Application
    6. 7.6 Boot Modes
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Typical Application
      1. 8.1.1 Schematic
      2. 8.1.2 Layout
        1. 8.1.2.1 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NZN|225
  • ZCE|285
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-1 Pin Attributes (ZCE, NZN Packages)
ZCE Ball Number NZN Ball Number Ball Name Signal Name Pin Control Register Pin Control Address MUX Mode Signal Type DSIS Ball State During Reset Ball State After Reset Mux Mode After Reset I/O Voltage Power Domain Hysteresis Pull Type Buffer Type
R2 L1 ADC1 ADC1 0 I 1.8V VIN_18ADC ADC
P2 P3 ADC2 ADC2 0 I 1.8V VIN_18ADC ADC
R1 K2 ADC3 ADC3 0 I 1.8V VIN_18ADC ADC
P1 K1 ADC4 ADC4 0 I 1.8V VIN_18ADC ADC
M2 J1 ADC5 ADC5 0 I 1.8V VIN_18ADC ADC
T2 L2 ADC6 ADC6 0 I 1.8V VIN_18ADC ADC
N2 N3 ADC7 ADC7 0 I 1.8V VIN_18ADC ADC
N1 J2 ADC8 ADC8 0 I 1.8V VIN_18ADC ADC
M1 M3 ADC9 ADC9 0 I 1.8V VIN_18ADC ADC
U1 N1 CLKM CLKM 0 I 1.8V VIN_18CLK Clock Subsystem
V1 P1 CLKP CLKP 0 I 1.8V VIN_18CLK Clock Subsystem
B6 CSI2_RX0CLKM CSI2_RX0CLKM I VIN_18CSI MIPI D-PHY
A6 CSI2_RX0CLKP CSI2_RX0CLKP I VIN_18CSI MIPI D-PHY
A8 CSI2_RX0M0 CSI2_RX0M0 I VIN_18CSI MIPI D-PHY
A7 CSI2_RX0M1 CSI2_RX0M1 I VIN_18CSI MIPI D-PHY
B5 CSI2_RX0M2 CSI2_RX0M2 I VIN_18CSI MIPI D-PHY
B4 CSI2_RX0M3 CSI2_RX0M3 I VIN_18CSI MIPI D-PHY
B8 CSI2_RX0P0 CSI2_RX0P0 I VIN_18CSI MIPI D-PHY
B7 CSI2_RX0P1 CSI2_RX0P1 I VIN_18CSI MIPI D-PHY
A5 CSI2_RX0P2 CSI2_RX0P2 I VIN_18CSI MIPI D-PHY
A4 CSI2_RX0P3 CSI2_RX0P3 I VIN_18CSI MIPI D-PHY
A11 CSI2_RX1CLKM CSI2_RX1CLKM I VIN_18CSI MIPI D-PHY
B11 CSI2_RX1CLKP CSI2_RX1CLKP I VIN_18CSI MIPI D-PHY
A13 CSI2_RX1M0 CSI2_RX1M0 I VIN_18CSI MIPI D-PHY
B12 CSI2_RX1M1 CSI2_RX1M1 I VIN_18CSI MIPI D-PHY
A10 CSI2_RX1M2 CSI2_RX1M2 I VIN_18CSI MIPI D-PHY
A9 CSI2_RX1M3 CSI2_RX1M3 I VIN_18CSI MIPI D-PHY
B13 CSI2_RX1P0 CSI2_RX1P0 I VIN_18CSI MIPI D-PHY
A12 CSI2_RX1P1 CSI2_RX1P1 I VIN_18CSI MIPI D-PHY
B10 CSI2_RX1P2 CSI2_RX1P2 I VIN_18CSI MIPI D-PHY
B9 CSI2_RX1P3 CSI2_RX1P3 I VIN_18CSI MIPI D-PHY
H19 F14 DSS_UARTA_RX var tempcontentStr='/Analog & Mixed-Signal/microcontrollers (mcus) & processors/arm-based microcontrollers/arm cortex-r mcus'; var partNum ='AM2732-Q1'; var contentStr = replaceSplChars( tempcontentStr )+ "/"+ partNum; var tiContentGroup = contentStr.replace("'",""); function replaceSplChars(content){ var myRegExp=new RegExp("™|®|™","gi"); content=content.replace(myRegExp,""); return content; } var tiProductPathID='/4/5018/268015/'; var tiPageName = 'Literature reader-SWRS245B-en_US'; var tiDocType = 'Data Sheet'; var tiLibraryStore = new com.TI.tiLibrary.tiLibraryStore(); var tiLibraryViewerStore = tiLibraryStore.viewer_store; RiotControl.addStore(tiLibraryStore); var subRoutes = riot.route.create(); subRoutes("/document-viewer/*/datasheet/*\\?*#*", function(gpn, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/datasheet/*#*", function(gpn, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/datasheet/*", function(gpn, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet/" + url, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet/*\\?*#*", function(locale, gpn, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet/*#*", function(locale, gpn, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet/*", function(locale, gpn, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet/" + url, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/datasheet#*/*", function(gpn, url, fragment) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet#" + url + "/" + fragment, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet#*/*", function(locale, gpn, url, fragment) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet#" + url + "/" + fragment, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*", function(litnum) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*/*\\?*#*", function(litnum, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*/*#*", function(litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*#*/*", function(litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "#" + url + "/" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*#*/*", function(locale, litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "#" + url + "/" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*/*", function(litnum, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "/" + url, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*/*\\?*#*", function(locale, litnum, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*/*#*", function(locale, litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*/*", function(locale, litnum, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "/" + url, toc: true, set_content: true }); }); var compose_url = function(q) { //URL format: scheme:[//[user[:password]@]host[:port]][/path][?query][#fragment] var tempUrl = q.url.replace("//www.ti.com/", ""); var url = tempUrl.replace("//www.ti.com/", ""); if (q.search != null) { var params = ""; var hash = ""; var url_parts = url.split('#'); if (url_parts.length == 2) { url = url_parts[0]; hash = url_parts[1]; } var param_parts = url.split('?'); if (param_parts.length == 2) { url = param_parts[0]; var parsed_params = param_parts[1].split('&'); var keyword_param_found = false; for (var i = 0; i < parsed_params.length; i++) { if (parsed_params[i].indexOf('search=') == 0) { keyword_param_found = true; parsed_params[i] = 'search=' + q.search; } } if (!keyword_param_found) { parsed_params.push('search=' + q.search); } params = parsed_params.join('&'); } else { params = 'search=' + q.search; } if (params > "") { url = url + '?' + params; } if (hash > "") { url = url + '#' + hash; } } return url; }; tiLibraryViewerStore.compose_url_route = function(location, q) { return compose_url(q); }; tiLibraryViewerStore.compute_content_href = function(href, url) { return url; }; tiLibraryViewerStore.compose_topic_url = function(location, q) { return compose_url(q); }; tiLibraryViewerStore.important_notice_url = "//www.ti.com/document-viewer/AM2732-Q1/datasheet/important_notice#ImpNotice001"; var ods_reader = riot.mount('ti-library-viewer', { store: tiLibraryStore.list_store, viewerstore: tiLibraryViewerStore }); riot.route.base('/'); riot.route.start(true); compute_document_locale = function(docName) { var locale = 'en_US'; if (docName) { if (docName.toLowerCase().indexOf('z')===0) { locale = 'zh_CN'; } else if (docName.toLowerCase().indexOf('j') == 0) { locale = 'ja_JP'; } } return locale; } open_reader = function() { var path = window.location.pathname.split('/'); var path_minus_filename = ''; for (var i = 0; i < path.length - 1; i++) { if (i == 0 && path[i] == '') { console.log("double slashes found in beginning of document path; treating document path as local machine path"); continue; } path_minus_filename += "/" + path[i]; } RiotControl.trigger("ti_library_open_viewer", { documentLocale: compute_document_locale( "SWRS245B"), document: { href: path_minus_filename, lit_num: "SWRS245B", doc_type: "Data Sheet", show_toc: "true", translated_doc_type: "Data sheet", gpn: "AM2732-Q1", title: "AM273x Sitara™ Microcontrollers", disclaimer: "", product: "//www.ti.com/product/AM2732-Q1", email: 'mailto:?subject=AM2732-Q1 Datasheet&body=http://www.ti.com/document-viewer/AM2732-Q1/datasheet', download: '//www.ti.com/lit/gpn/AM2732-Q1', tistore: '//store.ti.com/Search.aspx?k=AM2732-Q1&pt=-1', productstatusdescription: 'PRODUCTION DATA' }, url: "/document-viewer/AM2732-Q1/datasheet/GUID-20231102-DA0T-X37N-S8MM-506J606WPNH8.html", prepopulated: true, modalOptions: { dismissible: false } }); } open_reader();