SPRS717L October   2011  – March 2020 AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
      1. 4.1.1 ZCE Package Pin Maps (Top View)
        1. Table 4-1 ZCE Pin Map [Section Left - Top View]
        2.       ZCE Pin Map [Section Middle - Top View]
        3.       ZCE Pin Map [Section Right - Top View]
      2. 4.1.2 ZCZ Package Pin Maps (Top View)
        1.       ZCZ Pin Map [Section Left - Top View]
        2.       ZCZ Pin Map [Section Middle - Top View]
        3.       ZCZ Pin Map [Section Right - Top View]
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 External Memory Interfaces
      2. 4.3.2 General-Purpose IOs
      3. 4.3.3 Miscellaneous
        1. 4.3.3.1 eCAP
        2. 4.3.3.2 eHRPWM
        3. 4.3.3.3 eQEP
        4. 4.3.3.4 Timer
      4. 4.3.4 PRU-ICSS
        1. 4.3.4.1 PRU0
        2. 4.3.4.2 PRU1
      5. 4.3.5 Removable Media Interfaces
      6. 4.3.6 Serial Communication Interfaces
        1. 4.3.6.1 CAN
        2. 4.3.6.2 GEMAC_CPSW
        3. 4.3.6.3 I2C
        4. 4.3.6.4 McASP
        5. 4.3.6.5 SPI
        6. 4.3.6.6 UART
        7. 4.3.6.7 USB
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points (OPPs)
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  Thermal Resistance Characteristics for ZCE and ZCZ Packages
    9. 5.9  External Capacitors
      1. 5.9.1 Voltage Decoupling Capacitors
        1. 5.9.1.1 Core Voltage Decoupling Capacitors
        2. 5.9.1.2 I/O and Analog Voltage Decoupling Capacitors
      2. 5.9.2 Output Capacitors
    10. 5.10 Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
  6. 6Power and Clocking
    1. 6.1 Power Supplies
      1. 6.1.1 Power Supply Slew Rate Requirement
      2. 6.1.2 Power-Down Sequencing
      3. 6.1.3 VDD_MPU_MON Connections
      4. 6.1.4 Digital Phase-Locked Loop Power Supply Requirements
    2. 6.2 Clock Specifications
      1. 6.2.1 Input Clock Specifications
      2. 6.2.2 Input Clock Requirements
        1. 6.2.2.1 OSC0 Internal Oscillator Clock Source
          1. Table 6-2 OSC0 Crystal Circuit Requirements
          2. Table 6-3 OSC0 Crystal Circuit Characteristics
        2. 6.2.2.2 OSC0 LVCMOS Digital Clock Source
        3. 6.2.2.3 OSC1 Internal Oscillator Clock Source
          1. Table 6-5 OSC1 Crystal Circuit Requirements
          2. Table 6-6 OSC1 Crystal Circuit Characteristics
        4. 6.2.2.4 OSC1 LVCMOS Digital Clock Source
        5. 6.2.2.5 OSC1 Not Used
      3. 6.2.3 Output Clock Specifications
      4. 6.2.4 Output Clock Characteristics
        1. 6.2.4.1 CLKOUT1
        2. 6.2.4.2 CLKOUT2
  7. 7Peripheral Information and Timings
    1. 7.1  Parameter Information
      1. 7.1.1 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  OPP50 Support
    4. 7.4  Controller Area Network (CAN)
      1. 7.4.1 DCAN Electrical Data and Timing
        1. Table 7-1 DCAN Timing Conditions
        2. Table 7-2 Timing Requirements for DCANx Receive
        3. Table 7-3 Switching Characteristics for DCANx Transmit
    5. 7.5  DMTimer
      1. 7.5.1 DMTimer Electrical Data and Timing
        1. Table 7-4 DMTimer Timing Conditions
        2. Table 7-5 Timing Requirements for DMTimer [1-7]
        3. Table 7-6 Switching Characteristics for DMTimer [4-7]
    6. 7.6  Ethernet Media Access Controller (EMAC) and Switch
      1. 7.6.1 EMAC and Switch Electrical Data and Timing
        1. Table 7-7 EMAC and Switch Timing Conditions
        2. 7.6.1.1   EMAC/Switch MDIO Electrical Data and Timing
          1. Table 7-8  Timing Requirements for MDIO_DATA
          2. Table 7-9  Switching Characteristics for MDIO_CLK
          3. Table 7-10 Switching Characteristics for MDIO_DATA
        3. 7.6.1.2   EMAC and Switch MII Electrical Data and Timing
          1. Table 7-11 Timing Requirements for GMII[x]_RXCLK - MII Mode
          2. Table 7-12 Timing Requirements for GMII[x]_TXCLK - MII Mode
          3. Table 7-13 Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
          4. Table 7-14 Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
        4. 7.6.1.3   EMAC and Switch RMII Electrical Data and Timing
          1. Table 7-15 Timing Requirements for RMII[x]_REFCLK - RMII Mode
          2. Table 7-16 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
          3. Table 7-17 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
        5. 7.6.1.4   EMAC and Switch RGMII Electrical Data and Timing
          1. Table 7-18 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
          2. Table 7-19 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
          3. Table 7-20 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
          4. Table 7-21 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
    7. 7.7  External Memory Interfaces
      1. 7.7.1 General-Purpose Memory Controller (GPMC)
        1. 7.7.1.1 GPMC and NOR Flash—Synchronous Mode
          1. Table 7-22 GPMC and NOR Flash Timing Conditions—Synchronous Mode
          2. Table 7-23 GPMC and NOR Flash Timing Requirements—Synchronous Mode
          3. Table 7-24 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
        2. 7.7.1.2 GPMC and NOR Flash—Asynchronous Mode
          1. Table 7-25 GPMC and NOR Flash Timing Conditions—Asynchronous Mode
          2. Table 7-26 GPMC and NOR Flash Internal Timing Requirements—Asynchronous Mode
          3. Table 7-27 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
          4. Table 7-28 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
        3. 7.7.1.3 GPMC and NAND Flash—Asynchronous Mode
          1. Table 7-29 GPMC and NAND Flash Timing Conditions—Asynchronous Mode
          2. Table 7-30 GPMC and NAND Flash Internal Timing Requirements—Asynchronous Mode
          3. Table 7-31 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
          4. Table 7-32 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
      2. 7.7.2 mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
        1. 7.7.2.1 mDDR (LPDDR) Routing Guidelines
          1. 7.7.2.1.1 Board Designs
          2. 7.7.2.1.2 LPDDR Interface
            1. 7.7.2.1.2.1 LPDDR Interface Schematic
            2. 7.7.2.1.2.2 Compatible JEDEC LPDDR Devices
              1. Table 7-34 Compatible JEDEC LPDDR Devices (Per Interface)
            3. 7.7.2.1.2.3 PCB Stackup
            4. 7.7.2.1.2.4 Placement
            5. 7.7.2.1.2.5 LPDDR Keepout Region
            6. 7.7.2.1.2.6 Bulk Bypass Capacitors
            7. 7.7.2.1.2.7 High-Speed Bypass Capacitors
            8. 7.7.2.1.2.8 Net Classes
            9. 7.7.2.1.2.9 LPDDR Signal Termination
          3. 7.7.2.1.3 LPDDR CK and ADDR_CTRL Routing
        2. 7.7.2.2 DDR2 Routing Guidelines
          1. 7.7.2.2.1 Board Designs
          2. 7.7.2.2.2 DDR2 Interface
            1. 7.7.2.2.2.1  DDR2 Interface Schematic
            2. 7.7.2.2.2.2  Compatible JEDEC DDR2 Devices
              1. Table 7-46 Compatible JEDEC DDR2 Devices (Per Interface)
            3. 7.7.2.2.2.3  PCB Stackup
            4. 7.7.2.2.2.4  Placement
            5. 7.7.2.2.2.5  DDR2 Keepout Region
            6. 7.7.2.2.2.6  Bulk Bypass Capacitors
            7. 7.7.2.2.2.7  High-Speed (HS) Bypass Capacitors
            8. 7.7.2.2.2.8  Net Classes
            9. 7.7.2.2.2.9  DDR2 Signal Termination
            10. 7.7.2.2.2.10 DDR_VREF Routing
          3. 7.7.2.2.3 DDR2 CK and ADDR_CTRL Routing
        3. 7.7.2.3 DDR3 and DDR3L Routing Guidelines
          1. 7.7.2.3.1 Board Designs
            1. 7.7.2.3.1.1 DDR3 versus DDR2
          2. 7.7.2.3.2 DDR3 Device Combinations
          3. 7.7.2.3.3 DDR3 Interface
            1. 7.7.2.3.3.1  DDR3 Interface Schematic
            2. 7.7.2.3.3.2  Compatible JEDEC DDR3 Devices
            3. 7.7.2.3.3.3  PCB Stackup
            4. 7.7.2.3.3.4  Placement
            5. 7.7.2.3.3.5  DDR3 Keepout Region
            6. 7.7.2.3.3.6  Bulk Bypass Capacitors
            7. 7.7.2.3.3.7  High-Speed Bypass Capacitors
              1. 7.7.2.3.3.7.1 Return Current Bypass Capacitors
            8. 7.7.2.3.3.8  Net Classes
            9. 7.7.2.3.3.9  DDR3 Signal Termination
            10. 7.7.2.3.3.10 DDR_VREF Routing
            11. 7.7.2.3.3.11 VTT
          4. 7.7.2.3.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
            1. 7.7.2.3.4.1 Two DDR3 Devices
              1. 7.7.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
              2. 7.7.2.3.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
            2. 7.7.2.3.4.2 One DDR3 Device
              1. 7.7.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device
              2. 7.7.2.3.4.2.2 CK and ADDR_CTRL Routing, One DDR3 Device
          5. 7.7.2.3.5 Data Topologies and Routing Definition
            1. 7.7.2.3.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
            2. 7.7.2.3.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
          6. 7.7.2.3.6 Routing Specification
            1. 7.7.2.3.6.1 CK and ADDR_CTRL Routing Specification
            2. 7.7.2.3.6.2 DQS[x] and DQ[x] Routing Specification
    8. 7.8  I2C
      1. 7.8.1 I2C Electrical Data and Timing
        1. Table 7-70 I2C Timing Conditions – Slave Mode
        2. Table 7-71 Timing Requirements for I2C Input Timings
        3. Table 7-72 Switching Characteristics for I2C Output Timings
    9. 7.9  JTAG Electrical Data and Timing
      1. Table 7-73 JTAG Timing Conditions
      2. Table 7-74 Timing Requirements for JTAG
      3. Table 7-75 Switching Characteristics for JTAG
    10. 7.10 LCD Controller (LCDC)
      1. Table 7-76 LCD Controller Timing Conditions
      2. 7.10.1     LCD Interface Display Driver (LIDD Mode)
        1. Table 7-77 Timing Requirements for LCD LIDD Mode
        2. Table 7-78 Switching Characteristics for LCD LIDD Mode
      3. 7.10.2     LCD Raster Mode
        1. Table 7-79 Switching Characteristics for LCD Raster Mode
    11. 7.11 Multichannel Audio Serial Port (McASP)
      1. 7.11.1 McASP Device-Specific Information
      2. 7.11.2 McASP Electrical Data and Timing
        1. Table 7-80 McASP Timing Conditions
        2. Table 7-81 Timing Requirements for McASP
        3. Table 7-82 Switching Characteristics for McASP
    12. 7.12 Multichannel Serial Port Interface (McSPI)
      1. 7.12.1 McSPI Electrical Data and Timing
        1. 7.12.1.1 McSPI—Slave Mode
          1. Table 7-83 McSPI Timing Conditions – Slave Mode
          2. Table 7-84 Timing Requirements for McSPI Input Timings—Slave Mode
          3. Table 7-85 Switching Characteristics for McSPI Output Timings—Slave Mode
        2. 7.12.1.2 McSPI—Master Mode
          1. Table 7-86 McSPI Timing Conditions – Master Mode
          2. Table 7-87 Timing Requirements for McSPI Input Timings – Master Mode
          3. Table 7-88 Switching Characteristics for McSPI Output Timings – Master Mode
    13. 7.13 Multimedia Card (MMC) Interface
      1. 7.13.1 MMC Electrical Data and Timing
        1. Table 7-89 MMC Timing Conditions
        2. Table 7-90 Timing Requirements for MMC[x]_CMD and MMC[x]_DAT[7:0]
        3. Table 7-91 Switching Characteristics for MMC[x]_CLK
        4. Table 7-92 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—Standard Mode
        5. Table 7-93 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—High-Speed Mode
    14. 7.14 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      1. 7.14.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. Table 7-94 PRU-ICSS PRU Timing Conditions
        2. 7.14.1.1   PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
          1. Table 7-95 PRU-ICSS PRU Timing Requirements - Direct Input Mode
          2. Table 7-96 PRU-ICSS PRU Switching Requirements – Direct Output Mode
        3. 7.14.1.2   PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
          1. Table 7-97 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
        4. 7.14.1.3   PRU-ICSS PRU Shift Mode Electrical Data and Timing
          1. Table 7-98 PRU-ICSS PRU Timing Requirements – Shift In Mode
          2. Table 7-99 PRU-ICSS PRU Switching Requirements - Shift Out Mode
      2. 7.14.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. Table 7-100 PRU-ICSS ECAT Timing Conditions
        2. 7.14.2.1    PRU-ICSS ECAT Electrical Data and Timing
          1. Table 7-101 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
          2. Table 7-102 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
          3. Table 7-103 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
          4. Table 7-104 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
          5. Table 7-105 PRU-ICSS ECAT Switching Requirements - Digital I/Os
      3. 7.14.3 PRU-ICSS MII_RT and Switch
        1. Table 7-106 PRU-ICSS MII_RT Switch Timing Conditions
        2. 7.14.3.1    PRU-ICSS MDIO Electrical Data and Timing
          1. Table 7-107 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
          2. Table 7-108 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
          3. Table 7-109 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
        3. 7.14.3.2    PRU-ICSS MII_RT Electrical Data and Timing
          1. Table 7-110 PRU-ICSS MII_RT Timing Requirements – MII_RXCLK
          2. Table 7-111 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
          3. Table 7-112 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
          4. Table 7-113 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
      4. 7.14.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
        1. Table 7-114 UART Timing Conditions
        2. Table 7-115 Timing Requirements for PRU-ICSS UART Receive
        3. Table 7-116 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
      1. 7.15.1 UART Electrical Data and Timing
        1. Table 7-117 UART Timing Conditions
        2. Table 7-118 Timing Requirements for UARTx Receive
        3. Table 7-119 Switching Characteristics for UARTx Transmit
      2. 7.15.2 UART IrDA Interface
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Via Channel
    2. 9.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCZ|324
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Device Comparison

Table 3-1 lists the features supported across different AM335x devices.

Table 3-1 Device Features Comparison

FUNCTION AM3351 AM3352 AM3354 AM3356 AM3357 AM3358 AM3359
ARM Cortex-A8 Yes Yes Yes Yes Yes Yes Yes
Frequency(1) 300 MHz
600 MHz		 300 MHz
600 MHz
800 MHz
1000 MHz		 600 MHz
800 MHz
1000 MHz		 300 MHz
600 MHz
800 MHz		 300 MHz
600 MHz
800 MHz		 600 MHz
800 MHz
1000 MHz		 800 MHz
MIPS(2) 600
1200		 600
1200
1600
2000		 1200
1600
2000		 600
1200
1600		 600
1200
1600		 1200
1600
2000		 1600
On-chip L1 cache 64KB 64KB 64KB 64KB 64KB 64KB 64KB
On-chip L2 cache 256KB 256KB 256KB 256KB 256KB 256KB 256KB
Graphics accelerator (SGX530) — — 3D — — 3D 3D
Hardware acceleration Crypto accelerator Crypto accelerator Crypto accelerator Crypto accelerator Crypto accelerator Crypto accelerator Crypto accelerator
Programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) — — — Features including basic Industrial protocols;
ZCE: Limited PRU I/Os pinned out		 Features including all Industrial protocols Features including basic Industrial protocols Features including all Industrial protocols
On-chip memory 128KB 128KB 128KB 128KB 128KB 128KB 128KB
Display options LCD LCD LCD LCD LCD LCD LCD
General-purpose memory 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM)
DRAM(3) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800) 1 16-bit (LPDDR-400, DDR2-532, DDR3-800)
Universal serial bus (USB) ZCE: 1 port ZCE: 1 port
ZCZ: 2 ports		 ZCE: 1 port
ZCZ: 2 ports		 ZCE: 1 port
ZCZ: 2 ports		 No ZCE Available
ZCZ: 2 ports		 No ZCE Available
ZCZ: 2 ports		 No ZCE Available
ZCZ: 2 ports
Ethernet media access controller (EMAC) with 2-port switch 10/100/1000
ZCE: 1 port		 10/100/1000
ZCE: 1 port
ZCZ: 2 ports		 10/100/1000
ZCE: 1 port
ZCZ: 2 ports		 10/100/1000
ZCE: 1 port
ZCZ: 2 ports		 10/100/1000
No ZCE Available
ZCZ: 2 ports		 10/100/1000
No ZCE Available
ZCZ: 2 ports		 10/100/1000
No ZCE Available
ZCZ: 2 ports
Multimedia card (MMC) 3 3 3 3 3 3 3
Controller-area network (CAN) — 2 2 2 2 2 2
Universal asynchronous receiver and transmitter (UART) 6 6 6 6 6 6 6
Analog-to-digital converter (ADC) 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit
Enhanced high-resolution PWM modules (eHRPWM) 3 3 3 3 3 3 3
Enhanced capture modules (eCAP) 3 3 3 3 3 3 3
Enhanced quadrature encoder pulse (eQEP) 3 3 3 3 3 3 3
Real-time clock (RTC) 1 1 1 1 1 1 1
Inter-integrated circuit (I2C) 3 3 3 3 3 3 3
Multichannel audio serial port (McASP) 2 2 2 2 2 2 2
Multichannel serial port interface (McSPI) 2 2 2 2 2 2 2
Enhanced direct memory access (EDMA) 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch
Input/output (I/O) supply 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V
Operating temperature range 0 to 90°C
–40 to 105°C		 -40 to 125°C(4)
–40 to 105°C
–40 to 90°C
0 to 90°C		 –40 to 105°C
–40 to 90°C
0 to 90°C		 –40 to 105°C
–40 to 90°C
0 to 90°C		 –40 to 105°C
–40 to 90°C		 –40 to 105°C
–40 to 90°C
0 to 90°C		 –40 to 105°C
–40 to 90°C
DEV_FEATURE register value(5) 0x00FC0302 0x00FC0382 0x20FC0382 0x00FD0383 0x00FF0383 0x20FD0383 0x20FF0383
  1. Frequencies listed correspond to silicon revision 2.x. Earlier silicon revisions support 275 MHz, 500 MHz, 600 MHz, and 720 MHz.
  2. MIPS listed correspond to silicon revision 2.x. Earlier silicon revisions support 560, 1000, 1200, and 1440.
  3. DRAM speeds listed are data rates.
  4. Industrial extended temperature only supported for 300-MHz and 600-MHz frequencies.
  5. For more details about the DEV_FEATURE register, see the AM335x TRM.